Merge from projects/mips to head by hand:

Copy sys/dev/rmi to sys/mips/rmi/dev [sic].  For devices that are on
only one SoC, or family of SoC, we place them under sys/<vendor>/dev.
I'll fix the build problems this causes as best I can since rmi kernel
require external toolchains due to lack of support for rmi op-codes in
the ancient binutils we have in the tree.

sys/mips/rmi/dev/sec/rmilib.h

@@ -0,0 +1,997 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#ifndef _RMILIB_H_
+#define _RMILIB_H_
+
+#include <dev/rmi/sec/desc.h>
+#include <mips/xlr/iomap.h>
+
+/*#define XLR_SEC_CMD_DEBUG*/
+
+#ifdef XLR_SEC_CMD_DEBUG
+#define DPRINT  printf
+#define XLR_SEC_CMD_DIAG(fmt, args...) { \
+                DPRINT(fmt, ##args); \
+        }
+#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec) { \
+                decode_symkey_desc ((desc), (vec)); \
+        }
+#else
+#define DPRINT(fmt, args...)
+#define XLR_SEC_CMD_DIAG(fmt, args...)
+#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec)
+#endif
+
+
+
+
+
+
+/*
+#include <mips/include/pmap.h>
+
+#define OS_ALLOC_KERNEL(size) kmalloc((size), GFP_KERNEL)
+#define virt_to_phys(x)  vtophys((vm_offset_t)(x))
+*/
+/*
+ * Cryptographic parameter definitions
+ */
+#define XLR_SEC_DES_KEY_LENGTH        8	/* Bytes */
+#define XLR_SEC_3DES_KEY_LENGTH       24	/* Bytes */
+#define XLR_SEC_AES128_KEY_LENGTH     16	/* Bytes */
+#define XLR_SEC_AES192_KEY_LENGTH     24	/* Bytes */
+#define XLR_SEC_AES256_KEY_LENGTH     32	/* Bytes */
+#define XLR_SEC_AES128F8_KEY_LENGTH   32	/* Bytes */
+#define XLR_SEC_AES192F8_KEY_LENGTH   48	/* Bytes */
+#define XLR_SEC_AES256F8_KEY_LENGTH   64	/* Bytes */
+#define XLR_SEC_KASUMI_F8_KEY_LENGTH  16	/* Bytes */
+#define XLR_SEC_MAX_CRYPT_KEY_LENGTH  XLR_SEC_AES256F8_KEY_LENGTH
+
+
+#define XLR_SEC_DES_IV_LENGTH         8	/* Bytes */
+#define XLR_SEC_AES_IV_LENGTH         16	/* Bytes */
+#define XLR_SEC_ARC4_IV_LENGTH        0	/* Bytes */
+#define XLR_SEC_KASUMI_F8_IV_LENGTH   16	/* Bytes */
+#define XLR_SEC_MAX_IV_LENGTH         16	/* Bytes */
+#define XLR_SEC_IV_LENGTH_BYTES       8	/* Bytes */
+
+#define XLR_SEC_AES_BLOCK_SIZE        16	/* Bytes */
+#define XLR_SEC_DES_BLOCK_SIZE        8	/* Bytes */
+#define XLR_SEC_3DES_BLOCK_SIZE       8	/* Bytes */
+
+#define XLR_SEC_MD5_BLOCK_SIZE        64	/* Bytes */
+#define XLR_SEC_SHA1_BLOCK_SIZE       64	/* Bytes */
+#define XLR_SEC_SHA256_BLOCK_SIZE     64	/* Bytes */
+#define XLR_SEC_SHA384_BLOCK_SIZE     128	/* Bytes */
+#define XLR_SEC_SHA512_BLOCK_SIZE     128	/* Bytes */
+#define XLR_SEC_GCM_BLOCK_SIZE        16	/* XXX: Bytes */
+#define XLR_SEC_KASUMI_F9_BLOCK_SIZE  16	/* XXX: Bytes */
+#define XLR_SEC_MAX_BLOCK_SIZE        64	/* Max of MD5/SHA */
+#define XLR_SEC_MD5_LENGTH            16	/* Bytes */
+#define XLR_SEC_SHA1_LENGTH           20	/* Bytes */
+#define XLR_SEC_SHA256_LENGTH         32	/* Bytes */
+#define XLR_SEC_SHA384_LENGTH         64	/* Bytes */
+#define XLR_SEC_SHA512_LENGTH         64	/* Bytes */
+#define XLR_SEC_GCM_LENGTH            16	/* Bytes */
+#define XLR_SEC_KASUMI_F9_LENGTH      16	/* Bytes */
+#define XLR_SEC_KASUMI_F9_RESULT_LENGTH 4	/* Bytes */
+#define XLR_SEC_HMAC_LENGTH           64	/* Max of MD5/SHA/SHA256 */
+#define XLR_SEC_MAX_AUTH_KEY_LENGTH   XLR_SEC_SHA512_BLOCK_SIZE
+#define XLR_SEC_MAX_RC4_STATE_SIZE    264	/* char s[256], int i, int j */
+
+/* Status code is used by the SRL to indicate status */
+typedef unsigned int xlr_sec_status_t;
+
+/*
+ * Status codes
+ */
+#define XLR_SEC_STATUS_SUCCESS              0
+#define XLR_SEC_STATUS_NO_DEVICE           -1
+#define XLR_SEC_STATUS_TIMEOUT             -2
+#define XLR_SEC_STATUS_INVALID_PARAMETER   -3
+#define XLR_SEC_STATUS_DEVICE_FAILED       -4
+#define XLR_SEC_STATUS_DEVICE_BUSY         -5
+#define XLR_SEC_STATUS_NO_RESOURCE         -6
+#define XLR_SEC_STATUS_CANCELLED           -7
+
+/*
+ * Flags
+ */
+#define XLR_SEC_FLAGS_HIGH_PRIORITY         1
+
+/* Error code is used to indicate any errors */
+typedef int xlr_sec_error_t;
+
+/*
+ */
+#define XLR_SEC_ERR_NONE                    0
+#define XLR_SEC_ERR_CIPHER_OP              -1
+#define XLR_SEC_ERR_CIPHER_TYPE            -2
+#define XLR_SEC_ERR_CIPHER_MODE            -3
+#define XLR_SEC_ERR_CIPHER_INIT            -4
+#define XLR_SEC_ERR_DIGEST_TYPE            -5
+#define XLR_SEC_ERR_DIGEST_INIT            -6
+#define XLR_SEC_ERR_DIGEST_SRC             -7
+#define XLR_SEC_ERR_CKSUM_TYPE             -8
+#define XLR_SEC_ERR_CKSUM_SRC              -9
+#define XLR_SEC_ERR_ALLOC                  -10
+#define XLR_SEC_ERR_CONTROL_VECTOR         -11
+#define XLR_SEC_ERR_LOADHMACKEY_MODE       -12
+#define XLR_SEC_ERR_PADHASH_MODE           -13
+#define XLR_SEC_ERR_HASHBYTES_MODE         -14
+#define XLR_SEC_ERR_NEXT_MODE              -15
+#define XLR_SEC_ERR_PKT_IV_MODE            -16
+#define XLR_SEC_ERR_LASTWORD_MODE          -17
+#define XLR_SEC_ERR_PUBKEY_OP              -18
+#define XLR_SEC_ERR_SYMKEY_MSGSND          -19
+#define XLR_SEC_ERR_PUBKEY_MSGSND          -20
+#define XLR_SEC_ERR_SYMKEY_GETSEM          -21
+#define XLR_SEC_ERR_PUBKEY_GETSEM          -22
+
+/*
+ * Descriptor Vector quantities
+ *  (helps to identify descriptor type per operation)
+ */
+#define XLR_SEC_VECTOR_CIPHER_DES             0x0001
+#define XLR_SEC_VECTOR_CIPHER_3DES            0x0002
+#define XLR_SEC_VECTOR_CIPHER_AES128          0x0004
+#define XLR_SEC_VECTOR_CIPHER_AES192          0x0008
+#define XLR_SEC_VECTOR_CIPHER_AES256          0x0010
+#define XLR_SEC_VECTOR_CIPHER_ARC4            0x0020
+#define XLR_SEC_VECTOR_CIPHER_AES             (XLR_SEC_VECTOR_CIPHER_AES128 | \
+                                           XLR_SEC_VECTOR_CIPHER_AES192 | \
+                                           XLR_SEC_VECTOR_CIPHER_AES256)
+#define XLR_SEC_VECTOR_CIPHER                 (XLR_SEC_VECTOR_CIPHER_DES | \
+                                           XLR_SEC_VECTOR_CIPHER_3DES | \
+                                           XLR_SEC_VECTOR_CIPHER_AES128 | \
+                                           XLR_SEC_VECTOR_CIPHER_AES192 | \
+                                           XLR_SEC_VECTOR_CIPHER_AES256 | \
+                                           XLR_SEC_VECTOR_CIPHER_ARC4)
+
+#define XLR_SEC_VECTOR_HMAC                   0x0040
+#define XLR_SEC_VECTOR_MAC                    0x0080
+#define XLR_SEC_VECTOR_MODE_CTR_CFB           0x0100
+#define XLR_SEC_VECTOR_MODE_ECB_CBC_OFB       0x0200
+#define XLR_SEC_VECTOR_MODE_ECB_CBC           0x0400
+#define XLR_SEC_VECTOR_STATE                  0x0800
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8       0x01000
+#define XLR_SEC_VECTOR_HMAC2                  0x02000
+#define XLR_SEC_VECTOR_GCM                    0x04000
+#define XLR_SEC_VECTOR_F9                     0x08000
+#define XLR_SEC_VECTOR_MODE_F8                0x10000
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC)
+#define XLR_SEC_VECTOR_CIPHER_ARC4__STATE  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_STATE)
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9  \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_F9)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC  \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2  \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC2)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM  \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_GCM)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__F9  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE  \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
+
+/*
+ * Cipher Modes
+ */
+typedef enum {
+	XLR_SEC_CIPHER_MODE_NONE = 0,
+	XLR_SEC_CIPHER_MODE_PASS = 1,
+	XLR_SEC_CIPHER_MODE_ECB,
+	XLR_SEC_CIPHER_MODE_CBC,
+	XLR_SEC_CIPHER_MODE_OFB,
+	XLR_SEC_CIPHER_MODE_CTR,
+	XLR_SEC_CIPHER_MODE_CFB,
+	XLR_SEC_CIPHER_MODE_F8
+}    XLR_SEC_CIPHER_MODE;
+
+typedef enum {
+	XLR_SEC_CIPHER_OP_NONE = 0,
+	XLR_SEC_CIPHER_OP_ENCRYPT = 1,
+	XLR_SEC_CIPHER_OP_DECRYPT
+}    XLR_SEC_CIPHER_OP;
+
+typedef enum {
+	XLR_SEC_CIPHER_TYPE_UNSUPPORTED = -1,
+	XLR_SEC_CIPHER_TYPE_NONE = 0,
+	XLR_SEC_CIPHER_TYPE_DES,
+	XLR_SEC_CIPHER_TYPE_3DES,
+	XLR_SEC_CIPHER_TYPE_AES128,
+	XLR_SEC_CIPHER_TYPE_AES192,
+	XLR_SEC_CIPHER_TYPE_AES256,
+	XLR_SEC_CIPHER_TYPE_ARC4,
+	XLR_SEC_CIPHER_TYPE_KASUMI_F8
+}    XLR_SEC_CIPHER_TYPE;
+
+typedef enum {
+	XLR_SEC_CIPHER_INIT_OK = 1,	/* Preserve old Keys */
+	XLR_SEC_CIPHER_INIT_NK	/* Load new Keys */
+}    XLR_SEC_CIPHER_INIT;
+
+
+/*
+ *  Hash Modes
+ */
+typedef enum {
+	XLR_SEC_DIGEST_TYPE_UNSUPPORTED = -1,
+	XLR_SEC_DIGEST_TYPE_NONE = 0,
+	XLR_SEC_DIGEST_TYPE_MD5,
+	XLR_SEC_DIGEST_TYPE_SHA1,
+	XLR_SEC_DIGEST_TYPE_SHA256,
+	XLR_SEC_DIGEST_TYPE_SHA384,
+	XLR_SEC_DIGEST_TYPE_SHA512,
+	XLR_SEC_DIGEST_TYPE_GCM,
+	XLR_SEC_DIGEST_TYPE_KASUMI_F9,
+	XLR_SEC_DIGEST_TYPE_HMAC_MD5,
+	XLR_SEC_DIGEST_TYPE_HMAC_SHA1,
+	XLR_SEC_DIGEST_TYPE_HMAC_SHA256,
+	XLR_SEC_DIGEST_TYPE_HMAC_SHA384,
+	XLR_SEC_DIGEST_TYPE_HMAC_SHA512,
+	XLR_SEC_DIGEST_TYPE_HMAC_AES_CBC,
+	XLR_SEC_DIGEST_TYPE_HMAC_AES_XCBC
+}    XLR_SEC_DIGEST_TYPE;
+
+typedef enum {
+	XLR_SEC_DIGEST_INIT_OLDKEY = 1,	/* Preserve old key HMAC key stored in
+					 * ID registers (moot if HASH.HMAC ==
+					 * 0) */
+	XLR_SEC_DIGEST_INIT_NEWKEY	/* Load new HMAC key from memory ctrl
+					 * section to ID registers */
+}    XLR_SEC_DIGEST_INIT;
+
+typedef enum {
+	XLR_SEC_DIGEST_SRC_DMA = 1,	/* DMA channel */
+	XLR_SEC_DIGEST_SRC_CPHR	/* Cipher if word count exceeded
+				 * Cipher_Offset; else DMA */
+}    XLR_SEC_DIGEST_SRC;
+
+/*
+ *  Checksum Modes
+ */
+typedef enum {
+	XLR_SEC_CKSUM_TYPE_NOP = 1,
+	XLR_SEC_CKSUM_TYPE_IP
+}    XLR_SEC_CKSUM_TYPE;
+
+typedef enum {
+	XLR_SEC_CKSUM_SRC_DMA = 1,
+	XLR_SEC_CKSUM_SRC_CIPHER
+}    XLR_SEC_CKSUM_SRC;
+
+/*
+ *  Packet Modes
+ */
+typedef enum {
+	XLR_SEC_LOADHMACKEY_MODE_OLD = 1,
+	XLR_SEC_LOADHMACKEY_MODE_LOAD
+}    XLR_SEC_LOADHMACKEY_MODE;
+
+typedef enum {
+	XLR_SEC_PADHASH_PADDED = 1,
+	XLR_SEC_PADHASH_PAD
+}    XLR_SEC_PADHASH_MODE;
+
+typedef enum {
+	XLR_SEC_HASHBYTES_ALL8 = 1,
+	XLR_SEC_HASHBYTES_MSB,
+	XLR_SEC_HASHBYTES_MSW
+}    XLR_SEC_HASHBYTES_MODE;
+
+typedef enum {
+	XLR_SEC_NEXT_FINISH = 1,
+	XLR_SEC_NEXT_DO
+}    XLR_SEC_NEXT_MODE;
+
+typedef enum {
+	XLR_SEC_PKT_IV_OLD = 1,
+	XLR_SEC_PKT_IV_NEW
+}    XLR_SEC_PKT_IV_MODE;
+
+typedef enum {
+	XLR_SEC_LASTWORD_128 = 1,
+	XLR_SEC_LASTWORD_96MASK,
+	XLR_SEC_LASTWORD_64MASK,
+	XLR_SEC_LASTWORD_32MASK
+}    XLR_SEC_LASTWORD_MODE;
+
+typedef enum {
+	XLR_SEC_CFB_MASK_REGULAR_CTR = 0,
+	XLR_SEC_CFB_MASK_CCMP,
+	XLR_SEC_CFB_MASK_GCM_WITH_SCI,
+	XLR_SEC_CFB_MASK_GCM_WITHOUT_SCI
+}    XLR_SEC_CFB_MASK_MODE;
+
+/*
+ *  Public Key
+ */
+typedef enum {
+	RMIPK_BLKWIDTH_512 = 1,
+	RMIPK_BLKWIDTH_1024
+}    RMIPK_BLKWIDTH_MODE;
+
+typedef enum {
+	RMIPK_LDCONST_OLD = 1,
+	RMIPK_LDCONST_NEW
+}    RMIPK_LDCONST_MODE;
+
+
+typedef struct xlr_sec_io_s {
+	unsigned int command;
+	unsigned int result_status;
+	unsigned int flags;
+	unsigned int session_num;
+	unsigned int use_callback;
+	unsigned int time_us;
+	unsigned int user_context[2];	/* usable for anything by caller */
+	unsigned int command_context;	/* Context (ID) of this command). */
+	unsigned char initial_vector[XLR_SEC_MAX_IV_LENGTH];
+	unsigned char crypt_key[XLR_SEC_MAX_CRYPT_KEY_LENGTH];
+	unsigned char mac_key[XLR_SEC_MAX_AUTH_KEY_LENGTH];
+
+	XLR_SEC_CIPHER_OP cipher_op;
+	XLR_SEC_CIPHER_MODE cipher_mode;
+	XLR_SEC_CIPHER_TYPE cipher_type;
+	XLR_SEC_CIPHER_INIT cipher_init;
+	unsigned int cipher_offset;
+
+	XLR_SEC_DIGEST_TYPE digest_type;
+	XLR_SEC_DIGEST_INIT digest_init;
+	XLR_SEC_DIGEST_SRC digest_src;
+	unsigned int digest_offset;
+
+	XLR_SEC_CKSUM_TYPE cksum_type;
+	XLR_SEC_CKSUM_SRC cksum_src;
+	unsigned int cksum_offset;
+
+	XLR_SEC_LOADHMACKEY_MODE pkt_hmac;
+	XLR_SEC_PADHASH_MODE pkt_hash;
+	XLR_SEC_HASHBYTES_MODE pkt_hashbytes;
+	XLR_SEC_NEXT_MODE pkt_next;
+	XLR_SEC_PKT_IV_MODE pkt_iv;
+	XLR_SEC_LASTWORD_MODE pkt_lastword;
+
+	unsigned int nonce;
+	unsigned int cfb_mask;
+
+	unsigned int iv_offset;
+	unsigned short pad_type;
+	unsigned short rc4_key_len;
+
+	unsigned int num_packets;
+	unsigned int num_fragments;
+
+	uint64_t source_buf;
+	unsigned int source_buf_size;
+	uint64_t dest_buf;
+	unsigned int dest_buf_size;
+
+	uint64_t auth_dest;
+	uint64_t cksum_dest;
+
+	unsigned short rc4_loadstate;
+	unsigned short rc4_savestate;
+	uint64_t rc4_state;
+
+}            xlr_sec_io_t, *xlr_sec_io_pt;
+
+
+#define XLR_SEC_SESSION(sid)   ((sid) & 0x000007ff)
+#define XLR_SEC_SID(crd,ses)   (((crd) << 28) | ((ses) & 0x7ff))
+
+/*
+ *  Length values for cryptography
+ */
+/*
+#define XLR_SEC_DES_KEY_LENGTH     8
+#define XLR_SEC_3DES_KEY_LENGTH        24
+#define XLR_SEC_MAX_CRYPT_KEY_LENGTH   XLR_SEC_3DES_KEY_LENGTH
+#define XLR_SEC_IV_LENGTH          8
+#define XLR_SEC_AES_IV_LENGTH      16
+#define XLR_SEC_MAX_IV_LENGTH      XLR_SEC_AES_IV_LENGTH
+*/
+
+#define SEC_MAX_FRAG_LEN 16000
+
+struct xlr_sec_command {
+	uint16_t session_num;
+	struct cryptop *crp;
+	struct cryptodesc *enccrd, *maccrd;
+
+	xlr_sec_io_t op;
+};
+struct xlr_sec_session {
+	uint32_t sessionid;
+	int hs_used;
+	int hs_mlen;
+	struct xlr_sec_command cmd;
+	void *desc_ptr;
+	uint8_t multi_frag_flag;
+};
+
+/*
+ * Holds data specific to rmi security accelerators
+ */
+struct xlr_sec_softc {
+	device_t sc_dev;	/* device backpointer */
+	struct mtx sc_mtx;	/* per-instance lock */
+
+	int32_t sc_cid;
+	struct xlr_sec_session *sc_sessions;
+	int sc_nsessions;
+	xlr_reg_t *mmio;
+};
+
+
+/*
+
+union xlr_sec_operand_t {
+        struct mbuf *m;
+        struct uio *io;
+        void *buf;
+}xlr_sec_operand;
+*/
+
+
+
+
+
+/* this is passed to packet setup to optimize */
+#define XLR_SEC_SETUP_OP_CIPHER              0x00000001
+#define XLR_SEC_SETUP_OP_HMAC                0x00000002
+#define XLR_SEC_SETUP_OP_CIPHER_HMAC         (XLR_SEC_SETUP_OP_CIPHER | XLR_SEC_SETUP_OP_HMAC)
+/* this is passed to control_setup to update w/preserving existing keys */
+#define XLR_SEC_SETUP_OP_PRESERVE_HMAC_KEY    0x80000000
+#define XLR_SEC_SETUP_OP_PRESERVE_CIPHER_KEY  0x40000000
+#define XLR_SEC_SETUP_OP_UPDATE_KEYS          0x00000010
+#define XLR_SEC_SETUP_OP_FLIP_3DES_KEY        0x00000020
+
+
+
+
+
+/*
+ *   Message Ring Specifics
+ */
+
+#define SEC_MSGRING_WORDSIZE      2
+
+
+/*
+ *
+ *
+ * rwR      31  30 29     27 26    24 23      21 20     18
+ *         |  NA  | RSA0Out | Rsa0In | Pipe3Out | Pipe3In | ...
+ *
+ *          17       15 14     12 11      9 8       6 5        3 2       0
+ *         |  Pipe2Out | Pipe2In | Pipe1In | Pipe1In | Pipe0Out | Pipe0In |
+ *
+ * DMA CREDIT REG -
+ *   NUMBER OF CREDITS PER PIPE
+ */
+
+#define SEC_DMA_CREDIT_RSA0_OUT_FOUR   0x20000000
+#define SEC_DMA_CREDIT_RSA0_OUT_TWO    0x10000000
+#define SEC_DMA_CREDIT_RSA0_OUT_ONE    0x08000000
+
+#define SEC_DMA_CREDIT_RSA0_IN_FOUR    0x04000000
+#define SEC_DMA_CREDIT_RSA0_IN_TWO     0x02000000
+#define SEC_DMA_CREDIT_RSA0_IN_ONE     0x01000000
+
+#define SEC_DMA_CREDIT_PIPE3_OUT_FOUR  0x00800000
+#define SEC_DMA_CREDIT_PIPE3_OUT_TWO   0x00400000
+#define SEC_DMA_CREDIT_PIPE3_OUT_ONE   0x00200000
+
+#define SEC_DMA_CREDIT_PIPE3_IN_FOUR   0x00100000
+#define SEC_DMA_CREDIT_PIPE3_IN_TWO    0x00080000
+#define SEC_DMA_CREDIT_PIPE3_IN_ONE    0x00040000
+
+#define SEC_DMA_CREDIT_PIPE2_OUT_FOUR  0x00020000
+#define SEC_DMA_CREDIT_PIPE2_OUT_TWO   0x00010000
+#define SEC_DMA_CREDIT_PIPE2_OUT_ONE   0x00008000
+
+#define SEC_DMA_CREDIT_PIPE2_IN_FOUR   0x00004000
+#define SEC_DMA_CREDIT_PIPE2_IN_TWO    0x00002000
+#define SEC_DMA_CREDIT_PIPE2_IN_ONE    0x00001000
+
+#define SEC_DMA_CREDIT_PIPE1_OUT_FOUR  0x00000800
+#define SEC_DMA_CREDIT_PIPE1_OUT_TWO   0x00000400
+#define SEC_DMA_CREDIT_PIPE1_OUT_ONE   0x00000200
+
+#define SEC_DMA_CREDIT_PIPE1_IN_FOUR   0x00000100
+#define SEC_DMA_CREDIT_PIPE1_IN_TWO    0x00000080
+#define SEC_DMA_CREDIT_PIPE1_IN_ONE    0x00000040
+
+#define SEC_DMA_CREDIT_PIPE0_OUT_FOUR  0x00000020
+#define SEC_DMA_CREDIT_PIPE0_OUT_TWO   0x00000010
+#define SEC_DMA_CREDIT_PIPE0_OUT_ONE   0x00000008
+
+#define SEC_DMA_CREDIT_PIPE0_IN_FOUR   0x00000004
+#define SEC_DMA_CREDIT_PIPE0_IN_TWO    0x00000002
+#define SEC_DMA_CREDIT_PIPE0_IN_ONE    0x00000001
+
+
+/*
+ *  Currently, FOUR credits per PIPE
+ *  0x24924924
+ */
+#define SEC_DMA_CREDIT_CONFIG          SEC_DMA_CREDIT_RSA0_OUT_FOUR | \
+                                       SEC_DMA_CREDIT_RSA0_IN_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE3_OUT_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE3_IN_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE2_OUT_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE2_IN_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE1_OUT_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE1_IN_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE0_OUT_FOUR | \
+                                       SEC_DMA_CREDIT_PIPE0_IN_FOUR
+
+
+
+
+/*
+ * CONFIG2
+ *    31   5         4                   3
+ *   |  NA  | PIPE3_DEF_DBL_ISS | PIPE2_DEF_DBL_ISS | ...
+ *
+ *                 2                   1                   0
+ *   ... | PIPE1_DEF_DBL_ISS | PIPE0_DEF_DBL_ISS | ROUND_ROBIN_MODE |
+ *
+ *  DBL_ISS - mode for SECENG and DMA controller which slows down transfers
+ *             (to be conservativei; 0=Disable,1=Enable).
+ *  ROUND_ROBIN - mode where SECENG dispatches operations to PIPE0-PIPE3
+ *                and all messages are sent to PIPE0.
+ *
+ */
+
+#define SEC_CFG2_PIPE3_DBL_ISS_ON      0x00000010
+#define SEC_CFG2_PIPE3_DBL_ISS_OFF     0x00000000
+#define SEC_CFG2_PIPE2_DBL_ISS_ON      0x00000008
+#define SEC_CFG2_PIPE2_DBL_ISS_OFF     0x00000000
+#define SEC_CFG2_PIPE1_DBL_ISS_ON      0x00000004
+#define SEC_CFG2_PIPE1_DBL_ISS_OFF     0x00000000
+#define SEC_CFG2_PIPE0_DBL_ISS_ON      0x00000002
+#define SEC_CFG2_PIPE0_DBL_ISS_OFF     0x00000000
+#define SEC_CFG2_ROUND_ROBIN_ON        0x00000001
+#define SEC_CFG2_ROUND_ROBIN_OFF       0x00000000
+
+
+enum sec_pipe_config {
+
+	SEC_PIPE_CIPHER_KEY0_L0 = 0x00,
+	SEC_PIPE_CIPHER_KEY0_HI,
+	SEC_PIPE_CIPHER_KEY1_LO,
+	SEC_PIPE_CIPHER_KEY1_HI,
+	SEC_PIPE_CIPHER_KEY2_LO,
+	SEC_PIPE_CIPHER_KEY2_HI,
+	SEC_PIPE_CIPHER_KEY3_LO,
+	SEC_PIPE_CIPHER_KEY3_HI,
+	SEC_PIPE_HMAC_KEY0_LO,
+	SEC_PIPE_HMAC_KEY0_HI,
+	SEC_PIPE_HMAC_KEY1_LO,
+	SEC_PIPE_HMAC_KEY1_HI,
+	SEC_PIPE_HMAC_KEY2_LO,
+	SEC_PIPE_HMAC_KEY2_HI,
+	SEC_PIPE_HMAC_KEY3_LO,
+	SEC_PIPE_HMAC_KEY3_HI,
+	SEC_PIPE_HMAC_KEY4_LO,
+	SEC_PIPE_HMAC_KEY4_HI,
+	SEC_PIPE_HMAC_KEY5_LO,
+	SEC_PIPE_HMAC_KEY5_HI,
+	SEC_PIPE_HMAC_KEY6_LO,
+	SEC_PIPE_HMAC_KEY6_HI,
+	SEC_PIPE_HMAC_KEY7_LO,
+	SEC_PIPE_HMAC_KEY7_HI,
+	SEC_PIPE_NCFBM_LO,
+	SEC_PIPE_NCFBM_HI,
+	SEC_PIPE_INSTR_LO,
+	SEC_PIPE_INSTR_HI,
+	SEC_PIPE_RSVD0,
+	SEC_PIPE_RSVD1,
+	SEC_PIPE_RSVD2,
+	SEC_PIPE_RSVD3,
+
+	SEC_PIPE_DF_PTRS0,
+	SEC_PIPE_DF_PTRS1,
+	SEC_PIPE_DF_PTRS2,
+	SEC_PIPE_DF_PTRS3,
+	SEC_PIPE_DF_PTRS4,
+	SEC_PIPE_DF_PTRS5,
+	SEC_PIPE_DF_PTRS6,
+	SEC_PIPE_DF_PTRS7,
+
+	SEC_PIPE_DU_DATA_IN_LO,
+	SEC_PIPE_DU_DATA_IN_HI,
+	SEC_PIPE_DU_DATA_IN_CTRL,
+	SEC_PIPE_DU_DATA_OUT_LO,
+	SEC_PIPE_DU_DATA_OUT_HI,
+	SEC_PIPE_DU_DATA_OUT_CTRL,
+
+	SEC_PIPE_STATE0,
+	SEC_PIPE_STATE1,
+	SEC_PIPE_STATE2,
+	SEC_PIPE_STATE3,
+	SEC_PIPE_STATE4,
+	SEC_PIPE_INCLUDE_MASK0,
+	SEC_PIPE_INCLUDE_MASK1,
+	SEC_PIPE_INCLUDE_MASK2,
+	SEC_PIPE_INCLUDE_MASK3,
+	SEC_PIPE_INCLUDE_MASK4,
+	SEC_PIPE_EXCLUDE_MASK0,
+	SEC_PIPE_EXCLUDE_MASK1,
+	SEC_PIPE_EXCLUDE_MASK2,
+	SEC_PIPE_EXCLUDE_MASK3,
+	SEC_PIPE_EXCLUDE_MASK4,
+};
+
+
+enum sec_pipe_base_config {
+
+	SEC_PIPE0_BASE = 0x00,
+	SEC_PIPE1_BASE = 0x40,
+	SEC_PIPE2_BASE = 0x80,
+	SEC_PIPE3_BASE = 0xc0
+
+};
+
+enum sec_rsa_config {
+
+	SEC_RSA_PIPE0_DU_DATA_IN_LO = 0x100,
+	SEC_RSA_PIPE0_DU_DATA_IN_HI,
+	SEC_RSA_PIPE0_DU_DATA_IN_CTRL,
+	SEC_RSA_PIPE0_DU_DATA_OUT_LO,
+	SEC_RSA_PIPE0_DU_DATA_OUT_HI,
+	SEC_RSA_PIPE0_DU_DATA_OUT_CTRL,
+	SEC_RSA_RSVD0,
+	SEC_RSA_RSVD1,
+
+	SEC_RSA_PIPE0_STATE0,
+	SEC_RSA_PIPE0_STATE1,
+	SEC_RSA_PIPE0_STATE2,
+	SEC_RSA_PIPE0_INCLUDE_MASK0,
+	SEC_RSA_PIPE0_INCLUDE_MASK1,
+	SEC_RSA_PIPE0_INCLUDE_MASK2,
+	SEC_RSA_PIPE0_EXCLUDE_MASK0,
+	SEC_RSA_PIPE0_EXCLUDE_MASK1,
+	SEC_RSA_PIPE0_EXCLUDE_MASK2,
+	SEC_RSA_PIPE0_EVENT_CTR
+
+};
+
+
+
+
+enum sec_config {
+
+	SEC_DMA_CREDIT = 0x140,
+	SEC_CONFIG1,
+	SEC_CONFIG2,
+	SEC_CONFIG3,
+
+};
+
+
+
+enum sec_debug_config {
+
+	SEC_DW0_DESCRIPTOR0_LO = 0x180,
+	SEC_DW0_DESCRIPTOR0_HI,
+	SEC_DW0_DESCRIPTOR1_LO,
+	SEC_DW0_DESCRIPTOR1_HI,
+	SEC_DW1_DESCRIPTOR0_LO,
+	SEC_DW1_DESCRIPTOR0_HI,
+	SEC_DW1_DESCRIPTOR1_LO,
+	SEC_DW1_DESCRIPTOR1_HI,
+	SEC_DW2_DESCRIPTOR0_LO,
+	SEC_DW2_DESCRIPTOR0_HI,
+	SEC_DW2_DESCRIPTOR1_LO,
+	SEC_DW2_DESCRIPTOR1_HI,
+	SEC_DW3_DESCRIPTOR0_LO,
+	SEC_DW3_DESCRIPTOR0_HI,
+	SEC_DW3_DESCRIPTOR1_LO,
+	SEC_DW3_DESCRIPTOR1_HI,
+
+	SEC_STATE0,
+	SEC_STATE1,
+	SEC_STATE2,
+	SEC_INCLUDE_MASK0,
+	SEC_INCLUDE_MASK1,
+	SEC_INCLUDE_MASK2,
+	SEC_EXCLUDE_MASK0,
+	SEC_EXCLUDE_MASK1,
+	SEC_EXCLUDE_MASK2,
+	SEC_EVENT_CTR
+
+};
+
+
+enum sec_msgring_bucket_config {
+
+	SEC_BIU_CREDITS = 0x308,
+
+	SEC_MSG_BUCKET0_SIZE = 0x320,
+	SEC_MSG_BUCKET1_SIZE,
+	SEC_MSG_BUCKET2_SIZE,
+	SEC_MSG_BUCKET3_SIZE,
+	SEC_MSG_BUCKET4_SIZE,
+	SEC_MSG_BUCKET5_SIZE,
+	SEC_MSG_BUCKET6_SIZE,
+	SEC_MSG_BUCKET7_SIZE,
+};
+
+enum sec_msgring_credit_config {
+
+	SEC_CC_CPU0_0 = 0x380,
+	SEC_CC_CPU1_0 = 0x388,
+	SEC_CC_CPU2_0 = 0x390,
+	SEC_CC_CPU3_0 = 0x398,
+	SEC_CC_CPU4_0 = 0x3a0,
+	SEC_CC_CPU5_0 = 0x3a8,
+	SEC_CC_CPU6_0 = 0x3b0,
+	SEC_CC_CPU7_0 = 0x3b8
+
+};
+
+enum sec_engine_id {
+	SEC_PIPE0,
+	SEC_PIPE1,
+	SEC_PIPE2,
+	SEC_PIPE3,
+	SEC_RSA
+};
+
+enum sec_cipher {
+	SEC_AES256_MODE_HMAC,
+	SEC_AES256_MODE,
+	SEC_AES256_HMAC,
+	SEC_AES256,
+	SEC_AES192_MODE_HMAC,
+	SEC_AES192_MODE,
+	SEC_AES192_HMAC,
+	SEC_AES192,
+	SEC_AES128_MODE_HMAC,
+	SEC_AES128_MODE,
+	SEC_AES128_HMAC,
+	SEC_AES128,
+	SEC_DES_HMAC,
+	SEC_DES,
+	SEC_3DES,
+	SEC_3DES_HMAC,
+	SEC_HMAC
+};
+
+enum sec_msgrng_msg_ctrl_config {
+	SEC_EOP = 5,
+	SEC_SOP = 6,
+};
+
+
+
+void 
+xlr_sec_init(struct xlr_sec_softc *sc);
+
+int 
+xlr_sec_setup(struct xlr_sec_session *ses,
+    struct xlr_sec_command *cmd, symkey_desc_pt desc);
+
+symkey_desc_pt xlr_sec_allocate_desc(void *);
+
+#endif

sys/mips/rmi/dev/sec/rmisec.c

@@ -0,0 +1,603 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/sysctl.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <opencrypto/cryptodev.h>
+#include <sys/random.h>
+
+#include <dev/rmi/sec/rmilib.h>
+
+/*#define RMI_SEC_DEBUG */
+
+
+void xlr_sec_print_data(struct cryptop *crp);
+
+static int xlr_sec_newsession(void *arg, uint32_t * sidp, struct cryptoini *cri);
+static int xlr_sec_freesession(void *arg, uint64_t tid);
+static int xlr_sec_process(void *arg, struct cryptop *crp, int hint);
+
+
+static int xlr_sec_probe(device_t);
+static int xlr_sec_attach(device_t);
+static int xlr_sec_detach(device_t);
+
+
+static device_method_t xlr_sec_methods[] = {
+	/* device interface */
+	DEVMETHOD(device_probe, xlr_sec_probe),
+	DEVMETHOD(device_attach, xlr_sec_attach),
+	DEVMETHOD(device_detach, xlr_sec_detach),
+
+	/* bus interface */
+	DEVMETHOD(bus_print_child, bus_generic_print_child),
+	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+	{0, 0}
+};
+
+static driver_t xlr_sec_driver = {
+	"rmisec",
+	xlr_sec_methods,
+	sizeof(struct xlr_sec_softc)
+};
+static devclass_t xlr_sec_devclass;
+
+DRIVER_MODULE(rmisec, iodi, xlr_sec_driver, xlr_sec_devclass, 0, 0);
+MODULE_DEPEND(rmisec, crypto, 1, 1, 1);
+
+
+
+static int
+xlr_sec_probe(device_t dev)
+{
+	return (BUS_PROBE_DEFAULT);
+
+}
+
+
+/*
+ * Attach an interface that successfully probed.
+ */
+static int
+xlr_sec_attach(device_t dev)
+{
+
+	struct xlr_sec_softc *sc = device_get_softc(dev);
+
+	bzero(sc, sizeof(*sc));
+	sc->sc_dev = dev;
+
+
+	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "rmi crypto driver", MTX_DEF);
+
+	sc->sc_cid = crypto_get_driverid(0);
+	if (sc->sc_cid < 0) {
+		printf("xlr_sec - error : could not get the driver id\n");
+		goto error_exit;
+	}
+	if (crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_DES_CBC\n");
+
+	if (crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_3DES_CBC\n");
+
+	if (crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession,
+	    xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_AES_CBC\n");
+
+	if (crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_ARC4\n");
+
+
+	if (crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_MD5\n");
+
+	if (crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_SHA1\n");
+
+	if (crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_MD5_HMAC\n");
+
+	if (crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
+	    xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc) != 0)
+		printf("register failed for CRYPTO_SHA1_HMAC\n");
+
+
+	xlr_sec_init(sc);
+	return (0);
+
+
+error_exit:
+	return (ENXIO);
+
+}
+
+
+/*
+ * Detach an interface that successfully probed.
+ */
+static int
+xlr_sec_detach(device_t dev)
+{
+	int sesn;
+	struct xlr_sec_softc *sc = device_get_softc(dev);
+	struct xlr_sec_session *ses = NULL;
+	symkey_desc_pt desc;
+
+	for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
+		ses = &sc->sc_sessions[sesn];
+		desc = (symkey_desc_pt) ses->desc_ptr;
+		free(desc->user.kern_src, M_DEVBUF);
+		free(desc->user.kern_dest, M_DEVBUF);
+		free(desc->next_src_buf, M_DEVBUF);
+		free(desc->next_dest_buf, M_DEVBUF);
+		free(ses->desc_ptr, M_DEVBUF);
+	}
+
+	return (0);
+}
+
+
+
+
+/*
+ * Allocate a new 'session' and return an encoded session id.  'sidp'
+ * contains our registration id, and should contain an encoded session
+ * id on successful allocation.
+ */
+static int
+xlr_sec_newsession(void *arg, u_int32_t * sidp, struct cryptoini *cri)
+{
+	struct cryptoini *c;
+	struct xlr_sec_softc *sc = arg;
+	int mac = 0, cry = 0, sesn;
+	struct xlr_sec_session *ses = NULL;
+
+
+	if (sidp == NULL || cri == NULL || sc == NULL)
+		return (EINVAL);
+
+
+	if (sc->sc_sessions == NULL) {
+		ses = sc->sc_sessions = (struct xlr_sec_session *)malloc(
+		    sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
+		if (ses == NULL)
+			return (ENOMEM);
+
+		ses->desc_ptr = (void *)xlr_sec_allocate_desc((void *)ses);
+		if (ses->desc_ptr == NULL)
+			return (ENOMEM);
+
+		sesn = 0;
+		ses->sessionid = sesn;
+		sc->sc_nsessions = 1;
+	} else {
+		for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
+			if (!sc->sc_sessions[sesn].hs_used) {
+				ses = &sc->sc_sessions[sesn];
+				break;
+			}
+		}
+
+		if (ses == NULL) {
+			sesn = sc->sc_nsessions;
+			ses = (struct xlr_sec_session *)malloc((sesn + 1) *
+			    sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
+			if (ses == NULL)
+				return (ENOMEM);
+			bcopy(sc->sc_sessions, ses, sesn * sizeof(struct xlr_sec_session));
+			bzero(sc->sc_sessions, sesn * sizeof(struct xlr_sec_session));
+			free(sc->sc_sessions, M_DEVBUF);
+			sc->sc_sessions = ses;
+			ses = &sc->sc_sessions[sesn];
+			ses->sessionid = sesn;
+			ses->desc_ptr = (void *)xlr_sec_allocate_desc((void *)ses);
+			if (ses->desc_ptr == NULL)
+				return (ENOMEM);
+			sc->sc_nsessions++;
+		}
+	}
+	ses->hs_used = 1;
+
+
+	for (c = cri; c != NULL; c = c->cri_next) {
+
+		switch (c->cri_alg) {
+		case CRYPTO_MD5:
+		case CRYPTO_SHA1:
+		case CRYPTO_MD5_HMAC:
+		case CRYPTO_SHA1_HMAC:
+			if (mac)
+				return (EINVAL);
+			mac = 1;
+			ses->hs_mlen = c->cri_mlen;
+			if (ses->hs_mlen == 0) {
+				switch (c->cri_alg) {
+				case CRYPTO_MD5:
+				case CRYPTO_MD5_HMAC:
+					ses->hs_mlen = 16;
+					break;
+				case CRYPTO_SHA1:
+				case CRYPTO_SHA1_HMAC:
+					ses->hs_mlen = 20;
+					break;
+				}
+			}
+			break;
+		case CRYPTO_DES_CBC:
+		case CRYPTO_3DES_CBC:
+		case CRYPTO_AES_CBC:
+			/* XXX this may read fewer, does it matter? */
+			/*
+			 * read_random(ses->hs_iv, c->cri_alg ==
+			 * CRYPTO_AES_CBC ? XLR_SEC_AES_IV_LENGTH :
+			 * XLR_SEC_IV_LENGTH);
+			 */
+			/* FALLTHROUGH */
+		case CRYPTO_ARC4:
+			if (cry)
+				return (EINVAL);
+			cry = 1;
+			break;
+		default:
+			return (EINVAL);
+		}
+	}
+	if (mac == 0 && cry == 0)
+		return (EINVAL);
+
+	*sidp = XLR_SEC_SID(device_get_unit(sc->sc_dev), sesn);
+	return (0);
+}
+
+/*
+ * Deallocate a session.
+ * XXX this routine should run a zero'd mac/encrypt key into context ram.
+ * XXX to blow away any keys already stored there.
+ */
+static int
+xlr_sec_freesession(void *arg, u_int64_t tid)
+{
+	struct xlr_sec_softc *sc = arg;
+	int session;
+	u_int32_t sid = CRYPTO_SESID2LID(tid);
+
+	if (sc == NULL)
+		return (EINVAL);
+
+	session = XLR_SEC_SESSION(sid);
+	if (session >= sc->sc_nsessions)
+		return (EINVAL);
+
+	sc->sc_sessions[session].hs_used = 0;
+
+	return (0);
+}
+
+#ifdef RMI_SEC_DEBUG
+
+void 
+xlr_sec_print_data(struct cryptop *crp)
+{
+	int i, key_len;
+	struct cryptodesc *crp_desc;
+
+	printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n",
+	    crp->crp_sid, crp->crp_ilen, crp->crp_olen);
+
+	printf("crp_flags = 0x%x\n", crp->crp_flags);
+
+
+	printf("crp buf:\n");
+	for (i = 0; i < crp->crp_ilen; i++) {
+		printf("%c  ", crp->crp_buf[i]);
+		if (i % 10 == 0)
+			printf("\n");
+	}
+
+	printf("\n");
+	printf("****************** desc ****************\n");
+	crp_desc = crp->crp_desc;
+	printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n",
+	    crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags, crp_desc->crd_alg);
+
+	key_len = crp_desc->crd_klen / 8;
+	printf("key(%d) :\n", key_len);
+	for (i = 0; i < key_len; i++)
+		printf("%d", crp_desc->crd_key[i]);
+	printf("\n");
+
+	printf(" IV : \n");
+	for (i = 0; i < EALG_MAX_BLOCK_LEN; i++)
+		printf("%d", crp_desc->crd_iv[i]);
+	printf("\n");
+
+	printf("crd_next=%p\n", crp_desc->crd_next);
+	return;
+}
+
+#endif
+
+
+static int
+xlr_sec_process(void *arg, struct cryptop *crp, int hint)
+{
+	struct xlr_sec_softc *sc = arg;
+	struct xlr_sec_command *cmd = NULL;
+	int session, err;
+	struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
+	struct xlr_sec_session *ses;
+
+	if (crp == NULL || crp->crp_callback == NULL) {
+		return (EINVAL);
+	}
+	session = XLR_SEC_SESSION(crp->crp_sid);
+	if (sc == NULL || session >= sc->sc_nsessions) {
+		err = EINVAL;
+		goto errout;
+	}
+	ses = &sc->sc_sessions[session];
+
+	cmd = &ses->cmd;
+	if (cmd == NULL) {
+		err = ENOMEM;
+		goto errout;
+	}
+	crd1 = crp->crp_desc;
+	if (crd1 == NULL) {
+		err = EINVAL;
+		goto errout;
+	}
+	crd2 = crd1->crd_next;
+
+	if (crd2 == NULL) {
+		if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
+		    crd1->crd_alg == CRYPTO_SHA1_HMAC ||
+		    crd1->crd_alg == CRYPTO_SHA1 ||
+		    crd1->crd_alg == CRYPTO_MD5) {
+			maccrd = crd1;
+			enccrd = NULL;
+		} else if (crd1->crd_alg == CRYPTO_DES_CBC ||
+			    crd1->crd_alg == CRYPTO_3DES_CBC ||
+			    crd1->crd_alg == CRYPTO_AES_CBC ||
+		    crd1->crd_alg == CRYPTO_ARC4) {
+			maccrd = NULL;
+			enccrd = crd1;
+		} else {
+			err = EINVAL;
+			goto errout;
+		}
+	} else {
+		if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
+		    crd1->crd_alg == CRYPTO_SHA1_HMAC ||
+		    crd1->crd_alg == CRYPTO_MD5 ||
+		    crd1->crd_alg == CRYPTO_SHA1) &&
+		    (crd2->crd_alg == CRYPTO_DES_CBC ||
+		    crd2->crd_alg == CRYPTO_3DES_CBC ||
+		    crd2->crd_alg == CRYPTO_AES_CBC ||
+		    crd2->crd_alg == CRYPTO_ARC4)) {
+			maccrd = crd1;
+			enccrd = crd2;
+		} else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
+			    crd1->crd_alg == CRYPTO_ARC4 ||
+			    crd1->crd_alg == CRYPTO_3DES_CBC ||
+			    crd1->crd_alg == CRYPTO_AES_CBC) &&
+			    (crd2->crd_alg == CRYPTO_MD5_HMAC ||
+			    crd2->crd_alg == CRYPTO_SHA1_HMAC ||
+			    crd2->crd_alg == CRYPTO_MD5 ||
+			    crd2->crd_alg == CRYPTO_SHA1) &&
+		    (crd1->crd_flags & CRD_F_ENCRYPT)) {
+			enccrd = crd1;
+			maccrd = crd2;
+		} else {
+			err = EINVAL;
+			goto errout;
+		}
+	}
+
+	bzero(&cmd->op, sizeof(xlr_sec_io_t));
+
+	cmd->op.source_buf = (uint64_t) (unsigned long)crp->crp_buf;
+	cmd->op.source_buf_size = crp->crp_ilen;
+	if (crp->crp_flags & CRYPTO_F_REL) {
+		cmd->op.dest_buf = (uint64_t) (unsigned long)crp->crp_buf;
+		cmd->op.dest_buf_size = crp->crp_ilen;
+	} else {
+		cmd->op.dest_buf = (uint64_t) (unsigned long)crp->crp_buf;
+		cmd->op.dest_buf_size = crp->crp_ilen;
+	}
+	cmd->op.num_packets = 1;
+	cmd->op.num_fragments = 1;
+
+
+	if (cmd->op.source_buf_size > SEC_MAX_FRAG_LEN) {
+		ses->multi_frag_flag = 1;
+	} else {
+		ses->multi_frag_flag = 0;
+	}
+
+	if (maccrd) {
+		cmd->maccrd = maccrd;
+		cmd->op.cipher_op = XLR_SEC_CIPHER_MODE_PASS;
+		cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_NONE;
+		cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_NONE;
+		cmd->op.cipher_init = 0;
+		cmd->op.cipher_offset = 0;
+
+		switch (maccrd->crd_alg) {
+		case CRYPTO_MD5:
+			cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_MD5;
+			cmd->op.digest_init = XLR_SEC_DIGEST_INIT_NEWKEY;
+			cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
+			cmd->op.digest_offset = 0;
+
+			cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
+			cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
+			cmd->op.cksum_offset = 0;
+
+			cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
+			cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
+			cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
+			cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
+			cmd->op.pkt_iv = XLR_SEC_PKT_IV_OLD;
+			cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
+
+
+		default:
+			printf("currently not handled\n");
+		}
+	}
+	if (enccrd) {
+		cmd->enccrd = enccrd;
+
+#ifdef RMI_SEC_DEBUG
+		xlr_sec_print_data(crp);
+#endif
+
+		if (enccrd->crd_flags & CRD_F_ENCRYPT) {
+			cmd->op.cipher_op = XLR_SEC_CIPHER_OP_ENCRYPT;
+		} else
+			cmd->op.cipher_op = XLR_SEC_CIPHER_OP_DECRYPT;
+
+		switch (enccrd->crd_alg) {
+		case CRYPTO_DES_CBC:
+		case CRYPTO_3DES_CBC:
+			if (enccrd->crd_alg == CRYPTO_DES_CBC) {
+				cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_DES;
+				memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, XLR_SEC_DES_KEY_LENGTH);
+			} else {
+				cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_3DES;
+				//if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
+					memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, XLR_SEC_3DES_KEY_LENGTH);
+				}
+			}
+
+			cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
+			cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
+			cmd->op.cipher_offset = XLR_SEC_DES_IV_LENGTH;
+
+			cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
+			cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
+			cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
+			cmd->op.digest_offset = 0;
+
+			cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
+			cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
+			cmd->op.cksum_offset = 0;
+
+			cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
+			cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
+			cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
+			cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
+			cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
+			cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
+
+			//if ((!(enccrd->crd_flags & CRD_F_IV_PRESENT)) &&
+				    if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) {
+				memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv, XLR_SEC_DES_IV_LENGTH);
+				}
+			break;
+
+		case CRYPTO_AES_CBC:
+			if (enccrd->crd_alg == CRYPTO_AES_CBC) {
+				cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_AES128;
+				//if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
+					memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, XLR_SEC_AES128_KEY_LENGTH);
+				}
+			}
+			cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
+			cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
+			cmd->op.cipher_offset = XLR_SEC_AES_BLOCK_SIZE;
+
+			cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
+			cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
+			cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
+			cmd->op.digest_offset = 0;
+
+			cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
+			cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
+			cmd->op.cksum_offset = 0;
+
+			cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
+			cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
+			cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
+			cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
+			cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
+			cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
+
+			//if (!(enccrd->crd_flags & CRD_F_IV_PRESENT)) {
+				if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) {
+					memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv, XLR_SEC_AES_BLOCK_SIZE);
+				}
+				//
+			}
+			break;
+		}
+	}
+	cmd->crp = crp;
+	cmd->session_num = session;
+	xlr_sec_setup(ses, cmd, (symkey_desc_pt) ses->desc_ptr);
+
+	return (0);
+
+errout:
+	if (cmd != NULL)
+		free(cmd, M_DEVBUF);
+	crp->crp_etype = err;
+	crypto_done(crp);
+	return (err);
+}

sys/mips/rmi/dev/sec/stats.h

@@ -0,0 +1,469 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#ifndef _STATS_H_
+#define _STATS_H_
+
+typedef struct hmac_stats
+{
+  unsigned long md5_count;
+  unsigned long long md5_bytes;
+  unsigned long sha1_count;
+  unsigned long long sha1_bytes;
+  unsigned long sha256_count;
+  unsigned long long sha256_bytes;
+  unsigned long sha384_count;
+  unsigned long long sha384_bytes;
+  unsigned long sha512_count;
+  unsigned long long sha512_bytes;
+  unsigned long gcm_count;
+  unsigned long long gcm_bytes;
+  unsigned long kasumi_f9_count;
+  unsigned long long kasumi_f9_bytes;
+  unsigned long reverts;
+  unsigned long long reverts_bytes;
+} hmac_stats_t, *hmac_stats_pt;
+
+typedef struct cipher_stats
+{
+  unsigned long des_encrypts;
+  unsigned long long des_encrypt_bytes;
+  unsigned long des_decrypts;
+  unsigned long long des_decrypt_bytes;
+  unsigned long des3_encrypts;
+  unsigned long long des3_encrypt_bytes;
+  unsigned long des3_decrypts;
+  unsigned long long des3_decrypt_bytes;
+  unsigned long aes_encrypts;
+  unsigned long long aes_encrypt_bytes;
+  unsigned long aes_decrypts;
+  unsigned long long aes_decrypt_bytes;
+  unsigned long arc4_encrypts;
+  unsigned long long arc4_encrypt_bytes;
+  unsigned long arc4_decrypts;
+  unsigned long long arc4_decrypt_bytes;
+  unsigned long kasumi_f8_encrypts;
+  unsigned long long kasumi_f8_encrypt_bytes;
+  unsigned long kasumi_f8_decrypts;
+  unsigned long long kasumi_f8_decrypt_bytes;
+  unsigned long reverts;
+  unsigned long long reverts_bytes;
+} cipher_stats_t, *cipher_stats_pt;
+
+
+typedef struct modexp_stats
+{
+  unsigned long modexp_512s;
+  unsigned long modexp_1024s;
+} modexp_stats_t, *modexp_stats_pt;
+
+typedef struct ecc_stats
+{
+  unsigned long ecc_mul;
+  unsigned long ecc_add;
+  unsigned long ecc_dbl;
+  unsigned long ecc_vfy;
+  unsigned long ecc_bin_mul;
+  unsigned long ecc_field_bin_inv;
+  unsigned long ecc_field_bin_mul;
+  unsigned long ecc_field_bin_add;
+  unsigned long ecc_field_add;
+  unsigned long ecc_field_sub;
+  unsigned long ecc_field_mul;
+  unsigned long ecc_field_inv;
+  unsigned long ecc_field_div;
+  unsigned long ecc_field_red;
+} ecc_stats_t, *ecc_stats_pt;
+
+
+typedef struct opt_stats
+{
+  unsigned long combined;
+  unsigned long unaligned_auth_dest;
+  unsigned long sym_failed;
+  unsigned long modexp_failed;
+  unsigned long ecc_failed;
+} opt_stats_t, *opt_stats_pt;
+
+typedef struct rmisec_stats
+{
+  uint32_t sent;
+  uint32_t received;
+  uint32_t stats_mask;
+  uint32_t control_mask;
+  rwlock_t rmisec_control_lock;
+  rwlock_t rmisec_stats_lock;
+  char clear_start[0];
+  uint64_t wait_time;
+  uint32_t max_wait_time;
+  uint32_t maxsnd_wait_time;
+  uint32_t wait_count;
+  hmac_stats_t hmac;
+  cipher_stats_t cipher;
+  modexp_stats_t modexp;
+  ecc_stats_t ecc;
+  opt_stats_t opt;
+} rmisec_stats_t, *rmisec_stats_pt;
+
+
+/* stats routines */
+
+static void inline phxdrv_record_sent(rmisec_stats_pt stats)
+{
+  write_lock(&stats->rmisec_stats_lock);
+  stats->sent++;
+  write_unlock(&stats->rmisec_stats_lock);
+}
+
+static void inline phxdrv_record_received(rmisec_stats_pt stats)
+{
+  write_lock(&stats->rmisec_stats_lock);
+  stats->received++;
+  write_unlock(&stats->rmisec_stats_lock);
+}
+
+
+static void inline phxdrv_record_des(rmisec_stats_pt stats, int enc,
+                     int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_DES) {
+    write_lock(&stats->rmisec_stats_lock);
+    if (enc) {
+      stats->cipher.des_encrypts++;
+      stats->cipher.des_encrypt_bytes += nbytes;
+    }
+    else {
+      stats->cipher.des_decrypts++;
+      stats->cipher.des_decrypt_bytes += nbytes;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_3des(rmisec_stats_pt stats, int enc,
+                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_3DES) {
+    write_lock(&stats->rmisec_stats_lock);
+    if (enc) {
+      stats->cipher.des3_encrypts++;
+      stats->cipher.des3_encrypt_bytes += nbytes;
+    }
+    else {
+      stats->cipher.des3_decrypts++;
+      stats->cipher.des3_decrypt_bytes += nbytes;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_aes(rmisec_stats_pt stats, int enc,
+                     int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_AES) {
+    write_lock(&stats->rmisec_stats_lock);
+    if (enc) {
+      stats->cipher.aes_encrypts++;
+      stats->cipher.aes_encrypt_bytes += nbytes;
+    }
+    else {
+      stats->cipher.aes_decrypts++;
+      stats->cipher.aes_decrypt_bytes += nbytes;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_arc4(rmisec_stats_pt stats, int enc,
+                     int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_ARC4) {
+    write_lock(&stats->rmisec_stats_lock);
+    if (enc) {
+      stats->cipher.arc4_encrypts++;
+      stats->cipher.arc4_encrypt_bytes += nbytes;
+    }
+    else {
+      stats->cipher.arc4_decrypts++;
+      stats->cipher.arc4_decrypt_bytes += nbytes;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_kasumi_f8(rmisec_stats_pt stats, int enc,
+                                     int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_KASUMI_F8) {
+    write_lock(&stats->rmisec_stats_lock);
+    if (enc) {
+      stats->cipher.kasumi_f8_encrypts++;
+      stats->cipher.kasumi_f8_encrypt_bytes += nbytes;
+    }
+    else {
+      stats->cipher.kasumi_f8_decrypts++;
+      stats->cipher.kasumi_f8_decrypt_bytes += nbytes;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_modexp(rmisec_stats_pt stats,
+                        int blksize)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_MODEXP) {
+    write_lock(&stats->rmisec_stats_lock);
+    if (blksize == 512) {
+      stats->modexp.modexp_512s++;
+    }
+    if (blksize == 1024) {
+      stats->modexp.modexp_1024s++;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_ecc(rmisec_stats_pt stats, PHX_ECC_OP op)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_ECC) {
+    write_lock(&stats->rmisec_stats_lock);
+    switch (op) {
+    case PHX_ECC_NOP:
+        break;
+    case PHX_ECC_MUL:
+        stats->ecc.ecc_mul++;
+        break;
+    case PHX_ECC_BIN_MUL:
+        stats->ecc.ecc_bin_mul++;
+        break;
+    case PHX_ECC_ADD:
+        stats->ecc.ecc_add++;
+        break;
+    case PHX_ECC_DBL:
+        stats->ecc.ecc_dbl++;
+        break;
+    case PHX_ECC_VFY:
+        stats->ecc.ecc_vfy++;
+        break;
+    case PHX_ECC_FIELD_BIN_INV:
+        stats->ecc.ecc_field_bin_inv++;
+        break;
+    case PHX_ECC_FIELD_BIN_MUL:
+        stats->ecc.ecc_field_bin_mul++;
+        break;
+    case PHX_ECC_FIELD_BIN_ADD:
+        stats->ecc.ecc_field_bin_add++;
+        break;
+    case PHX_ECC_FIELD_ADD:
+        stats->ecc.ecc_field_add++;
+        break;
+    case PHX_ECC_FIELD_SUB:
+        stats->ecc.ecc_field_sub++;
+        break;
+    case PHX_ECC_FIELD_MUL:
+        stats->ecc.ecc_field_mul++;
+        break;
+    case PHX_ECC_FIELD_INV:
+        stats->ecc.ecc_field_inv++;
+        break;
+    case PHX_ECC_FIELD_DIV:
+        stats->ecc.ecc_field_div++;
+        break;
+    case PHX_ECC_FIELD_RED:
+        stats->ecc.ecc_field_red++;
+        break;
+    case PHX_ECC_FIELD:
+    case PHX_ECC_BIN:
+        break;
+    }
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_cipher_revert(rmisec_stats_pt stats,
+                           int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_CPHR_REVERTS) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->cipher.reverts++;
+    stats->cipher.reverts_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_hmac_revert(rmisec_stats_pt stats,
+                         int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_HMAC_REVERTS) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.reverts++;
+    stats->hmac.reverts_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_md5(rmisec_stats_pt stats,
+                     int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_MD5) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.md5_count++;
+    stats->hmac.md5_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_sha1(rmisec_stats_pt stats,
+                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_SHA1) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.sha1_count++;
+    stats->hmac.sha1_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_sha256(rmisec_stats_pt stats,
+                    int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_SHA256) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.sha256_count++;
+    stats->hmac.sha256_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_sha384(rmisec_stats_pt stats,
+                                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_SHA384) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.sha384_count++;
+    stats->hmac.sha384_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_sha512(rmisec_stats_pt stats,
+                                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_SHA512) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.sha512_count++;
+    stats->hmac.sha512_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_gcm(rmisec_stats_pt stats,
+                                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_GCM) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.gcm_count++;
+    stats->hmac.gcm_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_kasumi_f9(rmisec_stats_pt stats,
+                                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_KASUMI_F9) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->hmac.kasumi_f9_count++;
+    stats->hmac.kasumi_f9_bytes += nbytes;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_unaligned_auth_dest(rmisec_stats_pt stats,
+                             int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_UNALIGNED_AUTH_DEST) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->opt.unaligned_auth_dest++;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+
+static void inline phxdrv_record_combined(rmisec_stats_pt stats,
+                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->opt.combined++;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_sym_failed(rmisec_stats_pt stats,
+                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->opt.sym_failed++;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_modexp_failed(rmisec_stats_pt stats,
+                      int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->opt.modexp_failed++;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+static void inline phxdrv_record_ecc_failed(rmisec_stats_pt stats,
+                                          int nbytes)
+{
+  if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
+    write_lock(&stats->rmisec_stats_lock);
+    stats->opt.ecc_failed++;
+    write_unlock(&stats->rmisec_stats_lock);
+  }
+}
+
+#endif

sys/mips/rmi/dev/xlr/atx_cpld.h

@@ -0,0 +1,53 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _RMI_ATX_CPLD_H_
+#define _RMI_ATX_CPLD_H_
+
+/*
+ * bit_0 : xgs0 phy reset, bit_1 : xgs1 phy reset, bit_2 : HT reset, bit_3 :
+ * RTC reset, bit_4 : gmac phy soft reset, bit_5 : gmac phy hard reset, bit_6
+ * : board reset, bit_7 : reserved
+ */
+#define ATX_CPLD_RESET_1   2
+
+/*
+ * bit_0_2 : reserved, bit_3 : turn off xpak_0 tx, bit_4 : turn off xpak_1
+ * tx, bit_5 : HT stop (active low), bit_6 : flash program enable, bit_7 :
+ * compact flash io mode
+ */
+#define ATX_CPLD_MISC_CTRL 8
+
+/*
+ * bit_0 : reset tcam, bit_1 : reset xpak_0 module, bit_2 : reset xpak_1
+ * module, bit_3_7 : reserved
+ */
+#define ATX_CPLD_RESET_2   9
+
+#endif				/* _RMI_ATX_CPLD_H_ */

sys/mips/rmi/dev/xlr/xgmac_mdio.h

@@ -0,0 +1,127 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+/* MDIO Low level Access routines */
+/* All Phy's accessed from GMAC0 base */
+
+#ifndef _XGMAC_MDIO_H_
+#define _XGMAC_MDIO_H_
+
+static inline int
+xmdio_read(volatile unsigned int *_mmio,
+    uint32_t phy_addr, uint32_t address);
+static inline void
+xmdio_write(volatile unsigned int *_mmio,
+    uint32_t phy_addr, uint32_t address, uint32_t data);
+static inline void
+xmdio_address(volatile unsigned int *_mmio,
+    uint32_t phy_addr, uint32_t dev_ad, uint32_t address);
+
+static inline void
+xmdio_address(volatile unsigned int *_mmio,
+    uint32_t phy_addr, uint32_t dev_ad, uint32_t address)
+{
+	uint32_t st_field = 0x0;
+	uint32_t op_type = 0x0;	/* address operation */
+	uint32_t ta_field = 0x2;/* ta field */
+
+	_mmio[0x11] = ((st_field & 0x3) << 30) |
+	    ((op_type & 0x3) << 28) |
+	    ((phy_addr & 0x1F) << 23) |
+	    ((dev_ad & 0x1F) << 18) |
+	    ((ta_field & 0x3) << 16) |
+	    ((address & 0xffff) << 0);
+
+	_mmio[0x10] = (0x0 << 3) | 0x5;
+	_mmio[0x10] = (0x1 << 3) | 0x5;
+	_mmio[0x10] = (0x0 << 3) | 0x5;
+
+	/* wait for dev_ad cycle to complete */
+	while (_mmio[0x14] & 0x1) {
+	};
+
+}
+
+/* function prototypes */
+static inline int
+xmdio_read(volatile unsigned int *_mmio,
+    uint32_t phy_addr, uint32_t address)
+{
+	uint32_t st_field = 0x0;
+	uint32_t op_type = 0x3;	/* read operation */
+	uint32_t ta_field = 0x2;/* ta field */
+	uint32_t data = 0;
+
+	xmdio_address(_mmio, phy_addr, 5, address);
+	_mmio[0x11] = ((st_field & 0x3) << 30) |
+	    ((op_type & 0x3) << 28) |
+	    ((phy_addr & 0x1F) << 23) |
+	    ((5 & 0x1F) << 18) |
+	    ((ta_field & 0x3) << 16) |
+	    ((data & 0xffff) << 0);
+
+	_mmio[0x10] = (0x0 << 3) | 0x5;
+	_mmio[0x10] = (0x1 << 3) | 0x5;
+	_mmio[0x10] = (0x0 << 3) | 0x5;
+
+	/* wait for write cycle to complete */
+	while (_mmio[0x14] & 0x1) {
+	};
+
+	data = _mmio[0x11] & 0xffff;
+	return (data);
+}
+
+static inline void
+xmdio_write(volatile unsigned int *_mmio,
+    uint32_t phy_addr, uint32_t address, uint32_t data)
+{
+	uint32_t st_field = 0x0;
+	uint32_t op_type = 0x1;	/* write operation */
+	uint32_t ta_field = 0x2;/* ta field */
+
+	xmdio_address(_mmio, phy_addr, 5, address);
+	_mmio[0x11] = ((st_field & 0x3) << 30) |
+	    ((op_type & 0x3) << 28) |
+	    ((phy_addr & 0x1F) << 23) |
+	    ((5 & 0x1F) << 18) |
+	    ((ta_field & 0x3) << 16) |
+	    ((data & 0xffff) << 0);
+
+	_mmio[0x10] = (0x0 << 3) | 0x5;
+	_mmio[0x10] = (0x1 << 3) | 0x5;
+	_mmio[0x10] = (0x0 << 3) | 0x5;
+
+	/* wait for write cycle to complete */
+	while (_mmio[0x14] & 0x1) {
+	};
+
+}
+
+#endif