Add the SPI driver for the Marvell Armada 37x0 SoC.
Interrupt based driver, implements SPI mode and clock configuration. Tested on espressobin and SG-3200. Sponsored by: Rubicon Communications, LLC (Netgate)
This commit is contained in:
Luiz Otavio O Souza
parent
fed13eb3e8
commit
8cfe2a7ad3
494
sys/arm/mv/a37x0_spi.c
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494
sys/arm/mv/a37x0_spi.c
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@ -0,0 +1,494 @@
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/*-
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* Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include "spibus_if.h"
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struct a37x0_spi_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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struct spi_command *sc_cmd;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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uint32_t sc_len;
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uint32_t sc_maxfreq;
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uint32_t sc_read;
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uint32_t sc_flags;
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uint32_t sc_written;
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void *sc_intrhand;
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};
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#define A37X0_SPI_WRITE(_sc, _off, _val) \
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bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
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#define A37X0_SPI_READ(_sc, _off) \
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bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
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#define A37X0_SPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define A37X0_SPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define A37X0_SPI_BUSY (1 << 0)
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/*
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* While the A3700 utils from Marvell usually sets the QSF clock to 200MHz,
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* there is no guarantee that it is correct without the proper clock framework
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* to retrieve the actual TBG and PLL settings.
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*/
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#define A37X0_SPI_CLOCK 200000000 /* QSF Clock 200MHz */
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#define A37X0_SPI_CONTROL 0x0
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#define A37X0_SPI_CS_SHIFT 16
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#define A37X0_SPI_CS_MASK (0xf << A37X0_SPI_CS_SHIFT)
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#define A37X0_SPI_CONF 0x4
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#define A37X0_SPI_WFIFO_THRS_SHIFT 28
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#define A37X0_SPI_RFIFO_THRS_SHIFT 24
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#define A37X0_SPI_AUTO_CS_EN (1 << 20)
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#define A37X0_SPI_DMA_WR_EN (1 << 19)
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#define A37X0_SPI_DMA_RD_EN (1 << 18)
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#define A37X0_SPI_FIFO_MODE (1 << 17)
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#define A37X0_SPI_SRST (1 << 16)
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#define A37X0_SPI_XFER_START (1 << 15)
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#define A37X0_SPI_XFER_STOP (1 << 14)
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#define A37X0_SPI_INSTR_PIN (1 << 13)
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#define A37X0_SPI_ADDR_PIN (1 << 12)
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#define A37X0_SPI_DATA_PIN_MASK 0x3
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#define A37X0_SPI_DATA_PIN_SHIFT 10
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#define A37X0_SPI_FIFO_FLUSH (1 << 9)
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#define A37X0_SPI_RW_EN (1 << 8)
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#define A37X0_SPI_CLK_POL (1 << 7)
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#define A37X0_SPI_CLK_PHASE (1 << 6)
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#define A37X0_SPI_BYTE_LEN (1 << 5)
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#define A37X0_SPI_PSC_MASK 0x1f
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#define A37X0_SPI_DATA_OUT 0x8
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#define A37X0_SPI_DATA_IN 0xc
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#define A37X0_SPI_INTR_STAT 0x28
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#define A37X0_SPI_INTR_MASK 0x2c
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#define A37X0_SPI_RDY (1 << 1)
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#define A37X0_SPI_XFER_DONE (1 << 0)
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static struct ofw_compat_data compat_data[] = {
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{ "marvell,armada-3700-spi", 1 },
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{ NULL, 0 }
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};
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static void a37x0_spi_intr(void *);
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static int
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a37x0_spi_wait(struct a37x0_spi_softc *sc, int timeout, uint32_t reg,
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uint32_t mask)
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{
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int i;
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for (i = 0; i < timeout; i++) {
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if ((A37X0_SPI_READ(sc, reg) & mask) == 0)
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return (0);
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DELAY(100);
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}
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return (ETIMEDOUT);
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}
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static int
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a37x0_spi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Armada 37x0 SPI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a37x0_spi_attach(device_t dev)
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{
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int err, rid;
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pcell_t maxfreq;
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struct a37x0_spi_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot allocate interrupt\n");
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return (ENXIO);
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}
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/* Make sure that no CS is asserted. */
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reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);
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/* Reset FIFO. */
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reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_FIFO_FLUSH);
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err = a37x0_spi_wait(sc, 20, A37X0_SPI_CONF, A37X0_SPI_FIFO_FLUSH);
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if (err != 0) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot flush the controller fifo.\n");
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return (ENXIO);
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}
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/* Reset the Controller. */
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reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_SRST);
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DELAY(1000);
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/* Enable the single byte IO, disable FIFO. */
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reg &= ~(A37X0_SPI_FIFO_MODE | A37X0_SPI_BYTE_LEN);
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);
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/* Disable and clear interrupts. */
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A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_MASK, 0);
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reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);
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A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);
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/* Hook up our interrupt handler. */
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, a37x0_spi_intr, sc, &sc->sc_intrhand)) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot setup the interrupt handler\n");
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return (ENXIO);
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}
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mtx_init(&sc->sc_mtx, "a37x0_spi", NULL, MTX_DEF);
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/* Read the controller max-frequency. */
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if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency", &maxfreq,
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sizeof(maxfreq)) == -1)
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maxfreq = 0;
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sc->sc_maxfreq = maxfreq;
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device_add_child(dev, "spibus", -1);
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/* Probe and attach the spibus when interrupts are available. */
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config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
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return (0);
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}
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static int
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a37x0_spi_detach(device_t dev)
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{
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struct a37x0_spi_softc *sc;
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bus_generic_detach(dev);
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sc = device_get_softc(dev);
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mtx_destroy(&sc->sc_mtx);
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (0);
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}
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static __inline void
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a37x0_spi_rx_byte(struct a37x0_spi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t read;
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uint8_t *p;
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if (sc->sc_read == sc->sc_len)
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return;
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cmd = sc->sc_cmd;
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p = (uint8_t *)cmd->rx_cmd;
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read = sc->sc_read++;
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if (read >= cmd->rx_cmd_sz) {
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p = (uint8_t *)cmd->rx_data;
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read -= cmd->rx_cmd_sz;
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}
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p[read] = A37X0_SPI_READ(sc, A37X0_SPI_DATA_IN) & 0xff;
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}
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static __inline void
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a37x0_spi_tx_byte(struct a37x0_spi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t written;
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uint8_t *p;
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if (sc->sc_written == sc->sc_len)
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return;
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cmd = sc->sc_cmd;
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p = (uint8_t *)cmd->tx_cmd;
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written = sc->sc_written++;
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if (written >= cmd->tx_cmd_sz) {
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p = (uint8_t *)cmd->tx_data;
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written -= cmd->tx_cmd_sz;
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}
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A37X0_SPI_WRITE(sc, A37X0_SPI_DATA_OUT, p[written]);
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}
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static __inline void
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a37x0_spi_set_clock(struct a37x0_spi_softc *sc, uint32_t clock)
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{
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uint32_t psc, reg;
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if (sc->sc_maxfreq > 0 && clock > sc->sc_maxfreq)
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clock = sc->sc_maxfreq;
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psc = A37X0_SPI_CLOCK / clock;
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if ((A37X0_SPI_CLOCK % clock) > 0)
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psc++;
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reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);
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reg &= ~A37X0_SPI_PSC_MASK;
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reg |= psc & A37X0_SPI_PSC_MASK;
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);
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}
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static __inline void
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a37x0_spi_set_pins(struct a37x0_spi_softc *sc, uint32_t npins)
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{
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uint32_t reg;
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/* Sets single, dual or quad SPI mode. */
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reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);
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reg &= ~(A37X0_SPI_DATA_PIN_MASK << A37X0_SPI_DATA_PIN_SHIFT);
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reg |= (npins / 2) << A37X0_SPI_DATA_PIN_SHIFT;
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reg |= A37X0_SPI_INSTR_PIN | A37X0_SPI_ADDR_PIN;
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);
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}
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static __inline void
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a37x0_spi_set_mode(struct a37x0_spi_softc *sc, uint32_t mode)
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{
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uint32_t reg;
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reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);
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switch (mode) {
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case 0:
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reg &= ~(A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL);
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break;
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case 1:
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reg &= ~A37X0_SPI_CLK_POL;
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reg |= A37X0_SPI_CLK_PHASE;
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break;
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case 2:
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reg &= ~A37X0_SPI_CLK_PHASE;
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reg |= A37X0_SPI_CLK_POL;
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break;
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case 3:
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reg |= (A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL);
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break;
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}
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A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);
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}
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static void
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a37x0_spi_intr(void *arg)
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{
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struct a37x0_spi_softc *sc;
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uint32_t status;
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sc = (struct a37x0_spi_softc *)arg;
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A37X0_SPI_LOCK(sc);
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/* Filter stray interrupts. */
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if ((sc->sc_flags & A37X0_SPI_BUSY) == 0) {
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A37X0_SPI_UNLOCK(sc);
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return;
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}
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status = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);
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if (status & A37X0_SPI_XFER_DONE)
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a37x0_spi_rx_byte(sc);
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/* Clear the interrupt status. */
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A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, status);
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/* Check for end of transfer. */
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if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len)
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wakeup(sc->sc_dev);
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else
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a37x0_spi_tx_byte(sc);
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A37X0_SPI_UNLOCK(sc);
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}
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static int
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a37x0_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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int timeout;
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struct a37x0_spi_softc *sc;
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uint32_t clock, cs, mode, reg;
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("TX/RX command sizes should be equal"));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("TX/RX data sizes should be equal"));
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/* Get the proper data for this child. */
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spibus_get_cs(child, &cs);
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cs &= ~SPIBUS_CS_HIGH;
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if (cs > 3) {
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device_printf(dev,
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"Invalid CS %d requested by %s\n", cs,
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device_get_nameunit(child));
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return (EINVAL);
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}
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spibus_get_clock(child, &clock);
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if (clock == 0) {
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device_printf(dev,
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"Invalid clock %uHz requested by %s\n", clock,
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device_get_nameunit(child));
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return (EINVAL);
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}
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spibus_get_mode(child, &mode);
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if (mode > 3) {
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device_printf(dev,
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"Invalid mode %u requested by %s\n", mode,
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device_get_nameunit(child));
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return (EINVAL);
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}
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sc = device_get_softc(dev);
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A37X0_SPI_LOCK(sc);
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/* Wait until the controller is free. */
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while (sc->sc_flags & A37X0_SPI_BUSY)
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mtx_sleep(dev, &sc->sc_mtx, 0, "a37x0_spi", 0);
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/* Now we have control over SPI controller. */
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sc->sc_flags = A37X0_SPI_BUSY;
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/* Set transfer mode and clock. */
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a37x0_spi_set_mode(sc, mode);
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a37x0_spi_set_pins(sc, 1);
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a37x0_spi_set_clock(sc, clock);
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/* Set CS. */
|
||||
A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, 1 << (A37X0_SPI_CS_SHIFT + cs));
|
||||
|
||||
/* Save a pointer to the SPI command. */
|
||||
sc->sc_cmd = cmd;
|
||||
sc->sc_read = 0;
|
||||
sc->sc_written = 0;
|
||||
sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
|
||||
|
||||
/* Clear interrupts. */
|
||||
reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);
|
||||
A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);
|
||||
|
||||
while ((sc->sc_len - sc->sc_written) > 0) {
|
||||
/*
|
||||
* Write to start the transmission and read the byte
|
||||
* back when ready.
|
||||
*/
|
||||
a37x0_spi_tx_byte(sc);
|
||||
timeout = 1000;
|
||||
while (--timeout > 0) {
|
||||
reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);
|
||||
if (reg & A37X0_SPI_XFER_DONE)
|
||||
break;
|
||||
DELAY(1);
|
||||
}
|
||||
if (timeout == 0)
|
||||
break;
|
||||
a37x0_spi_rx_byte(sc);
|
||||
}
|
||||
|
||||
/* Stop the controller. */
|
||||
reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);
|
||||
A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);
|
||||
A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_MASK, 0);
|
||||
|
||||
/* Release the controller and wakeup the next thread waiting for it. */
|
||||
sc->sc_flags = 0;
|
||||
wakeup_one(dev);
|
||||
A37X0_SPI_UNLOCK(sc);
|
||||
|
||||
return ((timeout == 0) ? EIO : 0);
|
||||
}
|
||||
|
||||
static phandle_t
|
||||
a37x0_spi_get_node(device_t bus, device_t dev)
|
||||
{
|
||||
|
||||
return (ofw_bus_get_node(bus));
|
||||
}
|
||||
|
||||
static device_method_t a37x0_spi_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, a37x0_spi_probe),
|
||||
DEVMETHOD(device_attach, a37x0_spi_attach),
|
||||
DEVMETHOD(device_detach, a37x0_spi_detach),
|
||||
|
||||
/* SPI interface */
|
||||
DEVMETHOD(spibus_transfer, a37x0_spi_transfer),
|
||||
|
||||
/* ofw_bus interface */
|
||||
DEVMETHOD(ofw_bus_get_node, a37x0_spi_get_node),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static devclass_t a37x0_spi_devclass;
|
||||
|
||||
static driver_t a37x0_spi_driver = {
|
||||
"spi",
|
||||
a37x0_spi_methods,
|
||||
sizeof(struct a37x0_spi_softc),
|
||||
};
|
||||
|
||||
DRIVER_MODULE(a37x0_spi, simplebus, a37x0_spi_driver, a37x0_spi_devclass, 0, 0);
|
||||
@ -288,6 +288,7 @@ device mv_thermal # Marvell Thermal Sensor Controller
|
||||
|
||||
# SPI
|
||||
device spibus
|
||||
device a37x0_spi # Marvell Armada 37x0 SPI Controller
|
||||
device bcm2835_spi # Broadcom BCM283x SPI bus
|
||||
device rk_spi # RockChip SPI controller
|
||||
|
||||
|
||||
@ -108,6 +108,7 @@ arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm283
|
||||
arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838
|
||||
arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt
|
||||
arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt
|
||||
arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt
|
||||
arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
|
||||
arm/mv/gpio.c optional mv_gpio fdt
|
||||
arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user