fu540_spi: Rename to sifive_spi
The FU740 also uses the same SPI controller. Reviewed by: kp, philip MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D31026
This commit is contained in:
Jessica Clarke
parent
8e7e0690ec
commit
90a089cf2a
@ -174,5 +174,5 @@ options FDT
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makeoptions MODULES_EXTRA+="dtb/sifive"
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# SiFive device drivers
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device fu540spi
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device sifive_spi
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include "../sifive/std.sifive"
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@ -66,7 +66,7 @@ device xilinx_spi # Xilinx AXI Quad-SPI Controller
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# SOC-specific
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device fe310aon
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device fu540spi
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device sifive_spi
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files "../sifive/files.sifive"
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# Flattened Device Tree
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@ -1,6 +1,6 @@
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# $FreeBSD$
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riscv/sifive/fe310_aon.c optional fe310aon
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riscv/sifive/fu540_spi.c optional fu540spi spibus
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riscv/sifive/sifive_prci.c standard
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riscv/sifive/sifive_spi.c optional sifive_spi spibus
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riscv/sifive/sifive_uart.c standard
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@ -62,12 +62,12 @@ __FBSDID("$FreeBSD$");
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#define DBGPRINT(dev, fmt, args...)
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#endif
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static struct resource_spec fuspi_spec[] = {
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static struct resource_spec sfspi_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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RESOURCE_SPEC_END
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};
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struct fuspi_softc {
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struct sfspi_softc {
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device_t dev;
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device_t parent;
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@ -84,67 +84,67 @@ struct fuspi_softc {
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uint32_t cs_max;
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};
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#define FUSPI_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define FUSPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define FUSPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
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#define FUSPI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
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#define SFSPI_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define SFSPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define SFSPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
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#define SFSPI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
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/*
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* Register offsets.
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* From Sifive-Unleashed-FU540-C000-v1.0.pdf page 101.
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*/
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#define FUSPI_REG_SCKDIV 0x00 /* Serial clock divisor */
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#define FUSPI_REG_SCKMODE 0x04 /* Serial clock mode */
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#define FUSPI_REG_CSID 0x10 /* Chip select ID */
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#define FUSPI_REG_CSDEF 0x14 /* Chip select default */
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#define FUSPI_REG_CSMODE 0x18 /* Chip select mode */
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#define FUSPI_REG_DELAY0 0x28 /* Delay control 0 */
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#define FUSPI_REG_DELAY1 0x2C /* Delay control 1 */
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#define FUSPI_REG_FMT 0x40 /* Frame format */
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#define FUSPI_REG_TXDATA 0x48 /* Tx FIFO data */
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#define FUSPI_REG_RXDATA 0x4C /* Rx FIFO data */
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#define FUSPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
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#define FUSPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
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#define FUSPI_REG_FCTRL 0x60 /* SPI flash interface control* */
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#define FUSPI_REG_FFMT 0x64 /* SPI flash instruction format* */
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#define FUSPI_REG_IE 0x70 /* SPI interrupt enable */
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#define FUSPI_REG_IP 0x74 /* SPI interrupt pending */
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#define SFSPI_REG_SCKDIV 0x00 /* Serial clock divisor */
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#define SFSPI_REG_SCKMODE 0x04 /* Serial clock mode */
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#define SFSPI_REG_CSID 0x10 /* Chip select ID */
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#define SFSPI_REG_CSDEF 0x14 /* Chip select default */
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#define SFSPI_REG_CSMODE 0x18 /* Chip select mode */
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#define SFSPI_REG_DELAY0 0x28 /* Delay control 0 */
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#define SFSPI_REG_DELAY1 0x2C /* Delay control 1 */
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#define SFSPI_REG_FMT 0x40 /* Frame format */
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#define SFSPI_REG_TXDATA 0x48 /* Tx FIFO data */
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#define SFSPI_REG_RXDATA 0x4C /* Rx FIFO data */
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#define SFSPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
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#define SFSPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
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#define SFSPI_REG_FCTRL 0x60 /* SPI flash interface control* */
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#define SFSPI_REG_FFMT 0x64 /* SPI flash instruction format* */
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#define SFSPI_REG_IE 0x70 /* SPI interrupt enable */
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#define SFSPI_REG_IP 0x74 /* SPI interrupt pending */
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#define FUSPI_SCKDIV_MASK 0xfff
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#define SFSPI_SCKDIV_MASK 0xfff
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#define FUSPI_CSDEF_ALL ((1 << sc->cs_max)-1)
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#define SFSPI_CSDEF_ALL ((1 << sc->cs_max)-1)
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#define FUSPI_CSMODE_AUTO 0x0U
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#define FUSPI_CSMODE_HOLD 0x2U
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#define FUSPI_CSMODE_OFF 0x3U
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#define SFSPI_CSMODE_AUTO 0x0U
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#define SFSPI_CSMODE_HOLD 0x2U
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#define SFSPI_CSMODE_OFF 0x3U
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#define FUSPI_TXDATA_DATA_MASK 0xff
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#define FUSPI_TXDATA_FULL (1 << 31)
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#define SFSPI_TXDATA_DATA_MASK 0xff
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#define SFSPI_TXDATA_FULL (1 << 31)
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#define FUSPI_RXDATA_DATA_MASK 0xff
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#define FUSPI_RXDATA_EMPTY (1 << 31)
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#define SFSPI_RXDATA_DATA_MASK 0xff
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#define SFSPI_RXDATA_EMPTY (1 << 31)
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#define FUSPI_SCKMODE_PHA (1 << 0)
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#define FUSPI_SCKMODE_POL (1 << 1)
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#define SFSPI_SCKMODE_PHA (1 << 0)
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#define SFSPI_SCKMODE_POL (1 << 1)
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#define FUSPI_FMT_PROTO_SINGLE 0x0U
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#define FUSPI_FMT_PROTO_DUAL 0x1U
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#define FUSPI_FMT_PROTO_QUAD 0x2U
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#define FUSPI_FMT_PROTO_MASK 0x3U
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#define FUSPI_FMT_ENDIAN (1 << 2)
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#define FUSPI_FMT_DIR (1 << 3)
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#define FUSPI_FMT_LEN(x) ((uint32_t)(x) << 16)
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#define FUSPI_FMT_LEN_MASK (0xfU << 16)
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#define SFSPI_FMT_PROTO_SINGLE 0x0U
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#define SFSPI_FMT_PROTO_DUAL 0x1U
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#define SFSPI_FMT_PROTO_QUAD 0x2U
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#define SFSPI_FMT_PROTO_MASK 0x3U
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#define SFSPI_FMT_ENDIAN (1 << 2)
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#define SFSPI_FMT_DIR (1 << 3)
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#define SFSPI_FMT_LEN(x) ((uint32_t)(x) << 16)
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#define SFSPI_FMT_LEN_MASK (0xfU << 16)
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#define FUSPI_FIFO_DEPTH 8
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#define SFSPI_FIFO_DEPTH 8
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#define FUSPI_READ(_sc, _reg) \
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#define SFSPI_READ(_sc, _reg) \
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bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
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#define FUSPI_WRITE(_sc, _reg, _val) \
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#define SFSPI_WRITE(_sc, _reg, _val) \
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bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
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static void
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fuspi_tx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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sfspi_tx(struct sfspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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{
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uint32_t val;
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uint8_t *p, *end;
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@ -154,35 +154,35 @@ fuspi_tx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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end = buf + bufsiz;
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for (p = buf; p < end; p++) {
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do {
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val = FUSPI_READ(sc, FUSPI_REG_TXDATA);
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} while (val & FUSPI_TXDATA_FULL);
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val = SFSPI_READ(sc, SFSPI_REG_TXDATA);
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} while (val & SFSPI_TXDATA_FULL);
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val = *p;
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FUSPI_WRITE(sc, FUSPI_REG_TXDATA, val);
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SFSPI_WRITE(sc, SFSPI_REG_TXDATA, val);
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}
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}
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static void
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fuspi_rx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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sfspi_rx(struct sfspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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{
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uint32_t val;
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uint8_t *p, *end;
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KASSERT(buf != NULL, ("RX buffer cannot be NULL"));
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KASSERT(bufsiz <= FUSPI_FIFO_DEPTH,
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KASSERT(bufsiz <= SFSPI_FIFO_DEPTH,
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("Cannot receive more than %d bytes at a time\n",
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FUSPI_FIFO_DEPTH));
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SFSPI_FIFO_DEPTH));
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end = buf + bufsiz;
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for (p = buf; p < end; p++) {
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do {
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val = FUSPI_READ(sc, FUSPI_REG_RXDATA);
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} while (val & FUSPI_RXDATA_EMPTY);
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*p = val & FUSPI_RXDATA_DATA_MASK;
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val = SFSPI_READ(sc, SFSPI_REG_RXDATA);
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} while (val & SFSPI_RXDATA_EMPTY);
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*p = val & SFSPI_RXDATA_DATA_MASK;
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};
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}
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static int
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fuspi_xfer_buf(struct fuspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf,
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sfspi_xfer_buf(struct sfspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf,
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uint32_t txlen, uint32_t rxlen)
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{
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uint32_t bytes;
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@ -192,10 +192,10 @@ fuspi_xfer_buf(struct fuspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf,
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KASSERT(txbuf != NULL, ("TX buffer cannot be NULL"));
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while (txlen) {
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bytes = (txlen > FUSPI_FIFO_DEPTH) ? FUSPI_FIFO_DEPTH : txlen;
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fuspi_tx(sc, txbuf, bytes);
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bytes = (txlen > SFSPI_FIFO_DEPTH) ? SFSPI_FIFO_DEPTH : txlen;
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sfspi_tx(sc, txbuf, bytes);
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txbuf += bytes;
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fuspi_rx(sc, rxbuf, bytes);
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sfspi_rx(sc, rxbuf, bytes);
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rxbuf += bytes;
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txlen -= bytes;
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}
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@ -204,50 +204,50 @@ fuspi_xfer_buf(struct fuspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf,
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}
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static int
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fuspi_setup(struct fuspi_softc *sc, uint32_t cs, uint32_t mode,
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sfspi_setup(struct sfspi_softc *sc, uint32_t cs, uint32_t mode,
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uint32_t freq)
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{
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uint32_t csmode, fmt, sckdiv, sckmode;
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FUSPI_ASSERT_LOCKED(sc);
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SFSPI_ASSERT_LOCKED(sc);
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/*
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* Fsck = Fin / 2 * (div + 1)
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* -> div = Fin / (2 * Fsck) - 1
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*/
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sckdiv = (howmany(sc->freq >> 1, freq) - 1) & FUSPI_SCKDIV_MASK;
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FUSPI_WRITE(sc, FUSPI_REG_SCKDIV, sckdiv);
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sckdiv = (howmany(sc->freq >> 1, freq) - 1) & SFSPI_SCKDIV_MASK;
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SFSPI_WRITE(sc, SFSPI_REG_SCKDIV, sckdiv);
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switch (mode) {
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case SPIBUS_MODE_CPHA:
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sckmode = FUSPI_SCKMODE_PHA;
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sckmode = SFSPI_SCKMODE_PHA;
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break;
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case SPIBUS_MODE_CPOL:
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sckmode = FUSPI_SCKMODE_POL;
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sckmode = SFSPI_SCKMODE_POL;
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break;
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case SPIBUS_MODE_CPOL_CPHA:
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sckmode = FUSPI_SCKMODE_PHA | FUSPI_SCKMODE_POL;
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sckmode = SFSPI_SCKMODE_PHA | SFSPI_SCKMODE_POL;
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break;
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}
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FUSPI_WRITE(sc, FUSPI_REG_SCKMODE, sckmode);
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SFSPI_WRITE(sc, SFSPI_REG_SCKMODE, sckmode);
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csmode = FUSPI_CSMODE_HOLD;
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csmode = SFSPI_CSMODE_HOLD;
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if (cs & SPIBUS_CS_HIGH)
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csmode = FUSPI_CSMODE_AUTO;
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FUSPI_WRITE(sc, FUSPI_REG_CSMODE, csmode);
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csmode = SFSPI_CSMODE_AUTO;
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SFSPI_WRITE(sc, SFSPI_REG_CSMODE, csmode);
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FUSPI_WRITE(sc, FUSPI_REG_CSID, cs & ~SPIBUS_CS_HIGH);
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SFSPI_WRITE(sc, SFSPI_REG_CSID, cs & ~SPIBUS_CS_HIGH);
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fmt = FUSPI_FMT_PROTO_SINGLE | FUSPI_FMT_LEN(8);
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FUSPI_WRITE(sc, FUSPI_REG_FMT, fmt);
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fmt = SFSPI_FMT_PROTO_SINGLE | SFSPI_FMT_LEN(8);
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SFSPI_WRITE(sc, SFSPI_REG_FMT, fmt);
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return (0);
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}
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static int
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fuspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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sfspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct fuspi_softc *sc;
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struct sfspi_softc *sc;
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uint32_t clock, cs, csdef, mode;
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int err;
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@ -266,38 +266,38 @@ fuspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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return (EINVAL);
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}
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FUSPI_LOCK(sc);
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SFSPI_LOCK(sc);
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device_busy(sc->dev);
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err = fuspi_setup(sc, cs, mode, clock);
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err = sfspi_setup(sc, cs, mode, clock);
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if (err != 0) {
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FUSPI_UNLOCK(sc);
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SFSPI_UNLOCK(sc);
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return (err);
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}
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err = 0;
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if (cmd->tx_cmd_sz > 0)
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err = fuspi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
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err = sfspi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
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cmd->tx_cmd_sz, cmd->rx_cmd_sz);
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if (cmd->tx_data_sz > 0 && err == 0)
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err = fuspi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
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err = sfspi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
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cmd->tx_data_sz, cmd->rx_data_sz);
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/* Deassert chip select. */
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csdef = FUSPI_CSDEF_ALL & ~(1 << cs);
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FUSPI_WRITE(sc, FUSPI_REG_CSDEF, csdef);
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FUSPI_WRITE(sc, FUSPI_REG_CSDEF, FUSPI_CSDEF_ALL);
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csdef = SFSPI_CSDEF_ALL & ~(1 << cs);
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SFSPI_WRITE(sc, SFSPI_REG_CSDEF, csdef);
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SFSPI_WRITE(sc, SFSPI_REG_CSDEF, SFSPI_CSDEF_ALL);
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device_unbusy(sc->dev);
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FUSPI_UNLOCK(sc);
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SFSPI_UNLOCK(sc);
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return (err);
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}
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static int
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fuspi_attach(device_t dev)
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sfspi_attach(device_t dev)
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{
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struct fuspi_softc *sc;
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struct sfspi_softc *sc;
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int error;
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sc = device_get_softc(dev);
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@ -305,7 +305,7 @@ fuspi_attach(device_t dev)
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mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
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error = bus_alloc_resources(dev, fuspi_spec, &sc->res);
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error = bus_alloc_resources(dev, sfspi_spec, &sc->res);
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if (error) {
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device_printf(dev, "Couldn't allocate resources\n");
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goto fail;
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@ -334,13 +334,13 @@ fuspi_attach(device_t dev)
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* From Sifive-Unleashed-FU540-C000-v1.0.pdf page 103:
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* csdef is cs_width bits wide and all ones on reset.
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*/
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sc->cs_max = FUSPI_READ(sc, FUSPI_REG_CSDEF);
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sc->cs_max = SFSPI_READ(sc, SFSPI_REG_CSDEF);
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/*
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* We don't support the direct-mapped flash interface.
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* Disable it.
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*/
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FUSPI_WRITE(sc, FUSPI_REG_FCTRL, 0x0);
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SFSPI_WRITE(sc, SFSPI_REG_FCTRL, 0x0);
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/* Probe and attach the spibus when interrupts are available. */
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sc->parent = device_add_child(dev, "spibus", -1);
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@ -349,13 +349,13 @@ fuspi_attach(device_t dev)
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return (0);
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fail:
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bus_release_resources(dev, fuspi_spec, &sc->res);
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bus_release_resources(dev, sfspi_spec, &sc->res);
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mtx_destroy(&sc->mtx);
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return (error);
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}
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static int
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fuspi_probe(device_t dev)
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sfspi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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@ -364,37 +364,37 @@ fuspi_probe(device_t dev)
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if (!ofw_bus_is_compatible(dev, "sifive,spi0"))
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return (ENXIO);
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device_set_desc(dev, "SiFive FU540 SPI controller");
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device_set_desc(dev, "SiFive SPI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static phandle_t
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fuspi_get_node(device_t bus, device_t dev)
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sfspi_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static device_method_t fuspi_methods[] = {
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DEVMETHOD(device_probe, fuspi_probe),
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DEVMETHOD(device_attach, fuspi_attach),
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static device_method_t sfspi_methods[] = {
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DEVMETHOD(device_probe, sfspi_probe),
|
||||
DEVMETHOD(device_attach, sfspi_attach),
|
||||
|
||||
DEVMETHOD(spibus_transfer, fuspi_transfer),
|
||||
DEVMETHOD(spibus_transfer, sfspi_transfer),
|
||||
|
||||
DEVMETHOD(ofw_bus_get_node, fuspi_get_node),
|
||||
DEVMETHOD(ofw_bus_get_node, sfspi_get_node),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t fuspi_driver = {
|
||||
"fu540spi",
|
||||
fuspi_methods,
|
||||
sizeof(struct fuspi_softc)
|
||||
static driver_t sfspi_driver = {
|
||||
"sifive_spi",
|
||||
sfspi_methods,
|
||||
sizeof(struct sfspi_softc)
|
||||
};
|
||||
|
||||
static devclass_t fuspi_devclass;
|
||||
static devclass_t sfspi_devclass;
|
||||
|
||||
DRIVER_MODULE(fu540spi, simplebus, fuspi_driver, fuspi_devclass, 0, 0);
|
||||
DRIVER_MODULE(ofw_spibus, fu540spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0);
|
||||
MODULE_DEPEND(fu540spi, ofw_spibus, 1, 1, 1);
|
||||
DRIVER_MODULE(sifive_spi, simplebus, sfspi_driver, sfspi_devclass, 0, 0);
|
||||
DRIVER_MODULE(ofw_spibus, sifive_spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0);
|
||||
MODULE_DEPEND(sifive_spi, ofw_spibus, 1, 1, 1);
|
||||
Loading…
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Reference in New Issue
Block a user