Bring busdmafied sk(4) to all architectures.
- MPSAFE. No more recursive lock required. - bus_dma(9) conversion. I think it should work on all architectures. - optimized Rx handler for each normal and jumbo frames. Previously sk(4) used jumbo frame management code to handle normal sized frames. As the handler needs an additional lock to protect jumbo frame management structure from races, it used two lock operations for each received packet. Now sk(4) uses single lock operation for normal frame.(Jumbo frame still needs two lock operations as before.) The hardware supports DMA scatter operations for Rx descriptors such that it's possible to take advantagee of m_cljget(9) for jumbo frames. However, due to a unknown reasons it resulted in poor performance on sparc64. So I dropped m_cljget(9) approach. This should be revisited since it would reduce one lock operation for jumbo frame handling. - Tx TCP/Rx IP checksum offload support. According to the data sheet of SK-NET GENESIS the hardware supports Rx IP/TCP/UDP offload. But I couldn't make it work on my Yukon hardware. So Rx TCP/UDP was disabled at the moment. It seems that newer Yukon chips can support Tx UDP checksum offload too. But I need more documentation first. - Added more wait time in reading VPD data. It seems that ASUS LOM takes a very long time to respond VPD read signal. - Added an additional lock for MII register access callbacks. - Added more strict received packet validation routine. Previously it passed corrupted packets to upper layers under certain conditions. - A new function sk_yukon_tick() to handle auto-negotiation properly. - Interrupt handler now checks shared interrupt source and protects the interrupt handler from NULL pointer dereference which was caused by odd status word value. The status word can returns 0xffffffff if cable is unplugged while Rx/Tx/auto-negotiation is in progress. - suspend/resume support(not tested). - Added Rx/Tx FIFO flush routine for Yukon - Activate Tx descriptor poll timer in order to protect possible loss of SK_TXBMU_TX_START command. Previously the driver continuously issued SK_TXBMU_TX_START when it notices pending Tx descriptors not processed yet in interrupt handler. That approach would add additional PCI write access overhead under high Tx load situations and it might fail if the first SK_TXBMU_TX_START was lost and no interrupt is generated from the first SK_TXBMU_TX_START command. - s/printf/if_printf/, s/printf/device_printf/, Axe sk_unit in softc. - Setting multicast/station address is now safe on strict-alignment architectures. - Fix long standing bug in VLAN header length setup. - Added/corrected register definitions for Yukon. (Register information from Linux skge driver.) - Added Rx status definition for Marvell Yukon/XaQti XMAC. (Rx status register information from Linux skge driver.) - Update if_oerrors if we encounter watchdog error. - callout(9) conversion Special thanks to jkim who let me know RX status differences between Yukon and XaQti XMAC. It seems that there is still occasional watchdog timeout error but I couldn't reproduce it and need more information to analyze it from users. Tested by: bz(amd64), me(i386, sparc64), current ML Frank Behrens frank ! pinky ( sax $ de
This commit is contained in:
parent
d902fb71da
commit
919133a8ef
sys/dev/sk
2123
sys/dev/sk/if_sk.c
2123
sys/dev/sk/if_sk.c
File diff suppressed because it is too large
Load Diff
@ -793,13 +793,13 @@
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(SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
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SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
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SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
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SK_TXBMU_DESC_UNRESET)
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SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
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#define SK_TXBMU_OFFLINE \
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(SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
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SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
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SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
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SK_TXBMU_DESC_RESET)
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SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
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/* Block 16 -- Receive RAMbuffer 1 */
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#define SK_RXRB1_START 0x0800
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@ -894,24 +894,31 @@
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#define SK_RXMF1_END 0x0C40
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#define SK_RXMF1_THRESHOLD 0x0C44
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#define SK_RXMF1_CTRL_TEST 0x0C48
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#define SK_RXMF1_FLUSH_MASK 0x0C4C
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#define SK_RXMF1_FLUSH_THRESHOLD 0x0C50
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#define SK_RXMF1_WRITE_PTR 0x0C60
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#define SK_RXMF1_WRITE_LEVEL 0x0C68
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#define SK_RXMF1_READ_PTR 0x0C70
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#define SK_RXMF1_READ_LEVEL 0x0C78
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/* Receive MAC FIFO 1 Contro/Test */
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#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
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#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
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#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
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#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
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#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
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#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
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#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */
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#define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */
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#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */
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#define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */
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#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */
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#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
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#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
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#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
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#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
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#define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */
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/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
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#define SK_RXF2_END 0x0C80
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#define SK_RXF2_WPTR 0x0C84
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@ -971,7 +978,7 @@
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#define SK_TXLED1_CTL 0x0D28
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#define SK_TXLED1_TST 0x0D29
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/* Receive MAC FIFO 1 (Yukon Only) */
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/* Transmit MAC FIFO 1 (Yukon Only) */
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#define SK_TXMF1_END 0x0D40
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#define SK_TXMF1_THRESHOLD 0x0D44
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#define SK_TXMF1_CTRL_TEST 0x0D48
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@ -982,6 +989,7 @@
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#define SK_TXMF1_RESTART_PTR 0x0D74
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#define SK_TXMF1_READ_LEVEL 0x0D78
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/* Transmit MAC FIFO Control/Test */
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#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
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#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
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#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
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@ -1039,6 +1047,8 @@
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#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */
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#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */
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#define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */
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#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */
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#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */
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#define SK_DPT_TCTL_START 0x0002 /* Start Timer */
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@ -1054,7 +1064,7 @@
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#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */
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#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */
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#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */
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#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */
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#define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */
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#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */
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#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */
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#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */
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@ -1310,6 +1320,11 @@ struct sk_type {
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char *sk_name;
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};
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#define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
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#define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32)
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#define SK_RING_ALIGN 64
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/* RX queue descriptor data structure */
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struct sk_rx_desc {
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u_int32_t sk_ctl;
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@ -1318,10 +1333,8 @@ struct sk_rx_desc {
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u_int32_t sk_data_hi;
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u_int32_t sk_xmac_rxstat;
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u_int32_t sk_timestamp;
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u_int16_t sk_csum2;
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u_int16_t sk_csum1;
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u_int16_t sk_csum2_start;
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u_int16_t sk_csum1_start;
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u_int32_t sk_csum;
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u_int32_t sk_csum_start;
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};
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#define SK_OPCODE_DEFAULT 0x00550000
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@ -1339,8 +1352,7 @@ struct sk_rx_desc {
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#define SK_RXCTL_OWN 0x80000000
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#define SK_RXSTAT \
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(SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
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SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
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(SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
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struct sk_tx_desc {
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u_int32_t sk_ctl;
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@ -1348,10 +1360,8 @@ struct sk_tx_desc {
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u_int32_t sk_data_lo;
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u_int32_t sk_data_hi;
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u_int32_t sk_xmac_txstat;
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u_int16_t sk_rsvd0;
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u_int16_t sk_csum_startval;
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u_int16_t sk_csum_startpos;
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u_int16_t sk_csum_writepos;
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u_int32_t sk_csum_startval;
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u_int32_t sk_csum_start;
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u_int32_t sk_rsvd1;
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};
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@ -1369,11 +1379,14 @@ struct sk_tx_desc {
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#define SK_TXSTAT \
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(SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
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#define SK_RXBYTES(x) (x) & 0x0000FFFF;
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#define SK_RXBYTES(x) ((x) & 0x0000FFFF)
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#define SK_TXBYTES SK_RXBYTES
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#define SK_TX_RING_CNT 512
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#define SK_RX_RING_CNT 256
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#define SK_JUMBO_RX_RING_CNT 256
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#define SK_MAXTXSEGS 32
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#define SK_MAXRXSEGS 32
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/*
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* Jumbo buffer stuff. Note that we must allocate more jumbo
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@ -1385,6 +1398,9 @@ struct sk_tx_desc {
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*/
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#define SK_JUMBO_FRAMELEN 9018
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#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
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#define SK_MAX_FRAMELEN \
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(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
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#define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
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#define SK_JSLOTS ((SK_RX_RING_CNT * 3) / 2)
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#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
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@ -1399,32 +1415,73 @@ struct sk_jpool_entry {
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SLIST_ENTRY(sk_jpool_entry) jpool_entries;
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};
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struct sk_chain {
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void *sk_desc;
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struct mbuf *sk_mbuf;
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struct sk_chain *sk_next;
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struct sk_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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STAILQ_ENTRY(sk_txdesc) tx_q;
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};
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STAILQ_HEAD(sk_txdq, sk_txdesc);
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struct sk_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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};
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struct sk_chain_data {
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struct sk_chain sk_tx_chain[SK_TX_RING_CNT];
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struct sk_chain sk_rx_chain[SK_RX_RING_CNT];
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bus_dma_tag_t sk_parent_tag;
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bus_dma_tag_t sk_tx_tag;
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struct sk_txdesc sk_txdesc[SK_TX_RING_CNT];
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struct sk_txdq sk_txfreeq;
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struct sk_txdq sk_txbusyq;
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bus_dma_tag_t sk_rx_tag;
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struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT];
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bus_dma_tag_t sk_tx_ring_tag;
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bus_dma_tag_t sk_rx_ring_tag;
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bus_dmamap_t sk_tx_ring_map;
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bus_dmamap_t sk_rx_ring_map;
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bus_dmamap_t sk_rx_sparemap;
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bus_dma_tag_t sk_jumbo_rx_tag;
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bus_dma_tag_t sk_jumbo_tag;
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bus_dmamap_t sk_jumbo_map;
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bus_dma_tag_t sk_jumbo_mtag;
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caddr_t sk_jslots[SK_JSLOTS];
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struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT];
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bus_dma_tag_t sk_jumbo_rx_ring_tag;
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bus_dmamap_t sk_jumbo_rx_ring_map;
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bus_dmamap_t sk_jumbo_rx_sparemap;
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int sk_tx_prod;
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int sk_tx_cons;
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int sk_tx_cnt;
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int sk_rx_prod;
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int sk_rx_cons;
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int sk_rx_cnt;
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/* Stick the jumbo mem management stuff here too. */
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caddr_t sk_jslots[SK_JSLOTS];
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void *sk_jumbo_buf;
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int sk_jumbo_rx_cons;
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};
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struct sk_ring_data {
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struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT];
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struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT];
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struct sk_tx_desc *sk_tx_ring;
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bus_addr_t sk_tx_ring_paddr;
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struct sk_rx_desc *sk_rx_ring;
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bus_addr_t sk_rx_ring_paddr;
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struct sk_rx_desc *sk_jumbo_rx_ring;
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bus_addr_t sk_jumbo_rx_ring_paddr;
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void *sk_jumbo_buf;
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bus_addr_t sk_jumbo_buf_paddr;
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};
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#define SK_TX_RING_ADDR(sc, i) \
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((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i))
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#define SK_RX_RING_ADDR(sc, i) \
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((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
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#define SK_JUMBO_RX_RING_ADDR(sc, i) \
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((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
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#define SK_TX_RING_SZ \
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(sizeof(struct sk_tx_desc) * SK_TX_RING_CNT)
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#define SK_RX_RING_SZ \
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(sizeof(struct sk_rx_desc) * SK_RX_RING_CNT)
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#define SK_JUMBO_RX_RING_SZ \
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(sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT)
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struct sk_bcom_hack {
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int reg;
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int val;
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@ -1442,7 +1499,7 @@ struct sk_softc {
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void *sk_intrhand; /* irq handler handle */
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struct resource *sk_irq; /* IRQ resource handle */
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struct resource *sk_res; /* I/O or shared mem handle */
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u_int8_t sk_unit; /* controller number */
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device_t sk_dev;
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u_int8_t sk_type;
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u_int8_t sk_rev;
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u_int8_t spare;
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@ -1455,8 +1512,10 @@ struct sk_softc {
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u_int32_t sk_intrmask;
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int sk_int_mod;
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int sk_int_ticks;
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int sk_suspended;
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struct sk_if_softc *sk_if[2];
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device_t sk_devs[2];
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struct mtx sk_mii_mtx;
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struct mtx sk_mtx;
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};
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@ -1466,12 +1525,14 @@ struct sk_softc {
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#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc)
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#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc)
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#define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc)
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#define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx)
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#define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx)
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/* Softc for each logical interface */
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struct sk_if_softc {
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struct ifnet *sk_ifp; /* interface info */
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device_t sk_miibus;
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u_int8_t sk_unit; /* interface number */
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device_t sk_if_dev;
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u_int8_t sk_port; /* port # on controller */
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u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */
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u_int32_t sk_rx_ramstart;
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@ -1480,12 +1541,10 @@ struct sk_if_softc {
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u_int32_t sk_tx_ramend;
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int sk_phytype;
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int sk_phyaddr;
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device_t sk_dev;
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int sk_cnt;
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int sk_link;
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struct callout_handle sk_tick_ch;
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struct callout sk_tick_ch;
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struct sk_chain_data sk_cdata;
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struct sk_ring_data *sk_rdata;
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struct sk_ring_data sk_rdata;
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struct sk_softc *sk_softc; /* parent controller */
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int sk_tx_bmu; /* TX BMU register */
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int sk_if_flags;
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@ -1497,11 +1556,4 @@ struct sk_if_softc {
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#define SK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->sk_jlist_mtx)
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#define SK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_jlist_mtx)
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#define SK_MAXUNIT 256
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#define SK_TIMEOUT 1000
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#define ETHER_ALIGN 2
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#ifdef __alpha__
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#undef vtophys
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#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
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#endif
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#define XM_RXSTAT_VLAN_LEV1 0x00010000
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#define XM_RXSTAT_VLAN_LEV2 0x00020000
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#define XM_RXSTAT_LEN 0xFFFC0000
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#define XM_RXSTAT_LENSHIFT 18
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#define XM_RXSTAT_BYTES(x) ((x) >> XM_RXSTAT_LENSHIFT)
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/*
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* XMAC PHY registers, indirectly accessed through
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@ -22,7 +22,7 @@
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#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
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#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
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#define YU_GPSR_FCTL_TX 0x2000 /* flow control */
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#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
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#define YU_GPSR_LINK 0x1000 /* link status (down/up) */
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#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
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#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
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@ -31,25 +31,26 @@
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#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
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||||
#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */
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||||
#define YU_GPSR_PARTITION 0x0008 /* partition mode */
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#define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */
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||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */
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#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */
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#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */
|
||||
|
||||
/* General Purpose Control Register (GPCR) */
|
||||
#define YUKON_GPCR 0x0004
|
||||
|
||||
#define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */
|
||||
#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */
|
||||
#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */
|
||||
#define YU_GPCR_RXEN 0x0800 /* Receive Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* Loopback Enable */
|
||||
#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */
|
||||
#define YU_GPCR_PAR 0x0100 /* Partition Enable */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */
|
||||
#define YU_GPCR_FLP 0x0040 /* Force Link Pass */
|
||||
#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */
|
||||
#define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed */
|
||||
#define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */
|
||||
#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */
|
||||
#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */
|
||||
|
||||
/* Transmit Control Register (TCR) */
|
||||
#define YUKON_TCR 0x0008
|
||||
@ -169,3 +170,21 @@
|
||||
|
||||
#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */
|
||||
#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */
|
||||
|
||||
/* Receive status */
|
||||
#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */
|
||||
#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */
|
||||
#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */
|
||||
#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */
|
||||
#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */
|
||||
#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */
|
||||
#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */
|
||||
#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */
|
||||
#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */
|
||||
#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */
|
||||
#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */
|
||||
#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */
|
||||
#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */
|
||||
#define YU_RXSTAT_LENSHIFT 16
|
||||
|
||||
#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT)
|
||||
|
Loading…
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Reference in New Issue
Block a user