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Remove SoC-specific integrations from dTSEC, to make it SoC agnostic.

Browse Source 
This will allow a single kernel to run on all SoCs supported by the dTSEC driver.

Approved by:	re@(gjb)
This commit is contained in:
Justin Hibbits 2016-07-05 06:16:42 +00:00
parent 83d9b89cfb
commit 91ebf7d765
20 changed files with 35 additions and 3745 deletions
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7
sys/contrib/ncsw/inc/error_ext.h
View File

@ -353,6 +353,7 @@ int ERROR_DYNAMIC_LEVEL = ERROR_GLOBAL_LEVEL;
#define PRINT_FORMAT "[CPU%02d, %s:%d %s]"
#define PRINT_FMT_PARAMS CORE_GetId(), __FILE__, __LINE__, __FUNCTION__
#define ERR_STRING(err) #err
#if (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0))
/* No debug/error/event messages at all */
@ -398,7 +399,7 @@ extern const char *eventStrings[];
if (REPORT_LEVEL_##_level <= DEBUG_DYNAMIC_LEVEL) { \
XX_Print("> %s (%s) " PRINT_FORMAT ": ", \
dbgLevelStrings[REPORT_LEVEL_##_level - 1], \
moduleStrings[__ERR_MODULE__ >> 16], \
ERR_STRING(__ERR_MODULE__), \
PRINT_FMT_PARAMS); \
XX_Print _vmsg; \
XX_Print("\r\n"); \
@ -412,7 +413,7 @@ extern const char *eventStrings[];
if (REPORT_LEVEL_##_level <= ERROR_DYNAMIC_LEVEL) { \
XX_Print("! %s %s Error " PRINT_FORMAT ": %s; ", \
dbgLevelStrings[REPORT_LEVEL_##_level - 1], \
moduleStrings[__ERR_MODULE__ >> 16], \
ERR_STRING(__ERR_MODULE__), \
PRINT_FMT_PARAMS, \
errTypeStrings[(GET_ERROR_TYPE(_err) - E_OK - 1)]); \
XX_Print _vmsg; \
@ -435,7 +436,7 @@ extern const char *eventStrings[];
if (_ev##_LEVEL <= EVENT_DYNAMIC_LEVEL) { \
XX_Print("~ %s %s Event " PRINT_FORMAT ": %s (flags: 0x%04x); ", \
dbgLevelStrings[_ev##_LEVEL - 1], \
moduleStrings[__ERR_MODULE__ >> 16], \
ERR_STRING(__ERR_MODULE__), \
PRINT_FMT_PARAMS, \
eventStrings[((_ev) - EV_NO_EVENT - 1)], \
(uint16_t)(_flg)); \

349
sys/contrib/ncsw/inc/integrations/P2041/dpaa_integration_ext.h
View File

@ -1,349 +0,0 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File dpaa_integration_ext.h
@Description P2041 FM external definitions and structures.
*//***************************************************************************/
#ifndef __DPAA_INTEGRATION_EXT_H
#define __DPAA_INTEGRATION_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Description DPAA SW Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_SWPORTAL0 = 0,
e_DPAA_SWPORTAL1,
e_DPAA_SWPORTAL2,
e_DPAA_SWPORTAL3,
e_DPAA_SWPORTAL4,
e_DPAA_SWPORTAL5,
e_DPAA_SWPORTAL6,
e_DPAA_SWPORTAL7,
e_DPAA_SWPORTAL8,
e_DPAA_SWPORTAL9,
e_DPAA_SWPORTAL_DUMMY_LAST
} e_DpaaSwPortal;
/**************************************************************************//**
@Description DPAA Direct Connect Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_DCPORTAL0 = 0,
e_DPAA_DCPORTAL1,
e_DPAA_DCPORTAL2,
e_DPAA_DCPORTAL3,
e_DPAA_DCPORTAL4,
e_DPAA_DCPORTAL_DUMMY_LAST
} e_DpaaDcPortal;
#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST
#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST
/*****************************************************************************
QMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */
#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */
#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */
#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE)
/**< FQIDs range - 24 bits */
/**************************************************************************//**
@Description Work Queue Channel assignments in QMan.
*//***************************************************************************/
typedef enum
{
e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */
e_QM_FQ_CHANNEL_SWPORTAL1,
e_QM_FQ_CHANNEL_SWPORTAL2,
e_QM_FQ_CHANNEL_SWPORTAL3,
e_QM_FQ_CHANNEL_SWPORTAL4,
e_QM_FQ_CHANNEL_SWPORTAL5,
e_QM_FQ_CHANNEL_SWPORTAL6,
e_QM_FQ_CHANNEL_SWPORTAL7,
e_QM_FQ_CHANNEL_SWPORTAL8,
e_QM_FQ_CHANNEL_SWPORTAL9,
e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */
e_QM_FQ_CHANNEL_POOL2,
e_QM_FQ_CHANNEL_POOL3,
e_QM_FQ_CHANNEL_POOL4,
e_QM_FQ_CHANNEL_POOL5,
e_QM_FQ_CHANNEL_POOL6,
e_QM_FQ_CHANNEL_POOL7,
e_QM_FQ_CHANNEL_POOL8,
e_QM_FQ_CHANNEL_POOL9,
e_QM_FQ_CHANNEL_POOL10,
e_QM_FQ_CHANNEL_POOL11,
e_QM_FQ_CHANNEL_POOL12,
e_QM_FQ_CHANNEL_POOL13,
e_QM_FQ_CHANNEL_POOL14,
e_QM_FQ_CHANNEL_POOL15,
e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0:
connected to FMan 0; assigned in incrementing order to
each sub-portal (SP) in the portal */
e_QM_FQ_CHANNEL_FMAN0_SP1,
e_QM_FQ_CHANNEL_FMAN0_SP2,
e_QM_FQ_CHANNEL_FMAN0_SP3,
e_QM_FQ_CHANNEL_FMAN0_SP4,
e_QM_FQ_CHANNEL_FMAN0_SP5,
e_QM_FQ_CHANNEL_FMAN0_SP6,
e_QM_FQ_CHANNEL_FMAN0_SP7,
e_QM_FQ_CHANNEL_FMAN0_SP8,
e_QM_FQ_CHANNEL_FMAN0_SP9,
e_QM_FQ_CHANNEL_FMAN0_SP10,
e_QM_FQ_CHANNEL_FMAN0_SP11,
e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */
e_QM_FQ_CHANNEL_RMAN_SP3,
e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2:
connected to SEC 4.x */
e_QM_FQ_CHANNEL_PME = 0xA0 /**< Dedicated channel serviced by Direct Connect Portal 3:
connected to PME */
} e_QmFQChannel;
/*****************************************************************************
BMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */
/*****************************************************************************
SEC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define SEC_NUM_OF_DECOS 2
#define SEC_ALL_DECOS_MASK 0x00000003
/*****************************************************************************
FM INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define INTG_MAX_NUM_OF_FM 1
/* Ports defines */
#define FM_MAX_NUM_OF_1G_MACS 5
#define FM_MAX_NUM_OF_10G_MACS 1
#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS)
#define FM_MAX_NUM_OF_OH_PORTS 7
#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS)
#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS)
#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */
#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */
#define FM_MAX_NUM_OF_SUB_PORTALS 12
#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0
/* RAMs defines */
#define FM_MURAM_SIZE (160 * KILOBYTE)
#define FM_IRAM_SIZE ( 64 * KILOBYTE)
/* PCD defines */
#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */
#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */
#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */
/* RTC defines */
#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */
#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */
#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */
/* QMI defines */
#define QMI_MAX_NUM_OF_TNUMS 64
#define MAX_QMI_DEQ_SUBPORTAL 12
#define QMI_DEF_TNUMS_THRESH 48
/* FPM defines */
#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4
/* DMA defines */
#define DMA_THRESH_MAX_COMMQ 31
#define DMA_THRESH_MAX_BUF 127
/* BMI defines */
#define BMI_MAX_NUM_OF_TASKS 128
#define BMI_MAX_NUM_OF_DMAS 32
#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE)
#define PORT_MAX_WEIGHT 16 /**< Port weight in BMI arbitration register */
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmEventModules
{
e_FM_MOD_PRS, /**< Parser event */
e_FM_MOD_KG, /**< Keygen event */
e_FM_MOD_PLCR, /**< Policer event */
e_FM_MOD_10G_MAC, /**< 10G MAC error event */
e_FM_MOD_1G_MAC, /**< 1G MAC error event */
e_FM_MOD_TMR, /**< Timer event */
e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */
e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */
e_FM_MOD_DUMMY_LAST
} e_FmEventModules;
/**************************************************************************//**
@Description Enum for interrupts types
*//***************************************************************************/
typedef enum e_FmIntrType
{
e_FM_INTR_TYPE_ERR,
e_FM_INTR_TYPE_NORMAL
} e_FmIntrType;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmInterModuleEvent
{
e_FM_EV_PRS, /**< Parser event */
e_FM_EV_ERR_PRS, /**< Parser error event */
e_FM_EV_KG, /**< Keygen event */
e_FM_EV_ERR_KG, /**< Keygen error event */
e_FM_EV_PLCR, /**< Policer event */
e_FM_EV_ERR_PLCR, /**< Policer error event */
e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */
e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */
e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */
e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */
e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */
e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */
e_FM_EV_TMR, /**< Timer event */
e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */
e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */
e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */
e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */
e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */
e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */
e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */
e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */
e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */
e_FM_EV_DUMMY_LAST
} e_FmInterModuleEvent;
#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MOD_PRS: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
break; \
case e_FM_MOD_KG: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_PLCR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
break; \
case e_FM_MOD_10G_MAC: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_1G_MAC: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \
} \
break; \
case e_FM_MOD_TMR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
break; \
case e_FM_MOD_1G_MAC_TMR: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \
} \
break; \
case e_FM_MOD_FMAN_CTRL: \
if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \
else switch(id){ \
case(0): event = e_FM_EV_FMAN_CTRL_0; break; \
case(1): event = e_FM_EV_FMAN_CTRL_1; break; \
case(2): event = e_FM_EV_FMAN_CTRL_2; break; \
case(3): event = e_FM_EV_FMAN_CTRL_3; break; \
} \
break; \
default: event = e_FM_EV_DUMMY_LAST; \
break;}
#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE
/* P2041 unique features */
#define FM_QMI_DEQ_OPTIONS_SUPPORT
#define FM_NO_DISPATCH_RAM_ECC
#define FM_FIFO_ALLOCATION_OLD_ALG
#define FM_NO_WATCHDOG
#define FM_NO_TNUM_AGING
#define FM_NO_TGEC_LOOPBACK
#define FM_KG_NO_BYPASS_FQID_GEN
#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN
#define FM_NO_BACKUP_POOLS
#define FM_NO_OP_OBSERVED_POOLS
#define FM_NO_ADVANCED_RATE_LIMITER
#define FM_NO_OP_OBSERVED_CGS
/* FM erratas */
#define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#endif /* __DPAA_INTEGRATION_EXT_H */

758
sys/contrib/ncsw/inc/integrations/P2041/part_integration_ext.h
View File

@ -1,758 +0,0 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File part_integration_ext.h
@Description P2041 external definitions and structures.
*//***************************************************************************/
#ifndef __PART_INTEGRATION_EXT_H
#define __PART_INTEGRATION_EXT_H
#include "std_ext.h"
#include "ddr_std_ext.h"
#include "enet_ext.h"
#include "dpaa_integration_ext.h"
/**************************************************************************//**
@Group P2041_chip_id P2041 Application Programming Interface
@Description P2041 Chip functions,definitions and enums.
@{
*//***************************************************************************/
#define CORE_E500MC
#define INTG_MAX_NUM_OF_CORES 4
/**************************************************************************//**
@Description Module types.
*//***************************************************************************/
typedef enum e_ModuleId
{
e_MODULE_ID_DUART_1 = 0,
e_MODULE_ID_DUART_2,
e_MODULE_ID_DUART_3,
e_MODULE_ID_DUART_4,
e_MODULE_ID_LAW,
e_MODULE_ID_LBC,
e_MODULE_ID_PAMU,
e_MODULE_ID_QM, /**< Queue manager module */
e_MODULE_ID_BM, /**< Buffer manager module */
e_MODULE_ID_QM_CE_PORTAL_0,
e_MODULE_ID_QM_CI_PORTAL_0,
e_MODULE_ID_QM_CE_PORTAL_1,
e_MODULE_ID_QM_CI_PORTAL_1,
e_MODULE_ID_QM_CE_PORTAL_2,
e_MODULE_ID_QM_CI_PORTAL_2,
e_MODULE_ID_QM_CE_PORTAL_3,
e_MODULE_ID_QM_CI_PORTAL_3,
e_MODULE_ID_QM_CE_PORTAL_4,
e_MODULE_ID_QM_CI_PORTAL_4,
e_MODULE_ID_QM_CE_PORTAL_5,
e_MODULE_ID_QM_CI_PORTAL_5,
e_MODULE_ID_QM_CE_PORTAL_6,
e_MODULE_ID_QM_CI_PORTAL_6,
e_MODULE_ID_QM_CE_PORTAL_7,
e_MODULE_ID_QM_CI_PORTAL_7,
e_MODULE_ID_QM_CE_PORTAL_8,
e_MODULE_ID_QM_CI_PORTAL_8,
e_MODULE_ID_QM_CE_PORTAL_9,
e_MODULE_ID_QM_CI_PORTAL_9,
e_MODULE_ID_BM_CE_PORTAL_0,
e_MODULE_ID_BM_CI_PORTAL_0,
e_MODULE_ID_BM_CE_PORTAL_1,
e_MODULE_ID_BM_CI_PORTAL_1,
e_MODULE_ID_BM_CE_PORTAL_2,
e_MODULE_ID_BM_CI_PORTAL_2,
e_MODULE_ID_BM_CE_PORTAL_3,
e_MODULE_ID_BM_CI_PORTAL_3,
e_MODULE_ID_BM_CE_PORTAL_4,
e_MODULE_ID_BM_CI_PORTAL_4,
e_MODULE_ID_BM_CE_PORTAL_5,
e_MODULE_ID_BM_CI_PORTAL_5,
e_MODULE_ID_BM_CE_PORTAL_6,
e_MODULE_ID_BM_CI_PORTAL_6,
e_MODULE_ID_BM_CE_PORTAL_7,
e_MODULE_ID_BM_CI_PORTAL_7,
e_MODULE_ID_BM_CE_PORTAL_8,
e_MODULE_ID_BM_CI_PORTAL_8,
e_MODULE_ID_BM_CE_PORTAL_9,
e_MODULE_ID_BM_CI_PORTAL_9,
e_MODULE_ID_FM, /**< Frame manager module */
e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */
e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */
e_MODULE_ID_FM_BMI, /**< FM BMI block */
e_MODULE_ID_FM_QMI, /**< FM QMI block */
e_MODULE_ID_FM_PARSER, /**< FM parser block */
e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */
e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */
e_MODULE_ID_FM_PLCR, /**< FM Policer */
e_MODULE_ID_FM_KG, /**< FM Keygen */
e_MODULE_ID_FM_DMA, /**< FM DMA */
e_MODULE_ID_FM_FPM, /**< FM FPM */
e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */
e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/
e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/
e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/
e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/
e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/
e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */
e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */
e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */
e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */
e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */
e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */
e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */
e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */
e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */
e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */
e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */
e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */
e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */
e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */
e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */
e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */
e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */
e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */
e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */
e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */
e_MODULE_ID_PIC, /**< PIC */
e_MODULE_ID_GPIO, /**< GPIO */
e_MODULE_ID_SERDES, /**< SERDES */
e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */
e_MODULE_ID_DUMMY_LAST
} e_ModuleId;
#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST
/* Offsets relative to CCSR base */
#define P2041_OFFSET_LAW 0x00000c00
#define P2041_OFFSET_DDR 0x00008000
#define P2041_OFFSET_CPC 0x00010000
#define P2041_OFFSET_CCM 0x00018000
#define P2041_OFFSET_PAMU 0x00020000
#define P2041_OFFSET_PIC 0x00040000
#define P2041_OFFSET_GUTIL 0x000e0000
#define P2041_OFFSET_RCPM 0x000e2000
#define P2041_OFFSET_SERDES 0x000ea000
#define P2041_OFFSET_DMA1 0x00100100
#define P2041_OFFSET_DMA2 0x00101100
#define P2041_OFFSET_ESPI 0x00110000
#define P2041_OFFSET_ESDHC 0x00114000
#define P2041_OFFSET_I2C1 0x00118000
#define P2041_OFFSET_I2C2 0x00118100
#define P2041_OFFSET_I2C3 0x00119000
#define P2041_OFFSET_I2C4 0x00119100
#define P2041_OFFSET_DUART1 0x0011c500
#define P2041_OFFSET_DUART2 0x0011c600
#define P2041_OFFSET_DUART3 0x0011d500
#define P2041_OFFSET_DUART4 0x0011d600
#define P2041_OFFSET_LBC 0x00124000
#define P2041_OFFSET_GPIO 0x00130000
#define P2041_OFFSET_PCIE1 0x00200000
#define P2041_OFFSET_PCIE2 0x00201000
#define P2041_OFFSET_PCIE3 0x00202000
#define P2041_OFFSET_USB1 0x00210000
#define P2041_OFFSET_USB2 0x00211000
#define P2041_OFFSET_USB_PHY 0x00214000
#define P2041_OFFSET_SATA1 0x00220000
#define P2041_OFFSET_SATA2 0x00221000
#define P2041_OFFSET_SEC_GEN 0x00300000
#define P2041_OFFSET_SEC_JQ0 0x00301000
#define P2041_OFFSET_SEC_JQ1 0x00302000
#define P2041_OFFSET_SEC_JQ2 0x00303000
#define P2041_OFFSET_SEC_JQ3 0x00304000
#define P2041_OFFSET_SEC_RESERVED 0x00305000
#define P2041_OFFSET_SEC_RTIC 0x00306000
#define P2041_OFFSET_SEC_QI 0x00307000
#define P2041_OFFSET_SEC_DECO0_CCB0 0x00308000
#define P2041_OFFSET_SEC_DECO1_CCB1 0x00309000
#define P2041_OFFSET_PME 0x00316000
#define P2041_OFFSET_QM 0x00318000
#define P2041_OFFSET_BM 0x0031a000
#define P2041_OFFSET_FM 0x00400000
#define P2041_OFFSET_FM_MURAM P2041_OFFSET_FM
#define P2041_OFFSET_FM_BMI (P2041_OFFSET_FM + 0x00080000)
#define P2041_OFFSET_FM_QMI (P2041_OFFSET_FM + 0x00080400)
#define P2041_OFFSET_FM_PARSER (P2041_OFFSET_FM + 0x00080800)
#define P2041_OFFSET_FM_PORT_HO1 (P2041_OFFSET_FM + 0x00081000) /* host command/offline parser */
#define P2041_OFFSET_FM_PORT_HO2 (P2041_OFFSET_FM + 0x00082000)
#define P2041_OFFSET_FM_PORT_HO3 (P2041_OFFSET_FM + 0x00083000)
#define P2041_OFFSET_FM_PORT_HO4 (P2041_OFFSET_FM + 0x00084000)
#define P2041_OFFSET_FM_PORT_HO5 (P2041_OFFSET_FM + 0x00085000)
#define P2041_OFFSET_FM_PORT_HO6 (P2041_OFFSET_FM + 0x00086000)
#define P2041_OFFSET_FM_PORT_HO7 (P2041_OFFSET_FM + 0x00087000)
#define P2041_OFFSET_FM_PORT_1GRX1 (P2041_OFFSET_FM + 0x00088000)
#define P2041_OFFSET_FM_PORT_1GRX2 (P2041_OFFSET_FM + 0x00089000)
#define P2041_OFFSET_FM_PORT_1GRX3 (P2041_OFFSET_FM + 0x0008a000)
#define P2041_OFFSET_FM_PORT_1GRX4 (P2041_OFFSET_FM + 0x0008b000)
#define P2041_OFFSET_FM_PORT_1GRX5 (P2041_OFFSET_FM + 0x0008c000)
#define P2041_OFFSET_FM_PORT_10GRX (P2041_OFFSET_FM + 0x00090000)
#define P2041_OFFSET_FM_PORT_1GTX1 (P2041_OFFSET_FM + 0x000a8000)
#define P2041_OFFSET_FM_PORT_1GTX2 (P2041_OFFSET_FM + 0x000a9000)
#define P2041_OFFSET_FM_PORT_1GTX3 (P2041_OFFSET_FM + 0x000aa000)
#define P2041_OFFSET_FM_PORT_1GTX4 (P2041_OFFSET_FM + 0x000ab000)
#define P2041_OFFSET_FM_PORT_1GTX5 (P2041_OFFSET_FM + 0x000ac000)
#define P2041_OFFSET_FM_PORT_10GTX (P2041_OFFSET_FM + 0x000b0000)
#define P2041_OFFSET_FM_PLCR (P2041_OFFSET_FM + 0x000c0000)
#define P2041_OFFSET_FM_KG (P2041_OFFSET_FM + 0x000c1000)
#define P2041_OFFSET_FM_DMA (P2041_OFFSET_FM + 0x000c2000)
#define P2041_OFFSET_FM_FPM (P2041_OFFSET_FM + 0x000c3000)
#define P2041_OFFSET_FM_IRAM (P2041_OFFSET_FM + 0x000c4000)
#define P2041_OFFSET_FM_PARSER_IRAM (P2041_OFFSET_FM + 0x000c7000)
#define P2041_OFFSET_FM_1GMAC1 (P2041_OFFSET_FM + 0x000e0000)
#define P2041_OFFSET_FM_1GMDIO (P2041_OFFSET_FM + 0x000e1000 + 0x120)
#define P2041_OFFSET_FM_1GMAC2 (P2041_OFFSET_FM + 0x000e2000)
#define P2041_OFFSET_FM_1GMAC3 (P2041_OFFSET_FM + 0x000e4000)
#define P2041_OFFSET_FM_1GMAC4 (P2041_OFFSET_FM + 0x000e6000)
#define P2041_OFFSET_FM_1GMAC5 (P2041_OFFSET_FM + 0x000e8000)
#define P2041_OFFSET_FM_10GMAC (P2041_OFFSET_FM + 0x000f0000)
#define P2041_OFFSET_FM_10GMDIO (P2041_OFFSET_FM + 0x000f1000 + 0x030)
#define P2041_OFFSET_FM_RTC (P2041_OFFSET_FM + 0x000fe000)
/* Offsets relative to QM or BM portals base */
#define P2041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */
#define P2041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */
#define P2041_CE_PORTAL_SIZE 0x4000
#define P2041_CI_PORTAL_SIZE 0x1000
#define P2041_OFFSET_PORTALS_CE(portal) \
(P2041_OFFSET_PORTALS_CE_AREA + P2041_CE_PORTAL_SIZE * (portal))
#define P2041_OFFSET_PORTALS_CI(portal) \
(P2041_OFFSET_PORTALS_CI_AREA + P2041_CI_PORTAL_SIZE * (portal))
/**************************************************************************//**
@Description Transaction source ID (for memory conrollers error reporting).
*//***************************************************************************/
typedef enum e_TransSrc
{
e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */
e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */
e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */
e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */
e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */
e_TRANS_SRC_BMAN = 0x18, /**< BMan */
e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */
e_TRANS_SRC_PME = 0x20, /**< PME */
e_TRANS_SRC_SEC = 0x21, /**< Security engine */
e_TRANS_SRC_QMAN = 0x3C, /**< QMan */
e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */
e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */
e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */
e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */
e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */
e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */
e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */
e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */
e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */
e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */
e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */
e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */
e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */
e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */
e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */
e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */
e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */
e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */
e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */
e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */
e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */
e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */
e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */
e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */
e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */
e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */
e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */
e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */
e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */
e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */
e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */
} e_TransSrc;
/**************************************************************************//**
@Description Local Access Window Target interface ID
*//***************************************************************************/
typedef enum e_P2041LawTargetId
{
e_P2041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */
e_P2041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */
e_P2041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */
e_P2041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */
e_P2041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */
e_P2041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */
e_P2041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */
e_P2041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */
e_P2041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */
e_P2041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */
e_P2041_LAW_TARGET_NONE = 0xFF /**< None */
} e_P2041LawTargetId;
/***************************************************************
P2041 general routines
****************************************************************/
/**************************************************************************//**
@Group P2041_init_grp P2041 Initialization Unit
@Description P2041 initialization unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Part ID and revision number
*//***************************************************************************/
typedef enum e_P2041DeviceName
{
e_P2041_REV_INVALID = 0x00000000, /**< Invalid revision */
e_P2040_REV_1_0 = (int)0x82180010, /**< P2040 with security, revision 1.0 */
e_P2040_REV_1_0_NO_SEC = (int)0x82100010, /**< P2040 without security, revision 1.0 */
e_P2041_REV_1_0 = (int)0x82180110, /**< P2041 with security, revision 1.0 */
e_P2041_REV_1_0_NO_SEC = (int)0x82100110 /**< P2041 without security, revision 1.0 */
} e_P2041DeviceName;
/**************************************************************************//**
@Description Device Disable Register
*//***************************************************************************/
typedef enum e_P2041DeviceDisable
{
e_P2041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */
e_P2041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */
e_P2041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */
e_P2041_DEV_DISABLE_RMAN = 4, /**< RapidIO message manager disable */
e_P2041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */
e_P2041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */
e_P2041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */
e_P2041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */
e_P2041_DEV_DISABLE_DDR, /**< DDR controller disable */
e_P2041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */
e_P2041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */
e_P2041_DEV_DISABLE_LBC, /**< eLBC controller disable */
e_P2041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */
e_P2041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */
e_P2041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */
e_P2041_DEV_DISABLE_GPIO, /**< GPIO controller disable */
e_P2041_DEV_DISABLE_ESPI, /**< eSPI controller disable */
e_P2041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */
e_P2041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */
e_P2041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */
e_P2041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */
e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST = 32,
/**< Dummy entry signing end of DEVDISR1 register controllers */
e_P2041_DEV_DISABLE_PME = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST,
/**< Pattern match engine disable */
e_P2041_DEV_DISABLE_SEC, /**< Security disable */
e_P2041_DEV_DISABLE_QM_BM = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST + 4,
/**< Queue manager/buffer manager disable */
e_P2041_DEV_DISABLE_FM = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST + 6,
/**< Frame manager disable */
e_P2041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */
e_P2041_DEV_DISABLE_DTSEC_1,
/**< dTSEC controller 1 disable */
e_P2041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */
e_P2041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */
e_P2041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */
e_P2041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */
} e_P2041DeviceDisable;
/**************************************************************************//*
@Description structure representing P2041 devices configuration
*//***************************************************************************/
typedef struct t_P2041Devices
{
struct
{
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank,
one bit for lane, lane A is the first and so on, e.g.,
set 0xF000 for ABCD lanes */
e_EnetInterface ethIf;
uint8_t ratio;
bool divByTwo;
bool isTwoHalfSgmii;
} dtsecs[FM_MAX_NUM_OF_1G_MACS];
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane;
} tgec;
} fm;
} t_P2041Devices;
/**************************************************************************//**
@Function P2041_GetRevInfo
@Description Obtain revision information.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return Part ID and revision.
*//***************************************************************************/
e_P2041DeviceName P2041_GetRevInfo(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetE500Factor
@Description Obtain core's multiplication factors.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[in] coreIndex - Core index.
@Param[out] p_E500MulFactor - E500 to CCB multification factor.
@Param[out] p_E500DivFactor - E500 to CCB division factor.
*//***************************************************************************/
void P2041_GetE500Factor(uintptr_t gutilBase,
uint8_t coreIndex,
uint32_t *p_E500MulFactor,
uint32_t *p_E500DivFactor);
/**************************************************************************//**
@Function P2041_GetCcbFactor
@Description Obtain system multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return System multiplication factor.
*//***************************************************************************/
uint32_t P2041_GetCcbFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetDdrFactor
@Description Obtain DDR clock multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR clock multiplication factor.
*//***************************************************************************/
uint32_t P2041_GetDdrFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetDdrType
@Description Obtain DDR memory type.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR type.
*//***************************************************************************/
e_DdrType P2041_GetDdrType(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetFmFactor
@Description returns FM multiplication factors. (This value is returned using
two parameters to avoid using float parameter).
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[out] p_FmMulFactor - FM to CCB multification factor.
@Param[out] p_FmDivFactor - FM to CCB division factor.
*//***************************************************************************/
void P2041_GetFmFactor(uintptr_t gutilBase,
uint32_t *p_FmMulFactor,
uint32_t *p_FmDivFactor);
void P2041_CoreTimeBaseEnable(uintptr_t rcpmBase);
void P2041_CoreTimeBaseDisable(uintptr_t rcpmBase);
typedef enum e_SerdesProtocol
{
SRDS_PROTOCOL_NONE = 0,
SRDS_PROTOCOL_PCIE1,
SRDS_PROTOCOL_PCIE2,
SRDS_PROTOCOL_PCIE3,
SRDS_PROTOCOL_SRIO1,
SRDS_PROTOCOL_SRIO2,
SRDS_PROTOCOL_SGMII_FM,
SRDS_PROTOCOL_XAUI_FM,
SRDS_PROTOCOL_SATA1,
SRDS_PROTOCOL_SATA2,
SRDS_PROTOCOL_AURORA
} e_SerdesProtocol;
t_Error P2041_DeviceDisable(uintptr_t gutilBase, e_P2041DeviceDisable device, bool disable);
void P2041_GetDevicesConfiguration(uintptr_t gutilBase, t_P2041Devices *p_Devices);
t_Error P2041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable);
void P2041_SetDmaLiodn(uintptr_t gutilBase, uint8_t dmaId, uint16_t liodn);
uint32_t P2041_SerdesRcwGetProtocol(uintptr_t gutilBase);
bool P2041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device);
bool P2041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane);
/** @} */ /* end of P2041_init_grp group */
/** @} */ /* end of P2041_grp group */
/*****************************************************************************
INTEGRATION-SPECIFIC MODULE CODES
******************************************************************************/
#define MODULE_UNKNOWN 0x00000000
#define MODULE_MEM 0x00010000
#define MODULE_MM 0x00020000
#define MODULE_CORE 0x00030000
#define MODULE_P2041 0x00040000
#define MODULE_P2041_PLATFORM 0x00050000
#define MODULE_PM 0x00060000
#define MODULE_MMU 0x00070000
#define MODULE_PIC 0x00080000
#define MODULE_CPC 0x00090000
#define MODULE_DUART 0x000a0000
#define MODULE_SERDES 0x000b0000
#define MODULE_PIO 0x000c0000
#define MODULE_QM 0x000d0000
#define MODULE_BM 0x000e0000
#define MODULE_SEC 0x000f0000
#define MODULE_LAW 0x00100000
#define MODULE_LBC 0x00110000
#define MODULE_PAMU 0x00120000
#define MODULE_FM 0x00130000
#define MODULE_FM_MURAM 0x00140000
#define MODULE_FM_PCD 0x00150000
#define MODULE_FM_RTC 0x00160000
#define MODULE_FM_MAC 0x00170000
#define MODULE_FM_PORT 0x00180000
#define MODULE_DPA_PORT 0x00190000
#define MODULE_MII 0x001a0000
#define MODULE_I2C 0x001b0000
#define MODULE_DMA 0x001c0000
#define MODULE_DDR 0x001d0000
#define MODULE_ESPI 0x001e0000
/*****************************************************************************
PAMU INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define PAMU_NUM_OF_PARTITIONS 4
/*****************************************************************************
LAW INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define LAW_NUM_OF_WINDOWS 32
#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */
#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */
/*****************************************************************************
LBC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
/**************************************************************************//**
@Group lbc_exception_grp LBC Exception Unit
@Description LBC Exception unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Anchor lbc_exbm
@Collection LBC Errors Bit Mask
These errors are reported through the exceptions callback..
The values can be or'ed in any combination in the errors mask
parameter of the errors report structure.
These errors can also be passed as a bit-mask to
LBC_EnableErrorChecking() or LBC_DisableErrorChecking(),
for enabling or disabling error checking.
@{
*//***************************************************************************/
#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */
#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */
#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */
#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */
#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \
LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT)
/**< All possible errors */
/* @} */
/** @} */ /* end of lbc_exception_grp group */
#define LBC_INCORRECT_ERROR_REPORT_ERRATA
#define LBC_NUM_OF_BANKS 4
#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */
#define LBC_PARITY_SUPPORT
#define LBC_ADDRESS_HOLD_TIME_CTRL
#define LBC_HIGH_CLK_DIVIDERS
#define LBC_FCM_AVAILABLE
/*****************************************************************************
GPIO INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module;
Each port contains up to 32 I/O pins. */
#define GPIO_VALID_PIN_MASKS \
{ /* Port A */ 0xFFFFFFFF }
#define GPIO_VALID_INTR_MASKS \
{ /* Port A */ 0xFFFFFFFF }
/*****************************************************************************
SERDES INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define SRDS_MAX_LANES 10 /* Lanes C - H on bank 1, lanes A - D on bank 2 */
#define SRDS_MAX_BANK 2
/* Serdes lanes general information provided in the following form:
1) Lane index in Serdes Control Registers Map
2) Lane enable/disable bit number in RCW
3) Lane bank index */
#define SRDS_LANES \
{ \
{ 2, 154, 0 }, \
{ 3, 155, 0 }, \
{ 4, 156, 0 }, \
{ 5, 157, 0 }, \
{ 6, 158, 0 }, \
{ 7, 159, 0 }, \
{ 16, 162, 1 }, \
{ 17, 163, 1 }, \
{ 18, 164, 1 }, \
{ 19, 165, 1 } \
}
#define SRDS_PROTOCOL_OPTIONS \
/* Protocol Lane assignment */ \
{ \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x05 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x08 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x09 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x0A */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x0F */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x14 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x17 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x19 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1A */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x1C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_SGMII_FM, 0, 0} \
}
/*****************************************************************************
DDR INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DDR_NUM_OF_VALID_CS 4
/*****************************************************************************
DMA INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DMA_NUM_OF_CONTROLLERS 2
/*****************************************************************************
CPC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4
#define CPC_HARDWARE_FLUSH_ERRATA_CPC10
#endif /* __PART_INTEGRATION_EXT_H */

371
sys/contrib/ncsw/inc/integrations/P3041/dpaa_integration_ext.h
View File

@ -1,371 +0,0 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File dpaa_integration_ext.h
@Description P3041 FM external definitions and structures.
*//***************************************************************************/
#ifndef __DPAA_INTEGRATION_EXT_H
#define __DPAA_INTEGRATION_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Description DPAA SW Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_SWPORTAL0 = 0,
e_DPAA_SWPORTAL1,
e_DPAA_SWPORTAL2,
e_DPAA_SWPORTAL3,
e_DPAA_SWPORTAL4,
e_DPAA_SWPORTAL5,
e_DPAA_SWPORTAL6,
e_DPAA_SWPORTAL7,
e_DPAA_SWPORTAL8,
e_DPAA_SWPORTAL9,
e_DPAA_SWPORTAL_DUMMY_LAST
} e_DpaaSwPortal;
/**************************************************************************//**
@Description DPAA Direct Connect Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_DCPORTAL0 = 0,
e_DPAA_DCPORTAL1,
e_DPAA_DCPORTAL2,
e_DPAA_DCPORTAL3,
e_DPAA_DCPORTAL4,
e_DPAA_DCPORTAL_DUMMY_LAST
} e_DpaaDcPortal;
#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST
#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST
/*****************************************************************************
QMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */
#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */
#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */
#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE)
/**< FQIDs range - 24 bits */
/**************************************************************************//**
@Description Work Queue Channel assignments in QMan.
*//***************************************************************************/
typedef enum
{
e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */
e_QM_FQ_CHANNEL_SWPORTAL1,
e_QM_FQ_CHANNEL_SWPORTAL2,
e_QM_FQ_CHANNEL_SWPORTAL3,
e_QM_FQ_CHANNEL_SWPORTAL4,
e_QM_FQ_CHANNEL_SWPORTAL5,
e_QM_FQ_CHANNEL_SWPORTAL6,
e_QM_FQ_CHANNEL_SWPORTAL7,
e_QM_FQ_CHANNEL_SWPORTAL8,
e_QM_FQ_CHANNEL_SWPORTAL9,
e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */
e_QM_FQ_CHANNEL_POOL2,
e_QM_FQ_CHANNEL_POOL3,
e_QM_FQ_CHANNEL_POOL4,
e_QM_FQ_CHANNEL_POOL5,
e_QM_FQ_CHANNEL_POOL6,
e_QM_FQ_CHANNEL_POOL7,
e_QM_FQ_CHANNEL_POOL8,
e_QM_FQ_CHANNEL_POOL9,
e_QM_FQ_CHANNEL_POOL10,
e_QM_FQ_CHANNEL_POOL11,
e_QM_FQ_CHANNEL_POOL12,
e_QM_FQ_CHANNEL_POOL13,
e_QM_FQ_CHANNEL_POOL14,
e_QM_FQ_CHANNEL_POOL15,
e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0:
connected to FMan 0; assigned in incrementing order to
each sub-portal (SP) in the portal */
e_QM_FQ_CHANNEL_FMAN0_SP1,
e_QM_FQ_CHANNEL_FMAN0_SP2,
e_QM_FQ_CHANNEL_FMAN0_SP3,
e_QM_FQ_CHANNEL_FMAN0_SP4,
e_QM_FQ_CHANNEL_FMAN0_SP5,
e_QM_FQ_CHANNEL_FMAN0_SP6,
e_QM_FQ_CHANNEL_FMAN0_SP7,
e_QM_FQ_CHANNEL_FMAN0_SP8,
e_QM_FQ_CHANNEL_FMAN0_SP9,
e_QM_FQ_CHANNEL_FMAN0_SP10,
e_QM_FQ_CHANNEL_FMAN0_SP11,
e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */
e_QM_FQ_CHANNEL_RMAN_SP3,
e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2:
connected to SEC 4.x */
e_QM_FQ_CHANNEL_PME = 0xA0 /**< Dedicated channel serviced by Direct Connect Portal 3:
connected to PME */
} e_QmFQChannel;
/*****************************************************************************
BMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */
/*****************************************************************************
FM INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define INTG_MAX_NUM_OF_FM 1
/* Ports defines */
#define FM_MAX_NUM_OF_1G_MACS 5
#define FM_MAX_NUM_OF_10G_MACS 1
#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS)
#define FM_MAX_NUM_OF_OH_PORTS 7
#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS)
#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS)
#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */
#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */
#define FM_MAX_NUM_OF_SUB_PORTALS 12
#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0
/* RAMs defines */
#define FM_MURAM_SIZE (160 * KILOBYTE)
#define FM_IRAM_SIZE ( 64 * KILOBYTE)
/* PCD defines */
#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */
#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */
#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */
/* RTC defines */
#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */
#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */
#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */
/* QMI defines */
#define QMI_MAX_NUM_OF_TNUMS 64
#define MAX_QMI_DEQ_SUBPORTAL 12
#define QMI_DEF_TNUMS_THRESH 48
/* FPM defines */
#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4
/* DMA defines */
#define DMA_THRESH_MAX_COMMQ 31
#define DMA_THRESH_MAX_BUF 127
/* BMI defines */
#define BMI_MAX_NUM_OF_TASKS 128
#define BMI_MAX_NUM_OF_DMAS 32
#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE)
#define PORT_MAX_WEIGHT 16
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmEventModules
{
e_FM_MOD_PRS, /**< Parser event */
e_FM_MOD_KG, /**< Keygen event */
e_FM_MOD_PLCR, /**< Policer event */
e_FM_MOD_10G_MAC, /**< 10G MAC error event */
e_FM_MOD_1G_MAC, /**< 1G MAC error event */
e_FM_MOD_TMR, /**< Timer event */
e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */
e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */
e_FM_MOD_DUMMY_LAST
} e_FmEventModules;
/**************************************************************************//**
@Description Enum for interrupts types
*//***************************************************************************/
typedef enum e_FmIntrType
{
e_FM_INTR_TYPE_ERR,
e_FM_INTR_TYPE_NORMAL
} e_FmIntrType;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmInterModuleEvent
{
e_FM_EV_PRS, /**< Parser event */
e_FM_EV_ERR_PRS, /**< Parser error event */
e_FM_EV_KG, /**< Keygen event */
e_FM_EV_ERR_KG, /**< Keygen error event */
e_FM_EV_PLCR, /**< Policer event */
e_FM_EV_ERR_PLCR, /**< Policer error event */
e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */
e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */
e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */
e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */
e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */
e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */
e_FM_EV_TMR, /**< Timer event */
e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */
e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */
e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */
e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */
e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */
e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */
e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */
e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */
e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */
e_FM_EV_DUMMY_LAST
} e_FmInterModuleEvent;
#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MOD_PRS: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
break; \
case e_FM_MOD_KG: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_PLCR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
break; \
case e_FM_MOD_10G_MAC: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_1G_MAC: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \
} \
break; \
case e_FM_MOD_TMR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
break; \
case e_FM_MOD_1G_MAC_TMR: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \
} \
break; \
case e_FM_MOD_FMAN_CTRL: \
if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \
else switch(id){ \
case(0): event = e_FM_EV_FMAN_CTRL_0; break; \
case(1): event = e_FM_EV_FMAN_CTRL_1; break; \
case(2): event = e_FM_EV_FMAN_CTRL_2; break; \
case(3): event = e_FM_EV_FMAN_CTRL_3; break; \
} \
break; \
default: event = e_FM_EV_DUMMY_LAST; \
break;}
#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE
/* P3041 unique features */
#define FM_QMI_DEQ_OPTIONS_SUPPORT
#define FM_NO_DISPATCH_RAM_ECC
#define FM_FIFO_ALLOCATION_OLD_ALG
#define FM_NO_WATCHDOG
#define FM_NO_TNUM_AGING
#define FM_NO_TGEC_LOOPBACK
#define FM_KG_NO_BYPASS_FQID_GEN
#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN
#define FM_NO_BACKUP_POOLS
#define FM_NO_OP_OBSERVED_POOLS
#define FM_NO_ADVANCED_RATE_LIMITER
#define FM_NO_OP_OBSERVED_CGS
/* FM erratas */
#define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */
#define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007
#define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008
#define FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_GRS_ERRATA_DTSEC_A002
#define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003
#define FM_GTS_ERRATA_DTSEC_A004
#define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */
#define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */
#define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3
#define FM_TX_LOCKUP_ERRATA_DTSEC6
#define FM_IM_TX_SYNC_SKIP_TNUM_ERRATA_FMAN_A001 /* Implemented by ucode */
#define FM_HC_DEF_FQID_ONLY_ERRATA_FMAN_A003 /* Implemented by ucode */
#define FM_IM_TX_SHARED_TNUM_ERRATA_FMAN4 /* Implemented by ucode */
#define FM_IM_GS_DEADLOCK_ERRATA_FMAN5 /* Implemented by ucode */
#define FM_IM_DEQ_PIPELINE_DEPTH_ERRATA_FMAN10 /* Implemented by ucode */
#define FM_CC_GEN6_MISSMATCH_ERRATA_FMAN12 /* Implemented by ucode */
#define FM_CC_CHANGE_SHARED_TNUM_ERRATA_FMAN13 /* Implemented by ucode */
#define FM_IM_LARGE_MRBLR_ERRATA_FMAN15 /* Implemented by ucode */
#define FM_BMI_TO_RISC_ENQ_ERRATA_FMANc /* No implementation, Out of LLD scope */
#define FM_INVALID_SWPRS_DATA_ERRATA_FMANd
/* #define FM_PRS_MPLS_SSA_ERRATA_FMANj */ /* No implementation, No patch yet */
/* #define FM_PRS_INITIAL_PLANID_ERRATA_FMANk */ /* No implementation, No patch yet */
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001
#endif /* __DPAA_INTEGRATION_EXT_H */

995
sys/contrib/ncsw/inc/integrations/P3041/part_integration_ext.h
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@ -1,995 +0,0 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File part_integration_ext.h
@Description P3041 external definitions and structures.
*//***************************************************************************/
#ifndef __PART_INTEGRATION_EXT_H
#define __PART_INTEGRATION_EXT_H
#include "std_ext.h"
#include "ddr_std_ext.h"
#include "enet_ext.h"
#include "dpaa_integration_ext.h"
/**************************************************************************//**
@Group P3041_chip_id P3041 Application Programming Interface
@Description P3041 Chip functions,definitions and enums.
@{
*//***************************************************************************/
#define CORE_E500MC
#define INTG_MAX_NUM_OF_CORES 4
/**************************************************************************//**
@Description Module types.
*//***************************************************************************/
typedef enum e_ModuleId
{
e_MODULE_ID_DUART_1 = 0,
e_MODULE_ID_DUART_2,
e_MODULE_ID_DUART_3,
e_MODULE_ID_DUART_4,
e_MODULE_ID_LAW,
e_MODULE_ID_LBC,
e_MODULE_ID_PAMU,
e_MODULE_ID_QM, /**< Queue manager module */
e_MODULE_ID_BM, /**< Buffer manager module */
e_MODULE_ID_QM_CE_PORTAL_0,
e_MODULE_ID_QM_CI_PORTAL_0,
e_MODULE_ID_QM_CE_PORTAL_1,
e_MODULE_ID_QM_CI_PORTAL_1,
e_MODULE_ID_QM_CE_PORTAL_2,
e_MODULE_ID_QM_CI_PORTAL_2,
e_MODULE_ID_QM_CE_PORTAL_3,
e_MODULE_ID_QM_CI_PORTAL_3,
e_MODULE_ID_QM_CE_PORTAL_4,
e_MODULE_ID_QM_CI_PORTAL_4,
e_MODULE_ID_QM_CE_PORTAL_5,
e_MODULE_ID_QM_CI_PORTAL_5,
e_MODULE_ID_QM_CE_PORTAL_6,
e_MODULE_ID_QM_CI_PORTAL_6,
e_MODULE_ID_QM_CE_PORTAL_7,
e_MODULE_ID_QM_CI_PORTAL_7,
e_MODULE_ID_QM_CE_PORTAL_8,
e_MODULE_ID_QM_CI_PORTAL_8,
e_MODULE_ID_QM_CE_PORTAL_9,
e_MODULE_ID_QM_CI_PORTAL_9,
e_MODULE_ID_BM_CE_PORTAL_0,
e_MODULE_ID_BM_CI_PORTAL_0,
e_MODULE_ID_BM_CE_PORTAL_1,
e_MODULE_ID_BM_CI_PORTAL_1,
e_MODULE_ID_BM_CE_PORTAL_2,
e_MODULE_ID_BM_CI_PORTAL_2,
e_MODULE_ID_BM_CE_PORTAL_3,
e_MODULE_ID_BM_CI_PORTAL_3,
e_MODULE_ID_BM_CE_PORTAL_4,
e_MODULE_ID_BM_CI_PORTAL_4,
e_MODULE_ID_BM_CE_PORTAL_5,
e_MODULE_ID_BM_CI_PORTAL_5,
e_MODULE_ID_BM_CE_PORTAL_6,
e_MODULE_ID_BM_CI_PORTAL_6,
e_MODULE_ID_BM_CE_PORTAL_7,
e_MODULE_ID_BM_CI_PORTAL_7,
e_MODULE_ID_BM_CE_PORTAL_8,
e_MODULE_ID_BM_CI_PORTAL_8,
e_MODULE_ID_BM_CE_PORTAL_9,
e_MODULE_ID_BM_CI_PORTAL_9,
e_MODULE_ID_FM, /**< Frame manager module */
e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */
e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */
e_MODULE_ID_FM_BMI, /**< FM BMI block */
e_MODULE_ID_FM_QMI, /**< FM QMI block */
e_MODULE_ID_FM_PARSER, /**< FM parser block */
e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */
e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */
e_MODULE_ID_FM_PLCR, /**< FM Policer */
e_MODULE_ID_FM_KG, /**< FM Keygen */
e_MODULE_ID_FM_DMA, /**< FM DMA */
e_MODULE_ID_FM_FPM, /**< FM FPM */
e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */
e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/
e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/
e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/
e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/
e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/
e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */
e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */
e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */
e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */
e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */
e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */
e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */
e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */
e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */
e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */
e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */
e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */
e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */
e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */
e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */
e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */
e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */
e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */
e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */
e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */
e_MODULE_ID_PIC, /**< PIC */
e_MODULE_ID_GPIO, /**< GPIO */
e_MODULE_ID_SERDES, /**< SERDES */
e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */
e_MODULE_ID_DUMMY_LAST
} e_ModuleId;
#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST
/* Offsets relative to CCSR base */
#define P3041_OFFSET_LAW 0x00000c00
#define P3041_OFFSET_DDR 0x00008000
#define P3041_OFFSET_CPC 0x00010000
#define P3041_OFFSET_CCM 0x00018000
#define P3041_OFFSET_PAMU 0x00020000
#define P3041_OFFSET_PIC 0x00040000
#define P3041_OFFSET_GUTIL 0x000e0000
#define P3041_OFFSET_RCPM 0x000e2000
#define P3041_OFFSET_SERDES 0x000ea000
#define P3041_OFFSET_DMA1 0x00100100
#define P3041_OFFSET_DMA2 0x00101100
#define P3041_OFFSET_ESPI 0x00110000
#define P3041_OFFSET_ESDHC 0x00114000
#define P3041_OFFSET_I2C1 0x00118000
#define P3041_OFFSET_I2C2 0x00118100
#define P3041_OFFSET_I2C3 0x00119000
#define P3041_OFFSET_I2C4 0x00119100
#define P3041_OFFSET_DUART1 0x0011c500
#define P3041_OFFSET_DUART2 0x0011c600
#define P3041_OFFSET_DUART3 0x0011d500
#define P3041_OFFSET_DUART4 0x0011d600
#define P3041_OFFSET_LBC 0x00124000
#define P3041_OFFSET_GPIO 0x00130000
#define P3041_OFFSET_PCIE1 0x00200000
#define P3041_OFFSET_PCIE2 0x00201000
#define P3041_OFFSET_PCIE3 0x00202000
#define P3041_OFFSET_PCIE4 0x00203000
#define P3041_OFFSET_USB1 0x00210000
#define P3041_OFFSET_USB2 0x00211000
#define P3041_OFFSET_USB_PHY 0x00214000
#define P3041_OFFSET_SATA1 0x00220000
#define P3041_OFFSET_SATA2 0x00221000
#define P3041_OFFSET_SEC_GEN 0x00300000
#define P3041_OFFSET_SEC_JQ0 0x00301000
#define P3041_OFFSET_SEC_JQ1 0x00302000
#define P3041_OFFSET_SEC_JQ2 0x00303000
#define P3041_OFFSET_SEC_JQ3 0x00304000
#define P3041_OFFSET_SEC_RESERVED 0x00305000
#define P3041_OFFSET_SEC_RTIC 0x00306000
#define P3041_OFFSET_SEC_QI 0x00307000
#define P3041_OFFSET_SEC_DECO0_CCB0 0x00308000
#define P3041_OFFSET_SEC_DECO1_CCB1 0x00309000
#define P3041_OFFSET_PME 0x00316000
#define P3041_OFFSET_QM 0x00318000
#define P3041_OFFSET_BM 0x0031a000
#define P3041_OFFSET_FM 0x00400000
#define P3041_OFFSET_FM_MURAM P3041_OFFSET_FM
#define P3041_OFFSET_FM_BMI (P3041_OFFSET_FM + 0x00080000)
#define P3041_OFFSET_FM_QMI (P3041_OFFSET_FM + 0x00080400)
#define P3041_OFFSET_FM_PARSER (P3041_OFFSET_FM + 0x00080800)
#define P3041_OFFSET_FM_PORT_HO1 (P3041_OFFSET_FM + 0x00081000) /* host command/offline parser */
#define P3041_OFFSET_FM_PORT_HO2 (P3041_OFFSET_FM + 0x00082000)
#define P3041_OFFSET_FM_PORT_HO3 (P3041_OFFSET_FM + 0x00083000)
#define P3041_OFFSET_FM_PORT_HO4 (P3041_OFFSET_FM + 0x00084000)
#define P3041_OFFSET_FM_PORT_HO5 (P3041_OFFSET_FM + 0x00085000)
#define P3041_OFFSET_FM_PORT_HO6 (P3041_OFFSET_FM + 0x00086000)
#define P3041_OFFSET_FM_PORT_HO7 (P3041_OFFSET_FM + 0x00087000)
#define P3041_OFFSET_FM_PORT_1GRX1 (P3041_OFFSET_FM + 0x00088000)
#define P3041_OFFSET_FM_PORT_1GRX2 (P3041_OFFSET_FM + 0x00089000)
#define P3041_OFFSET_FM_PORT_1GRX3 (P3041_OFFSET_FM + 0x0008a000)
#define P3041_OFFSET_FM_PORT_1GRX4 (P3041_OFFSET_FM + 0x0008b000)
#define P3041_OFFSET_FM_PORT_1GRX5 (P3041_OFFSET_FM + 0x0008c000)
#define P3041_OFFSET_FM_PORT_10GRX (P3041_OFFSET_FM + 0x00090000)
#define P3041_OFFSET_FM_PORT_1GTX1 (P3041_OFFSET_FM + 0x000a8000)
#define P3041_OFFSET_FM_PORT_1GTX2 (P3041_OFFSET_FM + 0x000a9000)
#define P3041_OFFSET_FM_PORT_1GTX3 (P3041_OFFSET_FM + 0x000aa000)
#define P3041_OFFSET_FM_PORT_1GTX4 (P3041_OFFSET_FM + 0x000ab000)
#define P3041_OFFSET_FM_PORT_1GTX5 (P3041_OFFSET_FM + 0x000ac000)
#define P3041_OFFSET_FM_PORT_10GTX (P3041_OFFSET_FM + 0x000b0000)
#define P3041_OFFSET_FM_PLCR (P3041_OFFSET_FM + 0x000c0000)
#define P3041_OFFSET_FM_KG (P3041_OFFSET_FM + 0x000c1000)
#define P3041_OFFSET_FM_DMA (P3041_OFFSET_FM + 0x000c2000)
#define P3041_OFFSET_FM_FPM (P3041_OFFSET_FM + 0x000c3000)
#define P3041_OFFSET_FM_IRAM (P3041_OFFSET_FM + 0x000c4000)
#define P3041_OFFSET_FM_PARSER_IRAM (P3041_OFFSET_FM + 0x000c7000)
#define P3041_OFFSET_FM_1GMAC1 (P3041_OFFSET_FM + 0x000e0000)
#define P3041_OFFSET_FM_1GMDIO (P3041_OFFSET_FM + 0x000e1000 + 0x120)
#define P3041_OFFSET_FM_1GMAC2 (P3041_OFFSET_FM + 0x000e2000)
#define P3041_OFFSET_FM_1GMAC3 (P3041_OFFSET_FM + 0x000e4000)
#define P3041_OFFSET_FM_1GMAC4 (P3041_OFFSET_FM + 0x000e6000)
#define P3041_OFFSET_FM_1GMAC5 (P3041_OFFSET_FM + 0x000e8000)
#define P3041_OFFSET_FM_10GMAC (P3041_OFFSET_FM + 0x000f0000)
#define P3041_OFFSET_FM_10GMDIO (P3041_OFFSET_FM + 0x000f1000 + 0x030)
#define P3041_OFFSET_FM_RTC (P3041_OFFSET_FM + 0x000fe000)
/* Offsets relative to QM or BM portals base */
#define P3041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */
#define P3041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */
#define P3041_CE_PORTAL_SIZE 0x4000
#define P3041_CI_PORTAL_SIZE 0x1000
#define P3041_OFFSET_PORTALS_CE(portal) \
(P3041_OFFSET_PORTALS_CE_AREA + P3041_CE_PORTAL_SIZE * (portal))
#define P3041_OFFSET_PORTALS_CI(portal) \
(P3041_OFFSET_PORTALS_CI_AREA + P3041_CI_PORTAL_SIZE * (portal))
/**************************************************************************//**
@Description Transaction source ID (for memory controllers error reporting).
*//***************************************************************************/
typedef enum e_TransSrc
{
e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */
e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */
e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */
e_TRANS_SRC_PCIE_4 = 0x3, /**< PCI Express 4 */
e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */
e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */
e_TRANS_SRC_BMAN = 0x18, /**< BMan */
e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */
e_TRANS_SRC_PME = 0x20, /**< PME */
e_TRANS_SRC_SEC = 0x21, /**< Security engine */
e_TRANS_SRC_QMAN = 0x3C, /**< QMan */
e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */
e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */
e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */
e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */
e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */
e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */
e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */
e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */
e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */
e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */
e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */
e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */
e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */
e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */
e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */
e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */
e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */
e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */
e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */
e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */
e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */
e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */
e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */
e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */
e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */
e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */
e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */
e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */
e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */
e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */
e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */
} e_TransSrc;
/**************************************************************************//**
@Description Local Access Window Target interface ID
*//***************************************************************************/
typedef enum e_P3041LawTargetId
{
e_P3041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */
e_P3041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */
e_P3041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */
e_P3041_LAW_TARGET_PCIE_4 = 0x3, /**< PCI Express 4 */
e_P3041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */
e_P3041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */
e_P3041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */
e_P3041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */
e_P3041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */
e_P3041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */
e_P3041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */
e_P3041_LAW_TARGET_NONE = 0xFF /**< None */
} e_P3041LawTargetId;
/***************************************************************
P3041 general routines
****************************************************************/
/**************************************************************************//**
@Group P3041_init_grp P3041 Initialization Unit
@Description P3041 initialization unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Part ID and revision number
*//***************************************************************************/
typedef enum e_P3041DeviceName
{
e_P3041_REV_INVALID = 0x00000000, /**< Invalid revision */
e_P3041_REV_1_0 = (int)0x82190310, /**< P3041 with security, revision 1.0 */
e_P3041_REV_1_0_NO_SEC = (int)0x82110310 /**< P3041 without security, revision 1.0 */
} e_P3041DeviceName;
/**************************************************************************//**
@Description Device Disable Register
*//***************************************************************************/
typedef enum e_P3041DeviceDisable
{
e_P3041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */
e_P3041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */
e_P3041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */
e_P3041_DEV_DISABLE_PCIE_4, /**< PCI Express controller 4 disable */
e_P3041_DEV_DISABLE_RMAN, /**< RapidIO message manager disable */
e_P3041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */
e_P3041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */
e_P3041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */
e_P3041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */
e_P3041_DEV_DISABLE_DDR, /**< DDR controller disable */
e_P3041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */
e_P3041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */
e_P3041_DEV_DISABLE_LBC, /**< eLBC controller disable */
e_P3041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */
e_P3041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */
e_P3041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */
e_P3041_DEV_DISABLE_GPIO, /**< GPIO controller disable */
e_P3041_DEV_DISABLE_ESPI, /**< eSPI controller disable */
e_P3041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */
e_P3041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */
e_P3041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */
e_P3041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */
e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST = 32,
/**< Dummy entry signing end of DEVDISR1 register controllers */
e_P3041_DEV_DISABLE_PME = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST,
/**< Pattern match engine disable */
e_P3041_DEV_DISABLE_SEC, /**< Security disable */
e_P3041_DEV_DISABLE_QM_BM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 4,
/**< Queue manager/buffer manager disable */
e_P3041_DEV_DISABLE_FM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 6,
/**< Frame manager disable */
e_P3041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */
e_P3041_DEV_DISABLE_DTSEC_1, /**< dTSEC controller 1 disable */
e_P3041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */
e_P3041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */
e_P3041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */
e_P3041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */
} e_P3041DeviceDisable;
/**************************************************************************//*
@Description structure representing P3041 devices configuration
*//***************************************************************************/
typedef struct t_P3041Devices
{
struct
{
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank,
one bit for lane, lane A is the first and so on, e.g.,
set 0xF000 for ABCD lanes */
e_EnetInterface ethIf;
uint8_t ratio;
bool divByTwo;
bool isTwoHalfSgmii;
} dtsecs[FM_MAX_NUM_OF_1G_MACS];
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane;
} tgec;
} fm;
} t_P3041Devices;
/**************************************************************************//**
@Function P3041_GetRevInfo
@Description Obtain revision information.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return Part ID and revision.
*//***************************************************************************/
e_P3041DeviceName P3041_GetRevInfo(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetE500Factor
@Description Obtain core's multiplication factors.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[in] coreIndex - Core index.
@Param[out] p_E500MulFactor - E500 to CCB multification factor.
@Param[out] p_E500DivFactor - E500 to CCB division factor.
*//***************************************************************************/
void P3041_GetE500Factor(uintptr_t gutilBase,
uint8_t coreIndex,
uint32_t *p_E500MulFactor,
uint32_t *p_E500DivFactor);
/**************************************************************************//**
@Function P3041_GetCcbFactor
@Description Obtain system multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return System multiplication factor.
*//***************************************************************************/
uint32_t P3041_GetCcbFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetDdrFactor
@Description Obtain DDR clock multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR clock multiplication factor.
*//***************************************************************************/
uint32_t P3041_GetDdrFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetDdrType
@Description Obtain DDR memory type.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR type.
*//***************************************************************************/
e_DdrType P3041_GetDdrType(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetFmFactor
@Description returns FM multiplication factors. (This value is returned using
two parameters to avoid using float parameter).
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[out] p_FmMulFactor - FM to CCB multification factor.
@Param[out] p_FmDivFactor - FM to CCB division factor.
*//***************************************************************************/
void P3041_GetFmFactor(uintptr_t gutilBase,
uint32_t *p_FmMulFactor,
uint32_t *p_FmDivFactor);
void P3041_CoreTimeBaseEnable(uintptr_t rcpmBase);
void P3041_CoreTimeBaseDisable(uintptr_t rcpmBase);
typedef enum e_SerdesProtocol
{
SRDS_PROTOCOL_NONE = 0,
SRDS_PROTOCOL_PCIE1,
SRDS_PROTOCOL_PCIE2,
SRDS_PROTOCOL_PCIE3,
SRDS_PROTOCOL_PCIE4,
SRDS_PROTOCOL_SRIO1,
SRDS_PROTOCOL_SRIO2,
SRDS_PROTOCOL_SGMII_FM,
SRDS_PROTOCOL_XAUI_FM,
SRDS_PROTOCOL_SATA1,
SRDS_PROTOCOL_SATA2,
SRDS_PROTOCOL_AURORA
} e_SerdesProtocol;
t_Error P3041_DeviceDisable(uintptr_t gutilBase, e_P3041DeviceDisable device, bool disable);
void P3041_GetDevicesConfiguration(uintptr_t gutilBase, t_P3041Devices *p_Devices);
t_Error P3041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable);
uint32_t P3041_SerdesRcwGetProtocol(uintptr_t gutilBase);
bool P3041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device);
bool P3041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane);
/** @} */ /* end of P3041_init_grp group */
/** @} */ /* end of P3041_grp group */
/*****************************************************************************
INTEGRATION-SPECIFIC MODULE CODES
******************************************************************************/
#define MODULE_UNKNOWN 0x00000000
#define MODULE_MEM 0x00010000
#define MODULE_MM 0x00020000
#define MODULE_CORE 0x00030000
#define MODULE_P3041 0x00040000
#define MODULE_P3041_PLATFORM 0x00050000
#define MODULE_PM 0x00060000
#define MODULE_MMU 0x00070000
#define MODULE_PIC 0x00080000
#define MODULE_CPC 0x00090000
#define MODULE_DUART 0x000a0000
#define MODULE_SERDES 0x000b0000
#define MODULE_PIO 0x000c0000
#define MODULE_QM 0x000d0000
#define MODULE_BM 0x000e0000
#define MODULE_SEC 0x000f0000
#define MODULE_LAW 0x00100000
#define MODULE_LBC 0x00110000
#define MODULE_PAMU 0x00120000
#define MODULE_FM 0x00130000
#define MODULE_FM_MURAM 0x00140000
#define MODULE_FM_PCD 0x00150000
#define MODULE_FM_RTC 0x00160000
#define MODULE_FM_MAC 0x00170000
#define MODULE_FM_PORT 0x00180000
#define MODULE_DPA 0x00190000
#define MODULE_MII 0x001a0000
#define MODULE_I2C 0x001b0000
#define MODULE_DMA 0x001c0000
#define MODULE_DDR 0x001d0000
#define MODULE_ESPI 0x001e0000
/*****************************************************************************
PAMU INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define PAMU_NUM_OF_PARTITIONS 4
/*****************************************************************************
LAW INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define LAW_NUM_OF_WINDOWS 32
#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */
#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */
/*****************************************************************************
LBC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
/**************************************************************************//**
@Group lbc_exception_grp LBC Exception Unit
@Description LBC Exception unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Anchor lbc_exbm
@Collection LBC Errors Bit Mask
These errors are reported through the exceptions callback..
The values can be or'ed in any combination in the errors mask
parameter of the errors report structure.
These errors can also be passed as a bit-mask to
LBC_EnableErrorChecking() or LBC_DisableErrorChecking(),
for enabling or disabling error checking.
@{
*//***************************************************************************/
#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */
#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */
#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */
#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */
#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \
LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT)
/**< All possible errors */
/* @} */
/** @} */ /* end of lbc_exception_grp group */
#define LBC_INCORRECT_ERROR_REPORT_ERRATA
#define LBC_NUM_OF_BANKS 8
#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */
#define LBC_PARITY_SUPPORT
#define LBC_HIGH_CLK_DIVIDERS
#define LBC_FCM_AVAILABLE
/*****************************************************************************
GPIO INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module;
Each port contains up to 32 I/O pins. */
#define GPIO_VALID_PIN_MASKS \
{ /* Port A */ 0xFFFFFFFF }
#define GPIO_VALID_INTR_MASKS \
{ /* Port A */ 0xFFFFFFFF }
/*****************************************************************************
SERDES INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define SRDS_MAX_LANES 18
#define SRDS_MAX_BANK 3
/* Serdes lanes general information provided in the following form:
1) Lane index in Serdes Control Registers Map
2) Lane enable/disable bit number in RCW
3) Lane bank index */
#define SRDS_LANES \
{ \
{ 0, 152, 0 }, \
{ 1, 153, 0 }, \
{ 2, 154, 0 }, \
{ 3, 155, 0 }, \
{ 4, 156, 0 }, \
{ 5, 157, 0 }, \
{ 6, 158, 0 }, \
{ 7, 159, 0 }, \
{ 8, 160, 0 }, \
{ 9, 161, 0 }, \
{ 16, 162, 1 }, \
{ 17, 163, 1 }, \
{ 18, 164, 1 }, \
{ 19, 165, 1 }, \
{ 20, 166, 2 }, \
{ 21, 167, 2 }, \
{ 22, 168, 2 }, \
{ 23, 169, 2 } \
}
#define SRDS_PROTOCOL_ALL_OPTIONS
/* Serdes lanes assignment and multiplexing.
Each option is selected by SRDS_PRTCL bits of RCW. */
#define SRDS_PROTOCOL_OPTIONS \
/* Protocol Lane assignment */ \
{ \
/* 0x00 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x01 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x03 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x04 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x05 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x06 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x07 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x08 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x09 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x0A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x0B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x0C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x0D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x0E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x0F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x10 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x11 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x12 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x13 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x14 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x15 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1}, \
/* 0x17 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x18 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x19 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x1A */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x1B */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1C */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x1D */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x20 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x21 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x22 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x23 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x24 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x25 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x26 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x27 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x28 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x29 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x2A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x2B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x2C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x2D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x2E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x2F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x30 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x31 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x32 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x33 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x34 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x35 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x36 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x37 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2} \
}
/*****************************************************************************
DDR INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DDR_NUM_OF_VALID_CS 4
/*****************************************************************************
DMA INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DMA_NUM_OF_CONTROLLERS 2
/*****************************************************************************
CPC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4
#define CPC_HARDWARE_FLUSH_ERRATA_CPC10
#endif /* __PART_INTEGRATION_EXT_H */

1004
sys/contrib/ncsw/inc/integrations/P5020/part_integration_ext.h
View File

File diff suppressed because it is too large Load Diff

18
sys/contrib/ncsw/inc/integrations/P5020/dpaa_integration_ext.h → sys/contrib/ncsw/inc/integrations/dpaa_integration_ext.h
View File

@ -331,21 +331,19 @@ typedef enum e_FmInterModuleEvent
#define FM_NO_ADVANCED_RATE_LIMITER
#define FM_NO_OP_OBSERVED_CGS
/* FM erratas */
/* FM erratas (P5020, P3041) */
#define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */
#define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007
#define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008
#define FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_GRS_ERRATA_DTSEC_A002
#define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003
#define FM_GTS_ERRATA_DTSEC_A004
#define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */
#define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */
#define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3
#define FM_TX_LOCKUP_ERRATA_DTSEC6
@ -362,13 +360,19 @@ typedef enum e_FmInterModuleEvent
//#define FM_PRS_MPLS_SSA_ERRATA_FMANj /* No implementation, No patch yet */
//#define FM_PRS_INITIAL_PLANID_ERRATA_FMANk /* No implementation, No patch yet */
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001
/* P2041 */
#define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010
/* Common to all */
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#endif /* __DPAA_INTEGRATION_EXT_H */

44
sys/contrib/ncsw/inc/integrations/part_ext.h
View File

@ -41,32 +41,24 @@
#define __PART_EXT_H
#include "std_ext.h"
#include "part_integration_ext.h"
#include "enet_ext.h"
#include "dpaa_integration_ext.h"
#define CORE_E500MC
#if !(defined(MPC8306) || \
defined(MPC8309) || \
defined(MPC834x) || \
defined(MPC836x) || \
defined(MPC832x) || \
defined(MPC837x) || \
defined(MPC8568) || \
defined(MPC8569) || \
defined(P1020) || \
defined(P1021) || \
defined(P1022) || \
defined(P1023) || \
defined(P2020) || \
defined(P2040) || \
defined(P2041) || \
defined(P3041) || \
defined(P4080) || \
defined(SC4080) || \
defined(P5020) || \
defined(MSC814x))
#error "unable to proceed without chip-definition"
#endif /* !(defined(MPC834x) || ... */
/*****************************************************************************
INTEGRATION-SPECIFIC MODULE CODES
******************************************************************************/
#define MODULE_MEM 0x00010000
#define MODULE_MM 0x00020000
#define MODULE_QM 0x000d0000
#define MODULE_BM 0x000e0000
#define MODULE_FM 0x00130000
#define MODULE_FM_MURAM 0x00140000
#define MODULE_FM_PCD 0x00150000
#define MODULE_FM_RTC 0x00160000
#define MODULE_FM_MAC 0x00170000
#define MODULE_FM_PORT 0x00180000
/**************************************************************************//*
@Description Part data structure - must be contained in any integration
@ -74,10 +66,6 @@
*//***************************************************************************/
typedef struct t_Part
{
uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId);
/**< Returns the address of the module's memory map base. */
e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress);
/**< Returns the module's ID according to its memory map base. */
} t_Part;

62
sys/contrib/ncsw/integrations/P2041/module_strings.c
View File

@ -1,62 +0,0 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Module names for debug messages */
const char *moduleStrings[] =
{
"???" /* MODULE_UNKNOWN */
,"MEM" /* MODULE_ */
,"MM" /* MODULE_MM */
,"CORE" /* MODULE_CORE */
,"P2041" /* MODULE_P2041 */
,"P2041-Platform" /* MODULE_P2041_PLTFRM */
,"PM" /* MODULE_PM */
,"MMU" /* MODULE_MMU */
,"PIC" /* MODULE_PIC */
,"L3 cache (CPC)" /* MODULE_CPC */
,"DUART" /* MODULE_DUART */
,"SerDes" /* MODULE_SERDES */
,"PIO" /* MODULE_PIO */
,"QM" /* MODULE_QM */
,"BM" /* MODULE_BM */
,"SEC" /* MODULE_SEC */
,"LAW" /* MODULE_LAW */
,"LBC" /* MODULE_LBC */
,"PAMU" /* MODULE_PAMU */
,"FM" /* MODULE_FM */
,"FM-MURAM" /* MODULE_FM_MURAM */
,"FM-PCD" /* MODULE_FM_PCD */
,"FM-RTC" /* MODULE_FM_RTC */
,"FM-MAC" /* MODULE_FM_MAC */
,"FM-Port" /* MODULE_FM_PORT */
,"DPA" /* MODULE_DPA */
};

62
sys/contrib/ncsw/integrations/P3041/module_strings.c
View File

@ -1,62 +0,0 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Module names for debug messages */
const char *moduleStrings[] =
{
"???" /* MODULE_UNKNOWN */
,"MEM" /* MODULE_ */
,"MM" /* MODULE_MM */
,"CORE" /* MODULE_CORE */
,"P3041" /* MODULE_P3041 */
,"P3041-Platform" /* MODULE_P3041_PLTFRM */
,"PM" /* MODULE_PM */
,"MMU" /* MODULE_MMU */
,"PIC" /* MODULE_PIC */
,"L3 cache (CPC)" /* MODULE_CPC */
,"DUART" /* MODULE_DUART */
,"SerDes" /* MODULE_SERDES */
,"PIO" /* MODULE_PIO */
,"QM" /* MODULE_QM */
,"BM" /* MODULE_BM */
,"SEC" /* MODULE_SEC */
,"LAW" /* MODULE_LAW */
,"LBC" /* MODULE_LBC */
,"PAMU" /* MODULE_PAMU */
,"FM" /* MODULE_FM */
,"FM-MURAM" /* MODULE_FM_MURAM */
,"FM-PCD" /* MODULE_FM_PCD */
,"FM-RTC" /* MODULE_FM_RTC */
,"FM-MAC" /* MODULE_FM_MAC */
,"FM-Port" /* MODULE_FM_PORT */
,"DPA" /* MODULE_DPA */
};

62
sys/contrib/ncsw/integrations/P5020/module_strings.c
View File

@ -1,62 +0,0 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Module names for debug messages */
const char *moduleStrings[] =
{
"???" /* MODULE_UNKNOWN */
,"MEM" /* MODULE_ */
,"MM" /* MODULE_MM */
,"CORE" /* MODULE_CORE */
,"P5020" /* MODULE_P5020 */
,"P5020-Platform" /* MODULE_P5020_PLTFRM */
,"PM" /* MODULE_PM */
,"MMU" /* MODULE_MMU */
,"PIC" /* MODULE_PIC */
,"L3 cache (CPC)" /* MODULE_CPC */
,"DUART" /* MODULE_DUART */
,"SerDes" /* MODULE_SERDES */
,"PIO" /* MODULE_PIO */
,"QM" /* MODULE_QM */
,"BM" /* MODULE_BM */
,"SEC" /* MODULE_SEC */
,"LAW" /* MODULE_LAW */
,"LBC" /* MODULE_LBC */
,"PAMU" /* MODULE_PAMU */
,"FM" /* MODULE_FM */
,"FM-MURAM" /* MODULE_FM_MURAM */
,"FM-PCD" /* MODULE_FM_PCD */
,"FM-RTC" /* MODULE_FM_RTC */
,"FM-MAC" /* MODULE_FM_MAC */
,"FM-Port" /* MODULE_FM_PORT */
,"DPA" /* MODULE_DPA */
};

0
sys/contrib/ncsw/integrations/P3041/fman_ctrl_code/p3041_r1.0.h → sys/contrib/ncsw/integrations/fman_ctrl_code/p3041_r1.0.h
View File

2
sys/contrib/ncsw/integrations/fman_ucode.h
View File

@ -38,7 +38,7 @@
/**
* Header with actual uCode rel_101_8.
*/
#include "P3041/fman_ctrl_code/p3041_r1.0.h"
#include "fman_ctrl_code/p3041_r1.0.h"
/**
* Generic macro.

4
sys/powerpc/conf/dpaa/config.dpaa
View File

@ -1,6 +1,8 @@
# $FreeBSD$
makeoptions DPAA_COMPILE_CMD_COMMON="${NORMAL_C} \
files "dpaa/files.dpaa"
makeoptions DPAA_COMPILE_CMD="${NORMAL_C} \
-Wno-cast-qual -Wno-unused-function -Wno-init-self -fms-extensions \
-include $S/contrib/ncsw/build/dflags.h \
-I$S/contrib/ncsw/build/ \

11
sys/powerpc/conf/dpaa/config.p2041
View File

@ -1,11 +0,0 @@
# $FreeBSD$
files "dpaa/files.dpaa"
files "dpaa/files.p2041"
include "dpaa/config.dpaa"
makeoptions DPAA_COMPILE_CMD="${DPAA_COMPILE_CMD_COMMON} \
-I$S/contrib/ncsw/inc/integrations/P2041"
device dpaa

11
sys/powerpc/conf/dpaa/config.p3041
View File

@ -1,11 +0,0 @@
# $FreeBSD$
files "dpaa/files.dpaa"
files "dpaa/files.p3041"
include "dpaa/config.dpaa"
makeoptions DPAA_COMPILE_CMD="${DPAA_COMPILE_CMD_COMMON} \
-I$S/contrib/ncsw/inc/integrations/P3041"
device dpaa

11
sys/powerpc/conf/dpaa/config.p5020
View File

@ -1,11 +0,0 @@
# $FreeBSD$
files "dpaa/files.dpaa"
files "dpaa/files.p5020"
include "dpaa/config.dpaa"
makeoptions DPAA_COMPILE_CMD="${DPAA_COMPILE_CMD_COMMON} \
-I$S/contrib/ncsw/inc/integrations/P5020"
device dpaa

3
sys/powerpc/conf/dpaa/files.p2041
View File

@ -1,3 +0,0 @@
# $FreeBSD$
contrib/ncsw/integrations/P2041/module_strings.c optional dpaa

3
sys/powerpc/conf/dpaa/files.p3041
View File

@ -1,3 +0,0 @@
# $FreeBSD$
contrib/ncsw/integrations/P3041/module_strings.c optional dpaa

3
sys/powerpc/conf/dpaa/files.p5020
View File

@ -1,3 +0,0 @@
# $FreeBSD$
contrib/ncsw/integrations/P5020/module_strings.c optional dpaa