Merge commit 00925aadb from llvm git (by Fangrui Song):
[ELF][PPC32] Fix canonical PLTs when the order does not match the PLT order Reviewed By: Bdragon28 Differential Revision: https://reviews.llvm.org/D75394 This is needed to fix miscompiled canonical PLTs on ppc32/lld10. Requested by: bdragon MFC after: 6 weeks X-MFC-With: 358851 Differential Revision: https://reviews.freebsd.org/D24109
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@ -71,12 +71,11 @@ void writePPC32GlinkSection(uint8_t *buf, size_t numEntries) {
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// non-GOT-non-PLT relocations referencing external functions for -fpie/-fPIE.
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uint32_t glink = in.plt->getVA(); // VA of .glink
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if (!config->isPic) {
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for (const Symbol *sym : in.plt->entries)
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if (sym->needsPltAddr) {
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writePPC32PltCallStub(buf, sym->getGotPltVA(), nullptr, 0);
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buf += 16;
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glink += 16;
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}
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for (const Symbol *sym : cast<PPC32GlinkSection>(in.plt)->canonical_plts) {
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writePPC32PltCallStub(buf, sym->getGotPltVA(), nullptr, 0);
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buf += 16;
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glink += 16;
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}
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}
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// On PPC Secure PLT ABI, bl foo@plt jumps to a call stub, which loads an
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@ -1206,6 +1206,7 @@ static void processRelocAux(InputSectionBase &sec, RelExpr expr, RelType type,
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// PPC32 canonical PLT entries are at the beginning of .glink
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cast<Defined>(sym).value = in.plt->headerSize;
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in.plt->headerSize += 16;
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cast<PPC32GlinkSection>(in.plt)->canonical_plts.push_back(&sym);
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}
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}
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sym.needsPltAddr = true;
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@ -2446,12 +2446,9 @@ PltSection::PltSection()
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: SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16, ".plt"),
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headerSize(target->pltHeaderSize) {
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// On PowerPC, this section contains lazy symbol resolvers.
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if (config->emachine == EM_PPC || config->emachine == EM_PPC64) {
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if (config->emachine == EM_PPC64) {
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name = ".glink";
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alignment = 4;
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// PLTresolve is at the end.
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if (config->emachine == EM_PPC)
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footerSize = 64;
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}
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// On x86 when IBT is enabled, this section contains the second PLT (lazy
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@ -2467,11 +2464,6 @@ PltSection::PltSection()
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}
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void PltSection::writeTo(uint8_t *buf) {
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if (config->emachine == EM_PPC) {
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writePPC32GlinkSection(buf, entries.size());
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return;
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}
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// At beginning of PLT, we have code to call the dynamic
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// linker to resolve dynsyms at runtime. Write such code.
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target->writePltHeader(buf);
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@ -2489,7 +2481,7 @@ void PltSection::addEntry(Symbol &sym) {
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}
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size_t PltSection::getSize() const {
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return headerSize + entries.size() * target->pltEntrySize + footerSize;
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return headerSize + entries.size() * target->pltEntrySize;
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}
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bool PltSection::isNeeded() const {
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@ -2543,6 +2535,19 @@ void IpltSection::addSymbols() {
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}
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}
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PPC32GlinkSection::PPC32GlinkSection() {
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name = ".glink";
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alignment = 4;
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}
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void PPC32GlinkSection::writeTo(uint8_t *buf) {
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writePPC32GlinkSection(buf, entries.size());
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}
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size_t PPC32GlinkSection::getSize() const {
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return headerSize + entries.size() * target->pltEntrySize + footerSize;
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}
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// This is an x86-only extra PLT section and used only when a security
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// enhancement feature called CET is enabled. In this comment, I'll explain what
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// the feature is and why we have two PLT sections if CET is enabled.
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@ -684,7 +684,6 @@ public:
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size_t getNumEntries() const { return entries.size(); }
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size_t headerSize;
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size_t footerSize = 0;
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std::vector<const Symbol *> entries;
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};
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@ -705,6 +704,16 @@ public:
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void addEntry(Symbol &sym);
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};
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class PPC32GlinkSection : public PltSection {
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public:
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PPC32GlinkSection();
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void writeTo(uint8_t *buf) override;
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size_t getSize() const override;
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std::vector<const Symbol *> canonical_plts;
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static constexpr size_t footerSize = 64;
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};
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// This is x86-only.
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class IBTPltSection : public SyntheticSection {
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public:
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@ -521,7 +521,8 @@ template <class ELFT> void createSyntheticSections() {
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add(in.ibtPlt);
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}
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in.plt = make<PltSection>();
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in.plt = config->emachine == EM_PPC ? make<PPC32GlinkSection>()
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: make<PltSection>();
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add(in.plt);
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in.iplt = make<IpltSection>();
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add(in.iplt);
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