o Fix style(9) bugs and similar nits.
o Merge ncr53c9x.c from NetBSD: 1.115: fix variable shadowing 1.118: __inline -> inline 1.121: fix empty if
This commit is contained in:
Marius Strobl
parent
9b78febf8e
commit
93060c6c1b
@ -158,19 +158,19 @@ MODULE_DEPEND(esp, sbus, 1, 1, 1);
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MODULE_DEPEND(esp, cam, 1, 1, 1);
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/*
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* Functions and the switch for the MI code.
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* Functions and the switch for the MI code
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*/
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static u_char esp_read_reg(struct ncr53c9x_softc *, int);
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static void esp_write_reg(struct ncr53c9x_softc *, int, u_char);
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static int esp_dma_isintr(struct ncr53c9x_softc *);
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static void esp_dma_reset(struct ncr53c9x_softc *);
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static int esp_dma_intr(struct ncr53c9x_softc *);
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static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *,
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int, size_t *);
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static void esp_dma_go(struct ncr53c9x_softc *);
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static void esp_dma_stop(struct ncr53c9x_softc *);
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static int esp_dma_isactive(struct ncr53c9x_softc *);
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static int espattach(struct esp_softc *, struct ncr53c9x_glue *);
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static u_char esp_read_reg(struct ncr53c9x_softc *sc, int reg);
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static void esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v);
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static int esp_dma_isintr(struct ncr53c9x_softc *sc);
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static void esp_dma_reset(struct ncr53c9x_softc *sc);
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static int esp_dma_intr(struct ncr53c9x_softc *sc);
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static int esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr,
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size_t *len, int datain, size_t *dmasize);
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static void esp_dma_go(struct ncr53c9x_softc *sc);
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static void esp_dma_stop(struct ncr53c9x_softc *sc);
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static int esp_dma_isactive(struct ncr53c9x_softc *sc);
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static int espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep);
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static struct ncr53c9x_glue esp_sbus_glue = {
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esp_read_reg,
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@ -311,7 +311,7 @@ esp_sbus_attach(device_t dev)
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esc->sc_regh = rman_get_bushandle(esc->sc_res);
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} else {
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/*
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* Search accompanying DMA engine. It should have been
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* Search accompanying DMA engine. It should have been
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* already attached otherwise there isn't much we can do.
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*/
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if (device_get_children(device_get_parent(dev), &children,
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@ -498,9 +498,6 @@ esp_resume(device_t dev)
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return (ENXIO);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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static int
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espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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{
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@ -530,7 +527,7 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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*/
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/*
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* Read the part-unique ID code of the SCSI chip. The contained
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* Read the part-unique ID code of the SCSI chip. The contained
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* value is only valid if all of the following conditions are met:
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* - After power-up or chip reset.
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* - Before any value is written to this register.
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@ -570,7 +567,7 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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/* NCRCFG2_FE enables > 64K transfers. */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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@ -581,15 +578,18 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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case 0x00:
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sc->sc_rev = NCR_VARIANT_FAS100A;
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break;
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case 0x02:
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if ((uid & 0x07) == 0x02)
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sc->sc_rev = NCR_VARIANT_FAS216;
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else
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sc->sc_rev = NCR_VARIANT_FAS236;
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break;
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case 0x0a:
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sc->sc_rev = NCR_VARIANT_FAS366;
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break;
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default:
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/*
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* We could just treat unknown chips
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@ -660,10 +660,10 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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/*
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* The onboard SCSI chips in Sun Ultra 1 are actually
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* documented to be NCR53C9X which use NCRCFG3_FCLK and
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* NCRCFG3_FSCSI. BSD/OS however probes these chips as
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* NCRCFG3_FSCSI. BSD/OS however probes these chips as
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* FAS100A and uses NCRF9XCFG3_FCLK and NCRF9XCFG3_FSCSI
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* instead which seems to be correct as otherwise sync
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* negotiation just doesn't work. Using NCRF9XCFG3_FCLK
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* negotiation just doesn't work. Using NCRF9XCFG3_FCLK
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* and NCRF9XCFG3_FSCSI with these chips in fact also
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* yields Fast-SCSI speed.
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*/
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@ -683,7 +683,7 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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/* Limit minsync due to unsolved performance issues. */
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sc->sc_maxsync = sc->sc_minsync;
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/* Establish interrupt channel */
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/* Establish interrupt channel. */
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esc->sc_irqrid = 0;
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if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,
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&esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) {
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@ -697,7 +697,7 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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goto fail_ires;
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}
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/* Turn on target selection using the `DMA' method */
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/* Turn on target selection using the `DMA' method. */
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if (sc->sc_rev != NCR_VARIANT_FAS366)
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sc->sc_features |= NCR_F_DMASELECT;
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@ -720,7 +720,7 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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}
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/*
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* Glue functions.
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* Glue functions
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*/
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#ifdef ESP_SBUS_DEBUG
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@ -844,11 +844,8 @@ static void
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esp_dma_stop(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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uint32_t csr;
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csr = L64854_GCSR(esc->sc_dma);
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csr &= ~D_EN_DMA;
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L64854_SCSR(esc->sc_dma, csr);
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L64854_SCSR(esc->sc_dma, L64854_GCSR(esc->sc_dma) & ~D_EN_DMA);
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}
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static int
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File diff suppressed because it is too large
Load Diff
@ -69,20 +69,20 @@
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/* $FreeBSD$ */
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#ifndef _DEV_IC_NCR53C9XVAR_H_
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#define _DEV_IC_NCR53C9XVAR_H_
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#define _DEV_IC_NCR53C9XVAR_H_
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#include <sys/lock.h>
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/* Set this to 1 for normal debug, or 2 for per-target tracing. */
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/* #define NCR53C9X_DEBUG 2 */
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/* #define NCR53C9X_DEBUG 2 */
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/* Wide or differential can have 16 targets */
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#define NCR_NLUN 8
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#define NCR_NLUN 8
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#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
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#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
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#define FREQTOCCF(freq) (((freq + 4) / 5))
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#define FREQTOCCF(freq) (((freq + 4) / 5))
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/*
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* NCR 53c9x variants. Note these values are used as indexes into
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@ -104,7 +104,7 @@
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#define NCR_VARIANT_MAX 13
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/* XXX Max tag depth. Should this be defined in the register header? */
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#define NCR_TAG_DEPTH 256
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#define NCR_TAG_DEPTH 256
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/*
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* ECB. Holds additional information for each SCSI command Comments: We
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@ -138,7 +138,7 @@ struct ncr53c9x_ecb {
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char *daddr; /* Saved data pointer */
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int clen; /* Size of command in cmd.cmd */
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int dleft; /* Residue */
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u_char stat; /* SCSI status byte */
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u_char stat; /* SCSI status byte */
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u_char tag[2]; /* TAG bytes */
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u_char pad[1];
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@ -147,14 +147,14 @@ struct ncr53c9x_ecb {
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#endif
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};
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#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
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#define ECB_TRACE(ecb, msg, a, b) do { \
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#define ECB_TRACE(ecb, msg, a, b) do { \
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const char *f = "[" msg "]"; \
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int n = strlen((ecb)->trace); \
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if (n < (sizeof((ecb)->trace)-100)) \
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sprintf((ecb)->trace + n, f, a, b); \
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sprintf((ecb)->trace + n, f, a, b); \
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} while(0)
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#else
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#define ECB_TRACE(ecb, msg, a, b)
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#define ECB_TRACE(ecb, msg, a, b)
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#endif
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/*
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@ -186,14 +186,14 @@ struct ncr53c9x_tinfo {
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int touts; /* # of timeouts */
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int perrs; /* # of parity errors */
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int senses; /* # of request sense commands sent */
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u_char flags;
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#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
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#define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */
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#define T_SYNCHOFF 0x10 /* SYNC mode for is permanently off */
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#define T_RSELECTOFF 0x20 /* RE-SELECT mode is off */
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#define T_TAG 0x40 /* Turn on TAG QUEUEs */
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#define T_WIDE 0x80 /* Negotiate wide options */
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#define T_WDTRSENT 0x04 /* WDTR message has been sent to */
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u_char flags;
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#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
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#define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */
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#define T_SYNCHOFF 0x10 /* SYNC mode for is permanently off */
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#define T_RSELECTOFF 0x20 /* RE-SELECT mode is off */
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#define T_TAG 0x40 /* Turn on TAG QUEUEs */
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#define T_WIDE 0x80 /* Negotiate wide options */
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#define T_WDTRSENT 0x04 /* WDTR message has been sent to */
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u_char period; /* Period suggestion */
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u_char offset; /* Offset suggestion */
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u_char cfg3; /* per target config 3 */
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@ -204,59 +204,59 @@ struct ncr53c9x_tinfo {
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};
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/* Look up a lun in a tinfo */
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#define TINFO_LUN(t, l) ( \
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#define TINFO_LUN(t, l) ( \
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(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
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? ((t)->lun[(l)]) \
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: ncr53c9x_lunsearch((t), (int64_t)(l)) \
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)
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/* Register a linenumber (for debugging) */
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#define LOGLINE(p)
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#define LOGLINE(p)
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#define NCR_SHOWECBS 0x01
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#define NCR_SHOWINTS 0x02
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#define NCR_SHOWCMDS 0x04
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#define NCR_SHOWMISC 0x08
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#define NCR_SHOWTRAC 0x10
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#define NCR_SHOWSTART 0x20
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#define NCR_SHOWPHASE 0x40
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#define NCR_SHOWDMA 0x80
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#define NCR_SHOWCCMDS 0x100
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#define NCR_SHOWMSGS 0x200
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#define NCR_SHOWECBS 0x01
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#define NCR_SHOWINTS 0x02
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#define NCR_SHOWCMDS 0x04
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#define NCR_SHOWMISC 0x08
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#define NCR_SHOWTRAC 0x10
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#define NCR_SHOWSTART 0x20
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#define NCR_SHOWPHASE 0x40
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#define NCR_SHOWDMA 0x80
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#define NCR_SHOWCCMDS 0x100
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#define NCR_SHOWMSGS 0x200
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#ifdef NCR53C9X_DEBUG
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extern int ncr53c9x_debug;
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#define NCR_ECBS(str) \
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#define NCR_ECBS(str) \
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do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
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#define NCR_MISC(str) \
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#define NCR_MISC(str) \
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do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
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#define NCR_INTS(str) \
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#define NCR_INTS(str) \
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do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
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#define NCR_TRACE(str) \
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#define NCR_TRACE(str) \
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do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
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#define NCR_CMDS(str) \
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#define NCR_CMDS(str) \
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do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
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#define NCR_START(str) \
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#define NCR_START(str) \
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do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
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#define NCR_PHASE(str) \
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#define NCR_PHASE(str) \
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do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
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#define NCR_DMA(str) \
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#define NCR_DMA(str) \
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do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
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#define NCR_MSGS(str) \
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#define NCR_MSGS(str) \
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do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
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#else
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#define NCR_ECBS(str)
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#define NCR_MISC(str)
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#define NCR_INTS(str)
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#define NCR_TRACE(str)
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#define NCR_CMDS(str)
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#define NCR_START(str)
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#define NCR_PHASE(str)
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#define NCR_DMA(str)
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#define NCR_MSGS(str)
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#define NCR_ECBS(str)
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#define NCR_MISC(str)
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#define NCR_INTS(str)
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#define NCR_TRACE(str)
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#define NCR_CMDS(str)
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#define NCR_START(str)
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#define NCR_PHASE(str)
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#define NCR_DMA(str)
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#define NCR_MSGS(str)
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#endif
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#define NCR_MAX_MSG_LEN 8
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#define NCR_MAX_MSG_LEN 8
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struct ncr53c9x_softc;
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@ -305,12 +305,11 @@ struct ncr53c9x_softc {
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u_char sc_espintr;
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u_char sc_espstat;
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u_char sc_espstep;
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u_char sc_espstat2;
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u_char sc_espstat2;
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u_char sc_espfflags;
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/* Lists of command blocks */
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TAILQ_HEAD(ecb_list, ncr53c9x_ecb)
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ready_list;
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TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
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struct ncr53c9x_ecb *sc_nexus; /* Current command */
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int sc_ntarg;
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@ -329,7 +328,7 @@ struct ncr53c9x_softc {
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u_char sc_lastcmd;
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/* Message stuff */
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u_short sc_msgify; /* IDENTIFY message associated with this nexus */
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u_short sc_msgify; /* IDENTIFY message associated with nexus */
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u_short sc_msgout; /* What message is on its way out? */
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u_short sc_msgpriq; /* One or more messages to send (encoded) */
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u_short sc_msgoutq; /* What messages have been sent so far? */
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@ -365,72 +364,72 @@ struct ncr53c9x_softc {
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};
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/* values for sc_state */
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#define NCR_IDLE 1 /* Waiting for something to do */
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#define NCR_SELECTING 2 /* SCSI command is arbiting */
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#define NCR_RESELECTED 3 /* Has been reselected */
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#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
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#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
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#define NCR_IDLE 1 /* Waiting for something to do */
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#define NCR_SELECTING 2 /* SCSI command is arbiting */
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#define NCR_RESELECTED 3 /* Has been reselected */
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#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
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#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
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#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
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#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
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#define NCR_CLEANING 8
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#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
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#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
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/* values for sc_flags */
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#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
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#define NCR_ABORTING 0x02 /* Bailing out */
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#define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
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#define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
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#define NCR_ICCS 0x10 /* Expect status phase results */
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#define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */
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#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
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#define NCR_ABORTING 0x02 /* Bailing out */
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#define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
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#define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
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#define NCR_ICCS 0x10 /* Expect status phase results */
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#define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */
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#define NCR_ATN 0x40 /* ATN asserted */
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#define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */
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/* values for sc_features */
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#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
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#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
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#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
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#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
|
||||
#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
|
||||
|
||||
/* values for sc_msgout */
|
||||
#define SEND_DEV_RESET 0x0001
|
||||
#define SEND_PARITY_ERROR 0x0002
|
||||
#define SEND_INIT_DET_ERR 0x0004
|
||||
#define SEND_REJECT 0x0008
|
||||
#define SEND_IDENTIFY 0x0010
|
||||
#define SEND_ABORT 0x0020
|
||||
#define SEND_WDTR 0x0040
|
||||
#define SEND_SDTR 0x0080
|
||||
#define SEND_TAG 0x0100
|
||||
#define SEND_DEV_RESET 0x0001
|
||||
#define SEND_PARITY_ERROR 0x0002
|
||||
#define SEND_INIT_DET_ERR 0x0004
|
||||
#define SEND_REJECT 0x0008
|
||||
#define SEND_IDENTIFY 0x0010
|
||||
#define SEND_ABORT 0x0020
|
||||
#define SEND_WDTR 0x0040
|
||||
#define SEND_SDTR 0x0080
|
||||
#define SEND_TAG 0x0100
|
||||
|
||||
/* SCSI Status codes */
|
||||
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
|
||||
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
|
||||
|
||||
/* phase bits */
|
||||
#define IOI 0x01
|
||||
#define CDI 0x02
|
||||
#define MSGI 0x04
|
||||
#define IOI 0x01
|
||||
#define CDI 0x02
|
||||
#define MSGI 0x04
|
||||
|
||||
/* Information transfer phases */
|
||||
#define DATA_OUT_PHASE (0)
|
||||
#define DATA_IN_PHASE (IOI)
|
||||
#define COMMAND_PHASE (CDI)
|
||||
#define STATUS_PHASE (CDI|IOI)
|
||||
#define MESSAGE_OUT_PHASE (MSGI|CDI)
|
||||
#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
|
||||
#define DATA_OUT_PHASE (0)
|
||||
#define DATA_IN_PHASE (IOI)
|
||||
#define COMMAND_PHASE (CDI)
|
||||
#define STATUS_PHASE (CDI | IOI)
|
||||
#define MESSAGE_OUT_PHASE (MSGI | CDI)
|
||||
#define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
|
||||
|
||||
#define PHASE_MASK (MSGI|CDI|IOI)
|
||||
#define PHASE_MASK (MSGI | CDI | IOI)
|
||||
|
||||
/* Some pseudo phases for getphase()*/
|
||||
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
|
||||
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
|
||||
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
|
||||
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
|
||||
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
|
||||
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
|
||||
|
||||
/*
|
||||
* Macros to read and write the chip's registers.
|
||||
*/
|
||||
#define NCR_READ_REG(sc, reg) \
|
||||
#define NCR_READ_REG(sc, reg) \
|
||||
(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
|
||||
#define NCR_WRITE_REG(sc, reg, val) \
|
||||
#define NCR_WRITE_REG(sc, reg, val) \
|
||||
(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
|
||||
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
@ -450,8 +449,8 @@ struct ncr53c9x_softc {
|
||||
#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
|
||||
#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
|
||||
#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
|
||||
#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
|
||||
(*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
|
||||
#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
|
||||
(*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
|
||||
#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
|
||||
#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
|
||||
|
||||
@ -459,14 +458,14 @@ struct ncr53c9x_softc {
|
||||
* Macro to convert the chip register Clock Per Byte value to
|
||||
* Synchronous Transfer Period.
|
||||
*/
|
||||
#define ncr53c9x_cpb2stp(sc, cpb) \
|
||||
#define ncr53c9x_cpb2stp(sc, cpb) \
|
||||
((250 * (cpb)) / (sc)->sc_freq)
|
||||
|
||||
int ncr53c9x_attach(struct ncr53c9x_softc *);
|
||||
int ncr53c9x_detach(struct ncr53c9x_softc *);
|
||||
void ncr53c9x_action(struct cam_sim *, union ccb *);
|
||||
void ncr53c9x_reset(struct ncr53c9x_softc *);
|
||||
void ncr53c9x_intr(void *);
|
||||
void ncr53c9x_init(struct ncr53c9x_softc *, int);
|
||||
int ncr53c9x_attach(struct ncr53c9x_softc *sc);
|
||||
int ncr53c9x_detach(struct ncr53c9x_softc *sc);
|
||||
void ncr53c9x_action(struct cam_sim *sim, union ccb *ccb);
|
||||
void ncr53c9x_reset(struct ncr53c9x_softc *sc);
|
||||
void ncr53c9x_intr(void *arg);
|
||||
void ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset);
|
||||
|
||||
#endif /* _DEV_IC_NCR53C9XVAR_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user