Set the correct values in the arm aux control register, based on chip type.
The bits in the aux control register vary based on the processor type. In the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits, which worked fine for the first few SoCs we supported. Now that we support most of the cortex-a series processors, it's important to get the right bits set based on the processor type. Submitted by: Svatopluk Kraus <onwahe@gmail.com>
This commit is contained in:
Ian Lepore
parent
d2a489eb1a
commit
935c21a18e
@ -1294,7 +1294,7 @@ cortexa_setup(void)
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/* And again. */
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cpu_idcache_wbinv_all();
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#ifdef SMP
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#if defined(SMP) && !defined(ARM_NEW_PMAP)
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armv7_auxctrl((1 << 6) | (1 << 0), (1 << 6) | (1 << 0)); /* Enable SMP + TLB broadcasting */
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#endif
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@ -145,3 +145,82 @@ cpuinfo_init(void)
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cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
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cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
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}
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/*
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* Get bits that must be set or cleared in ACLR register.
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* Note: Bits in ACLR register are IMPLEMENTATION DEFINED.
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* Its expected that SCU is in operational state before this
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* function is called.
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*/
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void
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cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
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{
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*actlr_mask = 0;
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*actlr_set = 0;
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if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) {
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switch (cpuinfo.part_number) {
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case CPU_ARCH_CORTEX_A17:
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case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */
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/*
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* Enable SMP mode
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*/
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*actlr_mask = (1 << 6);
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*actlr_set = (1 << 6);
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break;
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case CPU_ARCH_CORTEX_A15:
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/*
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* Enable snoop-delayed exclusive handling
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* Enable SMP mode
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*/
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*actlr_mask = (1U << 31) |(1 << 6);
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*actlr_set = (1U << 31) |(1 << 6);
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break;
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case CPU_ARCH_CORTEX_A9:
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/*
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* Disable exclusive L1/L2 cache control
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* Enable SMP mode
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* Enable Cache and TLB maintenance broadcast
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*/
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*actlr_mask = (1 << 7) | (1 << 6) | (1 << 0);
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*actlr_set = (1 << 6) | (1 << 0);
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break;
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case CPU_ARCH_CORTEX_A8:
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/*
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* Enable L2 cache
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* Enable L1 data cache hardware alias checks
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*/
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*actlr_mask = (1 << 1) | (1 << 0);
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*actlr_set = (1 << 1);
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break;
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case CPU_ARCH_CORTEX_A7:
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/*
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* Enable SMP mode
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*/
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*actlr_mask = (1 << 6);
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*actlr_set = (1 << 6);
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break;
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case CPU_ARCH_CORTEX_A5:
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/*
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* Disable exclusive L1/L2 cache control
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* Enable SMP mode
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* Enable Cache and TLB maintenance broadcast
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*/
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*actlr_mask = (1 << 7) | (1 << 6) | (1 << 0);
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*actlr_set = (1 << 6) | (1 << 0);
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break;
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case CPU_ARCH_ARM1176:
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/*
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* Restrict cache size to 16KB
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* Enable the return stack
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* Enable dynamic branch prediction
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* Enable static branch prediction
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*/
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*actlr_mask = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
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*actlr_set = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
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break;
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}
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return;
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}
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}
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@ -154,10 +154,12 @@ init_secondary(int cpu)
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#ifndef ARM_INTRNG
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int start = 0, end = 0;
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#endif
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#ifdef ARM_NEW_PMAP
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uint32_t actlr_mask, actlr_set;
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pmap_set_tex();
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reinit_mmu(pmap_kern_ttb, (1<<6) | (1<< 0), (1<<6) | (1<< 0));
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cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
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reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
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cpu_setup();
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/* Provide stack pointers for other processor modes. */
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@ -713,6 +713,7 @@ pmap_bootstrap_prepare(vm_paddr_t last)
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pt1_entry_t *pte1p;
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pt2_entry_t *pte2p;
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u_int i;
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uint32_t actlr_mask, actlr_set;
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/*
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* Now, we are going to make real kernel mapping. Note that we are
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@ -829,8 +830,8 @@ pmap_bootstrap_prepare(vm_paddr_t last)
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/* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
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pmap_kern_ttb = base_pt1 | ttb_flags;
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reinit_mmu(pmap_kern_ttb, (1 << 6) | (1 << 0), (1 << 6) | (1 << 0));
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cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
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reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
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/*
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* Initialize the first available KVA. As kernel image is mapped by
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* sections, we are leaving some gap behind.
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@ -32,6 +32,23 @@
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#include <sys/types.h>
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#define CPU_IMPLEMENTER_ARM 0x41
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#define CPU_IMPLEMENTER_QCOM 0x51
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#define CPU_IMPLEMENTER_MRVL 0x56
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/* ARM */
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#define CPU_ARCH_ARM1176 0xB76
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#define CPU_ARCH_CORTEX_A5 0xC05
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#define CPU_ARCH_CORTEX_A7 0xC07
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#define CPU_ARCH_CORTEX_A8 0xC08
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#define CPU_ARCH_CORTEX_A9 0xC09
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#define CPU_ARCH_CORTEX_A12 0xC0D
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#define CPU_ARCH_CORTEX_A15 0xC0F
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#define CPU_ARCH_CORTEX_A17 0xC11
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/* QCOM */
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#define CPU_ARCH_KRAIT_300 0x06F
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struct cpuinfo {
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/* raw id registers */
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uint32_t midr;
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@ -93,5 +110,5 @@ struct cpuinfo {
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extern struct cpuinfo cpuinfo;
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void cpuinfo_init(void);
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void cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set);
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#endif /* _MACHINE_CPUINFO_H_ */
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