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mips74k: use cache-writeback for memory, not writethrough.

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When I ported this code from netbsd I was .. slightly mips74k greener.
I used writethrough because (a) it's what netbsd did, and (b) if I used
writethrough then things "didn't work."

Fast-forward a couple years, more MIPS hacking and a whole lot more
understanding of the bus APIs (the last few commits notwithstanding;
it's been a long week, ok?) and I have this working for arge,
argemdio, spi and ath.  Hans has it working for USB.  The ath barrier
code will come in a later commit.

This gets the routing throughput up from 220mbit -> 337mbit.
I'm sure the bridging throughput will be similarly improved.

Tested:

* QCA955x SoC, routing workload.
This commit is contained in:
Adrian Chadd 2015-10-31 00:04:44 +00:00
parent f17acb5fbe
commit 941f53b9a9
1 changed files with 1 additions and 1 deletions
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2
sys/mips/include/cpuregs.h
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@ -151,7 +151,7 @@
#if defined(CPU_MIPS74KC)
#define MIPS_CCA_UNCACHED 0x02
#define MIPS_CCA_CACHED 0x00
#define MIPS_CCA_CACHED 0x03
#endif
#ifndef MIPS_CCA_UNCACHED