qcom: add initial SCM legacy API
This is a very simple implementation of Qualcomm's SCM API. It is just the structure/field definitions and the atomic SCM call which doesn't use the structs yet - it uses the field definitions inside registers. I've tested that setting the cold boot address via the atomic API is fine - Linux does the same thing. But not all SCM calls can be done via the legacy API. This is a reimplementation based on the Linux qualcomm SCM legacy code and definitions. Tested: * Qualcomm IPQ4018 AP, as part of other changes for doing SMP bring-up Reviewed by: andrew, manu, imp Differential Revision: https://reviews.freebsd.org/D32723
This commit is contained in:
Adrian Chadd
parent
a516ccc4ae
commit
960e65d23a
@ -25,6 +25,9 @@ device sdhci
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device generic_timer
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device mpcore_timer
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# PSCI - SMC calls, needed for qualcomm SCM
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device psci
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options FDT
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# Disable CP14 work in DDB as TZ won't let us by default
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122
sys/arm/qualcomm/qcom_scm_defs.h
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122
sys/arm/qualcomm/qcom_scm_defs.h
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@ -0,0 +1,122 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_SCM_DEFS_H__
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#define __QCOM_SCM_DEFS_H__
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/*
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* Maximum SCM arguments and return values.
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*/
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#define MAX_QCOM_SCM_ARGS 10
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#define MAX_QCOM_SCM_RETS 3
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/*
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* SCM argument type definitions.
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*/
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#define QCOM_SCM_ARGTYPE_VAL 0x00
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#define QCOM_SCM_ARGTYPE_RO 0x01
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#define QCOM_SCM_ARGTYPE_RW 0x02
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#define QCOM_SCM_ARGTYPE_BUFVAL 0x03
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/*
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* SCM calls + arguments.
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*/
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#define QCOM_SCM_SVC_BOOT 0x01
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#define QCOM_SCM_BOOT_SET_ADDR 0x01
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#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
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#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
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#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
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#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
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/* Flags for QCOM_SCM_BOOT_SET_ADDR argv[0] */
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/* Note: no COLDBOOT for CPU0, it's already booted */
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#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
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#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
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#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
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#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
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#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
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#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
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#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
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#define QCOM_SCM_SVC_PIL 0x02
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#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
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#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
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#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
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#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
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#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
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#define QCOM_SCM_SVC_IO 0x05
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#define QCOM_SCM_IO_READ 0x01
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#define QCOM_SCM_IO_WRITE 0x02
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/*
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* Fetch SCM call availability information.
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*/
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#define QCOM_SCM_SVC_INFO 0x06
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#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
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#define QCOM_SCM_SVC_MP 0x0c
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#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
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#define QCOM_SCM_MP_VIDEO_VAR 0x08
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#define QCOM_SCM_MP_ASSIGN 0x16
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#define QCOM_SCM_SVC_OCMEM 0x0f
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#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
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#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
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#define QCOM_SCM_SVC_ES 0x10
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#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
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#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
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#define QCOM_SCM_SVC_HDCP 0x11
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#define QCOM_SCM_HDCP_INVOKE 0x01
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#define QCOM_SCM_SVC_LMH 0x13
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#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
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#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
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#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
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/*
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* Return values from the SCM calls.
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*/
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#define QCOM_SCM_RETVAL_V2_EBUSY -12
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#define QCOM_SCM_RETVAL_ENOMEM -5
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#define QCOM_SCM_RETVAL_EOPNOTSUPP -4
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#define QCOM_SCM_RETVAL_EINVAL_ADDR -3
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#define QCOM_SCM_RETVAL_EINVAL_ARG -2
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#define QCOM_SCM_RETVAL_ERROR -1
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#define QCOM_SCM_RETVAL_INTERRUPTED 1
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#endif /* __QCOM_SCM_DEFS_H__ */
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88
sys/arm/qualcomm/qcom_scm_legacy.c
Normal file
88
sys/arm/qualcomm/qcom_scm_legacy.c
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@ -0,0 +1,88 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/reboot.h>
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#include <sys/devmap.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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#include <machine/smp.h>
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#include <arm/qualcomm/qcom_scm_defs.h>
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#include <arm/qualcomm/qcom_scm_legacy_defs.h>
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#include <arm/qualcomm/qcom_scm_legacy.h>
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#include <dev/psci/smccc.h>
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/*
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* Set the cold boot address for (later) a mask of CPUs.
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*
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* Don't set it for CPU0, that CPU is the boot CPU and is already alive.
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*
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* For now it sets it on CPU1..3.
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*
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* This works on the IPQ4019 as tested; the retval is 0x0.
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*/
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uint32_t
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qcom_scm_legacy_mp_set_cold_boot_address(vm_offset_t mp_entry_func)
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{
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struct arm_smccc_res res;
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int ret;
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int context_id;
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uint32_t scm_arg0 = QCOM_SCM_LEGACY_ATOMIC_ID(QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_ADDR, 2);
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uint32_t scm_arg1 = QCOM_SCM_FLAG_COLDBOOT_CPU1
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| QCOM_SCM_FLAG_COLDBOOT_CPU2
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| QCOM_SCM_FLAG_COLDBOOT_CPU3;
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uint32_t scm_arg2 = pmap_kextract((vm_offset_t)mp_entry_func);
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ret = arm_smccc_smc(scm_arg0, (uint32_t) &context_id, scm_arg1,
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scm_arg2, 0, 0, 0, 0, &res);
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if (ret == 0 && res.a0 == 0)
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return (0);
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printf("%s: called; error; ret=0x%08x; retval[0]=0x%08x\n",
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__func__, ret, res.a0);
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return (0);
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}
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41
sys/arm/qualcomm/qcom_scm_legacy.h
Normal file
41
sys/arm/qualcomm/qcom_scm_legacy.h
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@ -0,0 +1,41 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_SCM_LEGACY_H__
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#define __QCOM_SCM_LEGACY_H__
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/*
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* These functions are specific to the 32 bit legacy SCM interface
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* used by the IPQ806x and IPQ401x SoCs.
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*/
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extern uint32_t qcom_scm_legacy_mp_set_cold_boot_address(
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vm_offset_t mp_entry_func);
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#endif /* __QCOM_SCM_LEGACY_H__ */
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149
sys/arm/qualcomm/qcom_scm_legacy_defs.h
Normal file
149
sys/arm/qualcomm/qcom_scm_legacy_defs.h
Normal file
@ -0,0 +1,149 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_SCM_LEGACY_DEFS_H__
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#define __QCOM_SCM_LEGACY_DEFS_H__
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/*
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* These definitions are specific to the 32 bit legacy SCM interface
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* used by the IPQ806x and IPQ401x SoCs.
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*/
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/*
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* Mapping of the SCM service/command fields into the a0 argument
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* in an SMC instruction call.
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*
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* This is particular to the legacy SCM interface, and is not the
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* same as the non-legacy 32/64 bit FNID mapping layout.
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*/
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#define QCOM_SCM_LEGACY_SMC_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
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/*
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* There are two kinds of SCM calls in this legacy path.
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*
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* The first kind are the normal ones - up to a defined max of arguments,
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* a defined max of responses and some identifiers for all of it.
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* They can be issues in parallel on different cores, can be interrupted,
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* etc.
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*
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* The second kind are what are termed "atomic" SCM calls -
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* up to 5 argument DWORDs, up to 3 response DWORDs, done atomically,
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* not interruptable/parallel.
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*
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* The former use the structures below to represent the request and response
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* in memory. The latter use defines and a direct SMC call with the
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* arguments in registers.
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*/
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struct qcom_scm_legacy_smc_args {
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uint32_t args[8];
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};
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/*
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* Atomic SCM call command/response buffer definitions.
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*/
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#define QCOM_SCM_LEGACY_ATOMIC_MAX_ARGCOUNT 5
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#define QCOM_SCM_LEGACY_CLASS_REGISTER (0x2 << 8)
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#define QCOM_SCM_LEGACY_MASK_IRQS (1U << 5)
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/*
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* Mapping an SCM service/command/argcount into the a0 register
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* for an SMC instruction call.
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*/
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#define QCOM_SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
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((QCOM_SCM_LEGACY_SMC_FNID((svc), cmd) << 12) | \
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QCOM_SCM_LEGACY_CLASS_REGISTER | \
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QCOM_SCM_LEGACY_MASK_IRQS | \
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((n) & 0xf))
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/*
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* Legacy command/response buffer definitions.
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*
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* The legacy path contains up to the defined maximum arguments
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* but only a single command/response pair per call.
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*
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* A command and response buffer is laid out in memory as such:
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*
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* | command header |
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* | (buffer payload) |
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* | response header |
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* | (response payload) |
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*/
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/*
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* The command header.
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*
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* len - the length of the total command and response, including
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* the headers.
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*
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* buf_offset - the offset inside the buffer, starting at the
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* beginning of this command header, where the command buffer
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* is found. The end is the byte before the response_header_offset.
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*
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* response_header_offset - the offset inside the buffer where
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* the response header is found.
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*
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* id - the QCOM_SCM_LEGACY_SMC_FNID() - service/command ids
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*/
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struct qcom_scm_legacy_command_header {
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uint32_t len;
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uint32_t buf_offset;
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uint32_t response_header_offset;
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uint32_t id;
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};
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/*
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* The response header.
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*
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* This is found immediately after the command header and command
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* buffer payload.
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*
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* len - the total amount of memory available for the response.
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* Linux doesn't set this; it always passes in a response
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* buffer large enough to store MAX_QCOM_SCM_RETS * DWORD
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* bytes.
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*
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* It's also possible this is set by the firmware.
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*
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* buf_offset - start of response buffer, relative to the beginning
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* of the command header. This also isn't set in Linux before
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* calling the SMC instruction, but it is checked afterwards
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* to assemble a pointer to the response data. The firmware
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* likely sets this.
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*
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* is_complete - true if complete. Linux loops over DMA sync to
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* check if this is complete even after the SMC call returns.
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*/
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struct qcom_scm_legacy_response_header {
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uint32_t len;
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uint32_t buf_offset;
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uint32_t is_complete;
|
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};
|
||||
|
||||
#endif /* __QCOM_SCM_LEGACY_DEFS_H__ */
|
||||
@ -1,4 +1,5 @@
|
||||
arm/qualcomm/ipq4018_machdep.c standard
|
||||
arm/qualcomm/ipq4018_mp.c optional smp
|
||||
arm/qualcomm/qcom_scm_legacy.c standard
|
||||
|
||||
dev/qcom_rnd/qcom_rnd.c optional qcom_rnd
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user