Remove the old CPU_ values from the arm kernel trampoline. These options
are gone so we can remove them from the code.
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@ -61,26 +61,11 @@ extern void do_call(void *, void *, void *, int);
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#define GZ_HEAD 0xa
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#if defined(CPU_ARM9)
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#define cpu_idcache_wbinv_all arm9_idcache_wbinv_all
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extern void arm9_idcache_wbinv_all(void);
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#elif defined(CPU_FA526)
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#define cpu_idcache_wbinv_all fa526_idcache_wbinv_all
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extern void fa526_idcache_wbinv_all(void);
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#elif defined(CPU_ARM9E)
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#if defined(CPU_ARM9E)
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#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
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extern void armv5_ec_idcache_wbinv_all(void);
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#elif defined(CPU_XSCALE_PXA2X0)
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#define cpu_idcache_wbinv_all xscale_cache_purgeID
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extern void xscale_cache_purgeID(void);
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#elif defined(CPU_XSCALE_81342)
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#define cpu_idcache_wbinv_all xscalec3_cache_purgeID
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extern void xscalec3_cache_purgeID(void);
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#endif
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#ifdef CPU_XSCALE_81342
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#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
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extern void xscalec3_l2cache_purge(void);
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#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
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#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
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#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
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extern void sheeva_l2cache_wbinv_all(void);
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#else
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@ -121,11 +106,6 @@ static int arm_dcache_l2_linesize;
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*/
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static struct arm_boot_params s_boot_params;
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extern int arm9_dcache_sets_inc;
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extern int arm9_dcache_sets_max;
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extern int arm9_dcache_index_max;
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extern int arm9_dcache_index_inc;
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static __inline void *
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memcpy(void *dst, const void *src, int len)
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{
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@ -165,8 +145,6 @@ bzero(void *addr, int count)
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}
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}
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static void arm9_setup(void);
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void
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_startC(unsigned r0, unsigned r1, unsigned r2, unsigned r3)
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{
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@ -250,13 +228,6 @@ _startC(unsigned r0, unsigned r1, unsigned r2, unsigned r3)
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"2: nop\n"
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"mov sp, %2\n"
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: "=r" (tmp1), "+r" (kernphysaddr), "+r" (sp));
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#ifndef KZIP
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#ifdef CPU_ARM9
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/* So that idcache_wbinv works; */
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if ((cpu_ident() & 0x0000f000) == 0x00009000)
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arm9_setup();
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#endif
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#endif
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__start();
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}
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@ -368,18 +339,6 @@ get_cachetype_cp15()
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}
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}
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static void
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arm9_setup(void)
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{
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get_cachetype_cp15();
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arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
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arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
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arm_dcache_l2_nsets)) - arm9_dcache_sets_inc;
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arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
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arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
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}
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#ifdef KZIP
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static unsigned char *orig_input, *i_input, *i_output;
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@ -684,11 +643,6 @@ __start(void)
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pt_addr = L1_TABLE_SIZE +
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rounddown2((int)&_end + KERNSIZE + 0x100, L1_TABLE_SIZE);
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#ifdef CPU_ARM9
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/* So that idcache_wbinv works; */
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if ((cpu_ident() & 0x0000f000) == 0x00009000)
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arm9_setup();
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#endif
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setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
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(vm_paddr_t)curaddr + 0x10000000, 1);
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/* Gzipped kernel */
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