Add support for the 8139C+ chipset. Unlike the other chips in the 8139
series, the 8139C+ has a descriptor-based DMA mechanism, and its performance is actually pretty respectable. Note: the 8139D chip does not support C+ mode. Only the 8139C+ and 8169 gigE chips support C+ mode. Supported features: - RX and TX checksum offload - hardware VLAN tag insertion/extraction - TX interrupt moderation using the 8139's on-board timer Everything should be properly busdma'ed and endian-independent, so things should work ok on non-x86 platforms. Unfortunately, my call for testers on this code was met with deafening silence, and I don't have access to any non-x86 FreeBSD boxes at the moment, so this is speculation. The device detection code has been cleaned up a little as well (thanks to Michal Mertl) for the patches. There are also updates to the rl(4) man page (which I accidentally checked in before when I updated the dc(4) man page. Oops.) Todo: finish support for the 8169 gigabit ethernet chip. This mainly requires writing an rlgphy driver to handle the 8169's built-in PHY. This will have to wait until I actually get my hands on an 8169 card for testing though. (I still can't find a source for one in the U.S. Suggestions/pointers welcome.)
This commit is contained in:
Bill Paul
parent
e0b2dc9329
commit
96fd5c300d
1245
sys/pci/if_rl.c
1245
sys/pci/if_rl.c
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
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/*
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* Copyright (c) 1997, 1998
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* Copyright (c) 1997, 1998-2003
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -99,6 +99,34 @@
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#define RL_RX_ER 0x0072 /* RX_ER counter */
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#define RL_CSCFG 0x0074 /* CS configuration register */
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/*
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* When operating in special C+ mode, some of the registers in an
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* 8139C+ chip have different definitions. These are also used for
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* the 8169 gigE chip.
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*/
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#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
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#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
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#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
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#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
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#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
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#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
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#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
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#define RL_TXSTART 0x00D9 /* 8 bits */
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#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
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#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
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#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
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#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
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/*
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* Registers specific to the 8169 gigE chip
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*/
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#define RL_PHYAR 0x0060
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#define RL_TBICSR 0x0064
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#define RL_TBI_ANAR 0x0068
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#define RL_TBI_LPAR 0x006A
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#define RL_GMEDIASTAT 0x006C /* 8 bits */
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#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
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#define RL_GTXSTART 0x0038 /* 16 bits */
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/*
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* TX config register bits
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@ -108,6 +136,16 @@
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#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
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#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
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#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
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#define RL_TXCFG_HWREV 0x7CC00000
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#define RL_HWREV_8139 0x60000000
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#define RL_HWREV_8139A 0x70000000
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#define RL_HWREV_8139AG 0x70800000
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#define RL_HWREV_8139B 0x78000000
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#define RL_HWREV_8130 0x7C000000
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#define RL_HWREV_8139C 0x74000000
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#define RL_HWREV_8139D 0x74400000
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#define RL_HWREV_8139CPLUS 0x74800000
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#define RL_TXDMA_16BYTES 0x00000000
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#define RL_TXDMA_32BYTES 0x00000100
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@ -142,7 +180,11 @@
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#define RL_ISR_RX_OVERRUN 0x0010
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#define RL_ISR_PKT_UNDERRUN 0x0020
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#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
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#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
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#define RL_ISR_SWI 0x0100 /* C+ only */
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#define RL_ISR_CABLE_LEN_CHGD 0x2000
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#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
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#define RL_ISR_TIMEOUT_EXPIRED 0x4000
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#define RL_ISR_SYSTEM_ERR 0x8000
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#define RL_INTRS \
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@ -150,6 +192,11 @@
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RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
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RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
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#define RL_INTRS_CPLUS \
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(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
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RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
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RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
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/*
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* Media status register. (8139 only)
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*/
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@ -281,6 +328,53 @@
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#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
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#define RL_CFG1_LED1 0x80
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/*
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* 8139C+ register definitions
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*/
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/* RL_DUMPSTATS_LO register */
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#define RL_DUMPSTATS_START 0x00000008
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/* Transmit start register */
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#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
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#define RL_TXSTART_START 0x40 /* start normal queue transmit */
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#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
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/* C+ mode command register */
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#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
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#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
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#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
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#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
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#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
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#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
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/* C+ early transmit threshold */
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#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
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/*
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* Gigabit PHY access register (8169 only)
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*/
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#define RL_PHYAR_PHYDATA 0x0000FFFF
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#define RL_PHYAR_PHYREG 0x001F0000
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#define RL_PHYAR_BUSY 0x80000000
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/*
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* Gigabit media status (8169 only)
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*/
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#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
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#define RL_GMEDIASTAT_LINK 0x02 /* link up */
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#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
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#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
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#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */
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#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
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#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
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#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
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/*
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* The RealTek doesn't use a fragment-based descriptor mechanism.
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* Instead, there are only four register sets, each or which represents
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@ -336,9 +430,16 @@ struct rl_chain_data {
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struct rl_type {
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u_int16_t rl_vid;
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u_int16_t rl_did;
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int rl_basetype;
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char *rl_name;
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};
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struct rl_hwrev {
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u_int32_t rl_rev;
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int rl_type;
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char *rl_desc;
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};
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struct rl_mii_frame {
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u_int8_t mii_stdelim;
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u_int8_t mii_opcode;
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@ -358,6 +459,167 @@ struct rl_mii_frame {
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#define RL_8129 1
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#define RL_8139 2
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#define RL_8139CPLUS 3
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#define RL_8169 4
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#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
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(x)->rl_type == RL_8169)
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/*
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* The 8139C+ and 8160 gigE chips support descriptor-based TX
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* and RX. In fact, they even support TCP large send. Descriptors
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* must be allocated in contiguous blocks that are aligned on a
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* 256-byte boundary. The rings can hold a maximum of 64 descriptors.
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*/
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/*
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* RX/TX descriptor definition. When large send mode is enabled, the
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* lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
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* the checksum offload bits are disabled. The structure layout is
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* the same for RX and TX descriptors
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*/
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struct rl_desc {
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u_int32_t rl_cmdstat;
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u_int32_t rl_vlanctl;
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u_int32_t rl_bufaddr_lo;
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u_int32_t rl_bufaddr_hi;
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};
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#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
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#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
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#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
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#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
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#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
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#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
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#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
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#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
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#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
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#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
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#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
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#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
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/*
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* Error bits are valid only on the last descriptor of a frame
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* (i.e. RL_TDESC_CMD_EOF == 1)
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*/
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#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
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#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
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#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
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#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
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#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
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#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
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#define RL_TDESC_STAT_OWN 0x80000000
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/*
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* RX descriptor cmd/vlan definitions
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*/
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#define RL_RDESC_CMD_EOR 0x40000000
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#define RL_RDESC_CMD_OWN 0x80000000
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#define RL_RDESC_CMD_BUFLEN 0x00001FFF
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#define RL_RDESC_STAT_OWN 0x80000000
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#define RL_RDESC_STAT_EOR 0x40000000
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#define RL_RDESC_STAT_SOF 0x20000000
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#define RL_RDESC_STAT_EOF 0x10000000
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#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
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#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
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#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
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#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
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#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
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#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
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#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
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#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
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#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
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#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
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#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
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#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
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#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
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#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
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#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
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#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
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(rl_vlandata valid)*/
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#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
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#define RL_PROTOID_NONIP 0x00000000
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#define RL_PROTOID_TCPIP 0x00010000
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#define RL_PROTOID_UDPIP 0x00020000
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#define RL_PROTOID_IP 0x00030000
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#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
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RL_PROTOID_TCPIP)
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#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
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RL_PROTOID_UDPIP)
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/*
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* Statistics counter structure (8139C+ and 8169 only)
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*/
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struct rl_stats {
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u_int32_t rl_tx_pkts_lo;
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u_int32_t rl_tx_pkts_hi;
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u_int32_t rl_tx_errs_lo;
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u_int32_t rl_tx_errs_hi;
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u_int32_t rl_tx_errs;
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u_int16_t rl_missed_pkts;
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u_int16_t rl_rx_framealign_errs;
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u_int32_t rl_tx_onecoll;
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u_int32_t rl_tx_multicolls;
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u_int32_t rl_rx_ucasts_hi;
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u_int32_t rl_rx_ucasts_lo;
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u_int32_t rl_rx_bcasts_lo;
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u_int32_t rl_rx_bcasts_hi;
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u_int32_t rl_rx_mcasts;
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u_int16_t rl_tx_aborts;
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u_int16_t rl_rx_underruns;
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};
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#define RL_RX_DESC_CNT 64
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#define RL_TX_DESC_CNT 64
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#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc))
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#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc))
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#define RL_RING_ALIGN 256
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#define RL_IFQ_MAXLEN 512
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#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT)
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#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
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#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \
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RL_RDESC_STAT_FRAGLEN)
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#define RL_PKTSZ(x) ((x) >> 3)
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struct rl_softc;
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struct rl_dmaload_arg {
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struct rl_softc *sc;
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int rl_idx;
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int rl_maxsegs;
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struct rl_desc *rl_ring;
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};
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struct rl_list_data {
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struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT];
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struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT];
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int rl_tx_prodidx;
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int rl_rx_prodidx;
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int rl_tx_considx;
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int rl_tx_free;
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bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT];
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bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT];
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bus_dma_tag_t rl_mtag; /* mbuf mapping tag */
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bus_dma_tag_t rl_stag; /* stats mapping tag */
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bus_dmamap_t rl_smap; /* stats map */
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struct rl_stats *rl_stats;
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u_int32_t rl_stats_addr;
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bus_dma_tag_t rl_rx_list_tag;
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bus_dmamap_t rl_rx_list_map;
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struct rl_desc *rl_rx_list;
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u_int32_t rl_rx_list_addr;
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bus_dma_tag_t rl_tx_list_tag;
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bus_dmamap_t rl_tx_list_map;
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struct rl_desc *rl_tx_list;
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u_int32_t rl_tx_list_addr;
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};
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struct rl_softc {
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struct arpcom arpcom; /* interface info */
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@ -375,6 +637,7 @@ struct rl_softc {
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u_int8_t rl_stats_no_timeout;
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int rl_txthresh;
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struct rl_chain_data rl_cdata;
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struct rl_list_data rl_ldata;
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struct callout_handle rl_stat_ch;
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struct mtx rl_mtx;
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int suspended; /* 0 = normal 1 = suspended */
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@ -424,6 +687,9 @@ struct rl_softc {
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#define RT_DEVICEID_8129 0x8129
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#define RT_DEVICEID_8138 0x8138
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#define RT_DEVICEID_8139 0x8139
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#define RT_DEVICEID_8169 0x8169
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#define RT_REVID_8139CPLUS 0x20
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/*
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* Accton PCI vendor ID
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@ -503,12 +769,37 @@ struct rl_softc {
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/*
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* Planex Communications, Inc. vendor ID
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*/
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#define PLANEX_VENDORID 0x14ea
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#define PLANEX_VENDORID 0x14ea
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/*
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* Planex FNW-3800-TX device ID
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*/
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#define PLANEX_DEVICEID_FNW3800TX 0xab07
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#define PLANEX_DEVICEID_FNW3800TX 0xab07
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/*
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* LevelOne vendor ID
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*/
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#define LEVEL1_VENDORID 0x018A
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/*
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* LevelOne FPC-0106TX devide ID
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*/
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#define LEVEL1_DEVICEID_FPC0106TX 0x0106
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/*
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* Compaq vendor ID
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*/
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#define CP_VENDORID 0x021B
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/*
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* Edimax vendor ID
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*/
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#define EDIMAX_VENDORID 0x13D1
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/*
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* Edimax EP-4103DL cardbus device ID
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*/
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#define EDIMAX_DEVICEID_EP4103DL 0xAB06
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/*
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* PCI low memory base and low I/O base register, and
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Block a user