Added support for Intel PRO/1000 GT Desktop Adapter(Device ID 8086 107C)
Removed support for Intel 82541ER Added fix for 82547 which corrects an issue with Jumbo frames larger than 10k. Added fix for vlan tagged frames not being properly bridged. Corrected TBI workaround. Corrected incorrect LED operation issues Submitted by: tackerman (Tony Ackerman) MFC after: 2 weeks
This commit is contained in:
Prafulla Deuskar
parent
c78752b94b
commit
9821d34f43
@ -51,7 +51,7 @@ struct adapter *em_adapter_list = NULL;
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* Driver version
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*********************************************************************/
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char em_driver_version[] = "1.7.25";
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char em_driver_version[] = "1.7.35";
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/*********************************************************************
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@ -80,7 +80,6 @@ static em_vendor_info_t em_vendor_info_array[] =
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{ 0x8086, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x1013, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x1015, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x1016, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x1017, PCI_ANY_ID, PCI_ANY_ID, 0},
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@ -99,6 +98,7 @@ static em_vendor_info_t em_vendor_info_array[] =
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{ 0x8086, 0x1079, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x107A, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x107B, PCI_ANY_ID, PCI_ANY_ID, 0},
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{ 0x8086, 0x107C, PCI_ANY_ID, PCI_ANY_ID, 0},
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/* required last entry */
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{ 0, 0, 0, 0, 0}
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};
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@ -742,7 +742,7 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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em_init(adapter);
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break;
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default:
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IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)\n", (int)command);
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IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command);
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error = EINVAL;
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}
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@ -797,6 +797,7 @@ em_init_locked(struct adapter * adapter)
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{
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struct ifnet *ifp;
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uint32_t pba;
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ifp = &adapter->interface_data.ac_if;
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INIT_DEBUGOUT("em_init: begin");
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@ -805,6 +806,36 @@ em_init_locked(struct adapter * adapter)
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em_stop(adapter);
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/* Packet Buffer Allocation (PBA)
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* Writing PBA sets the receive portion of the buffer
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* the remainder is used for the transmit buffer.
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*
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* Devices before the 82547 had a Packet Buffer of 64K.
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* Default allocation: PBA=48K for Rx, leaving 16K for Tx.
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* After the 82547 the buffer was reduced to 40K.
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* Default allocation: PBA=30K for Rx, leaving 10K for Tx.
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* Note: default does not leave enough room for Jumbo Frame >10k.
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*/
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if(adapter->hw.mac_type < em_82547) {
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/* Total FIFO is 64K */
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if(adapter->rx_buffer_len > EM_RXBUFFER_8192)
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pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
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else
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pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
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} else {
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/* Total FIFO is 40K */
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if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) {
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pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
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} else {
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pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
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}
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adapter->tx_fifo_head = 0;
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adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
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adapter->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
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}
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INIT_DEBUGOUT1("em_init: pba=%dK",pba);
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E1000_WRITE_REG(&adapter->hw, PBA, pba);
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/* Get the latest mac address, User can use a LAA */
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bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
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ETHER_ADDR_LEN);
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@ -1138,10 +1169,6 @@ em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int e
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bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
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}
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#define EM_FIFO_HDR 0x10
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#define EM_82547_PKT_THRESH 0x3e0
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#define EM_82547_TX_FIFO_SIZE 0x2800
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#define EM_82547_TX_FIFO_BEGIN 0xf00
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/*********************************************************************
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*
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* This routine maps the mbufs to tx descriptors.
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@ -1356,7 +1383,7 @@ em_82547_move_tail_locked(struct adapter *adapter)
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if(eop) {
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if (em_82547_fifo_workaround(adapter, length)) {
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adapter->tx_fifo_wrk++;
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adapter->tx_fifo_wrk_cnt++;
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callout_reset(&adapter->tx_fifo_timer, 1,
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em_82547_move_tail, adapter);
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break;
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@ -1387,7 +1414,7 @@ em_82547_fifo_workaround(struct adapter *adapter, int len)
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fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR);
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if (adapter->link_duplex == HALF_DUPLEX) {
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fifo_space = EM_82547_TX_FIFO_SIZE - adapter->tx_fifo_head;
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fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
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if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
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if (em_82547_tx_fifo_reset(adapter)) {
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@ -1409,8 +1436,8 @@ em_82547_update_fifo_head(struct adapter *adapter, int len)
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/* tx_fifo_head is always 16 byte aligned */
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adapter->tx_fifo_head += fifo_pkt_len;
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if (adapter->tx_fifo_head >= EM_82547_TX_FIFO_SIZE) {
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adapter->tx_fifo_head -= EM_82547_TX_FIFO_SIZE;
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if (adapter->tx_fifo_head >= adapter->tx_fifo_size) {
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adapter->tx_fifo_head -= adapter->tx_fifo_size;
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}
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return;
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@ -1435,17 +1462,17 @@ em_82547_tx_fifo_reset(struct adapter *adapter)
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E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
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/* Reset FIFO pointers */
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E1000_WRITE_REG(&adapter->hw, TDFT, EM_82547_TX_FIFO_BEGIN);
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E1000_WRITE_REG(&adapter->hw, TDFH, EM_82547_TX_FIFO_BEGIN);
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E1000_WRITE_REG(&adapter->hw, TDFTS, EM_82547_TX_FIFO_BEGIN);
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E1000_WRITE_REG(&adapter->hw, TDFHS, EM_82547_TX_FIFO_BEGIN);
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E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr);
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E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr);
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E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
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E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
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/* Re-enable TX unit */
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E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
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E1000_WRITE_FLUSH(&adapter->hw);
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adapter->tx_fifo_head = 0;
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adapter->tx_fifo_reset++;
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adapter->tx_fifo_reset_cnt++;
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return(TRUE);
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}
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@ -1459,13 +1486,23 @@ em_set_promisc(struct adapter * adapter)
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{
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u_int32_t reg_rctl;
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u_int32_t ctrl;
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struct ifnet *ifp = &adapter->interface_data.ac_if;
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reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
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ctrl = E1000_READ_REG(&adapter->hw, CTRL);
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if (ifp->if_flags & IFF_PROMISC) {
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reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
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E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
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/* Disable VLAN stripping in promiscous mode
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* This enables bridging of vlan tagged frames to occur
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* and also allows vlan tags to be seen in tcpdump
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*/
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ctrl &= ~E1000_CTRL_VME;
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E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
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} else if (ifp->if_flags & IFF_ALLMULTI) {
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reg_rctl |= E1000_RCTL_MPE;
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reg_rctl &= ~E1000_RCTL_UPE;
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@ -1486,6 +1523,7 @@ em_disable_promisc(struct adapter * adapter)
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reg_rctl &= (~E1000_RCTL_MPE);
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E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
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em_enable_vlans(adapter);
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return;
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}
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@ -3169,6 +3207,10 @@ em_print_debug_info(struct adapter *adapter)
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uint8_t *hw_addr = adapter->hw.hw_addr;
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printf("em%d: Adapter hardware address = %p \n", unit, hw_addr);
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printf("em%d:CTRL = 0x%x\n", unit,
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E1000_READ_REG(&adapter->hw, CTRL));
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printf("em%d:RCTL = 0x%x PS=(0x8402)\n", unit,
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E1000_READ_REG(&adapter->hw, RCTL));
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printf("em%d:tx_int_delay = %d, tx_abs_int_delay = %d\n", unit,
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E1000_READ_REG(&adapter->hw, TIDV),
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E1000_READ_REG(&adapter->hw, TADV));
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@ -3183,8 +3225,8 @@ em_print_debug_info(struct adapter *adapter)
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adapter->clean_tx_interrupts);
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#endif
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printf("em%d: fifo workaround = %lld, fifo_reset = %lld\n", unit,
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(long long)adapter->tx_fifo_wrk,
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(long long)adapter->tx_fifo_reset);
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(long long)adapter->tx_fifo_wrk_cnt,
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(long long)adapter->tx_fifo_reset_cnt);
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printf("em%d: hw tdh = %d, hw tdt = %d\n", unit,
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E1000_READ_REG(&adapter->hw, TDH),
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E1000_READ_REG(&adapter->hw, TDT));
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@ -399,8 +399,6 @@ struct adapter {
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struct mbuf *fmp;
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struct mbuf *lmp;
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u_int16_t tx_fifo_head;
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struct sysctl_ctx_list sysctl_ctx;
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struct sysctl_oid *sysctl_tree;
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@ -412,8 +410,21 @@ struct adapter {
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unsigned long no_tx_desc_avail2;
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unsigned long no_tx_map_avail;
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unsigned long no_tx_dma_setup;
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u_int64_t tx_fifo_reset;
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u_int64_t tx_fifo_wrk;
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/* Used in for 82547 10Mb Half workaround */
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#define EM_PBA_BYTES_SHIFT 0xA
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#define EM_TX_HEAD_ADDR_SHIFT 7
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#define EM_PBA_TX_MASK 0xFFFF0000
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#define EM_FIFO_HDR 0x10
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#define EM_82547_PKT_THRESH 0x3e0
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u_int32_t tx_fifo_size;
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u_int32_t tx_fifo_head;
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u_int32_t tx_fifo_head_addr;
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u_int64_t tx_fifo_reset_cnt;
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u_int64_t tx_fifo_wrk_cnt;
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u_int32_t tx_head_addr;
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/* For 82544 PCIX Workaround */
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boolean_t pcix_82544;
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File diff suppressed because it is too large
Load Diff
@ -42,7 +42,7 @@
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#include <dev/em/if_em_osdep.h>
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#ifndef NO_VERSION_CONTROL
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#ident "@(#)$RCSfile: if_em_hw.h,v $$Revision: 1.37 $$Date: 2003/12/20 00:14:51 $"
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#ident "@(#)$RCSfile: if_em_hw.h,v $$Revision: 1.41 $$Date: 2004/05/17 15:18:53 $"
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#endif
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/* Forward declarations of structures used by the shared code */
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@ -365,6 +365,7 @@ int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
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#define E1000_DEV_ID_82547GI 0x1075
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#define E1000_DEV_ID_82541GI 0x1076
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#define E1000_DEV_ID_82541GI_MOBILE 0x1077
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#define E1000_DEV_ID_82541GI_LF 0x107C
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#define E1000_DEV_ID_82546GB_COPPER 0x1079
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#define E1000_DEV_ID_82546GB_FIBER 0x107A
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#define E1000_DEV_ID_82546GB_SERDES 0x107B
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@ -378,6 +379,9 @@ int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
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#define E1000_82542_2_0_REV_ID 2
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#define E1000_82542_2_1_REV_ID 3
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#define E1000_REVISION_0 0
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#define E1000_REVISION_1 1
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#define E1000_REVISION_2 2
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#define SPEED_10 10
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#define SPEED_100 100
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@ -772,6 +776,7 @@ struct em_ffvt_entry {
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#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
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#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
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#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
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#define E1000_HOST_IF 0x08800 /* Host Interface */
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#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
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#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
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@ -908,6 +913,7 @@ struct em_ffvt_entry {
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#define E1000_82542_TDFT 0x08018
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#define E1000_82542_FFMT E1000_FFMT
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#define E1000_82542_FFVT E1000_FFVT
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#define E1000_82542_HOST_IF E1000_HOST_IF
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/* Statistics counters collected by the MAC */
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struct em_hw_stats {
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@ -1443,6 +1449,10 @@ struct em_hw {
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#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
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#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
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#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
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#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
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* filtering */
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#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
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* memory */
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#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
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#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
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#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
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@ -1489,6 +1499,7 @@ struct em_hw {
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#define EEPROM_COMPAT 0x0003
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#define EEPROM_ID_LED_SETTINGS 0x0004
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#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
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#define EEPROM_PHY_CLASS_WORD 0x0007
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#define EEPROM_INIT_CONTROL1_REG 0x000A
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#define EEPROM_INIT_CONTROL2_REG 0x000F
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#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
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@ -1522,6 +1533,9 @@ struct em_hw {
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/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
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#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
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/* Mask bit for PHY class in Word 7 of the EEPROM */
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#define EEPROM_PHY_CLASS_A 0x8000
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/* Mask bits for fields in Word 0x0a of the EEPROM */
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#define EEPROM_WORD0A_ILOS 0x0010
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#define EEPROM_WORD0A_SWDPIO 0x01E0
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@ -1549,7 +1563,7 @@ struct em_hw {
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#define PBA_SIZE 4
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/* Collision related configuration parameters */
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#define E1000_COLLISION_THRESHOLD 16
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#define E1000_COLLISION_THRESHOLD 15
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#define E1000_CT_SHIFT 4
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#define E1000_COLLISION_DISTANCE 64
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#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
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@ -2015,7 +2029,7 @@ struct em_hw {
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#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
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/* IGP01E1000 Specific Port Control Register - R/W */
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#define IGP01E1000_PSCR_TP_LOOPBACK 0x0001
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#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
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#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
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#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
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#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
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@ -2025,16 +2039,18 @@ struct em_hw {
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/* IGP01E1000 Specific Port Link Health Register */
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#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
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#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
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#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
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#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
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#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
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#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
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#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
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#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
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#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010
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#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008
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#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004
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#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002
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#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001
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#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000
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#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
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#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
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#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
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#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
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#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
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#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
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/* IGP01E1000 Channel Quality Register */
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#define IGP01E1000_MSE_CHANNEL_D 0x000F
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