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ixgbe: add typecast for type mismatch

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Add typecast for type mismatch.

Signed-off-by: Jakub Chylkowski <jakubx.chylkowski@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>

Approved by:	imp
Obtained from:	DPDK (d8e52b2cf771c31b523b46852fd86225b5a2c721)
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D31621
This commit is contained in:
Guinan Sun 2020-07-09 08:00:37 +00:00 committed by Kevin Bowling
parent d5bbb5500c
commit 994dd6328c
5 changed files with 8 additions and 8 deletions
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8
sys/dev/ixgbe/ixgbe_82599.c
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@ -1583,7 +1583,7 @@ void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
* is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
*/
fdirhashcmd = (u64)fdircmd << 32;
fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common);
IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
@ -1672,7 +1672,7 @@ static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
{
u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port);
mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
@ -1905,14 +1905,14 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
/* record source and destination port (little-endian)*/
fdirport = IXGBE_NTOHS(input->formatted.dst_port);
fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
fdirport |= IXGBE_NTOHS(input->formatted.src_port);
fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port);
IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
}
/* record VLAN (little-endian) and flex_bytes(big-endian) */
fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id);
IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
if (cloud_mode) {

2
sys/dev/ixgbe/ixgbe_common.c
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@ -774,7 +774,7 @@ s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
*pba_num |= data;
*pba_num |= (u32)data;
return IXGBE_SUCCESS;
}

2
sys/dev/ixgbe/ixgbe_dcb_82598.c
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@ -198,7 +198,7 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
max_credits = max[i];
reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
reg |= refill[i];
reg |= (u32)(refill[i]);
reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)

2
sys/dev/ixgbe/ixgbe_dcb_82599.c
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@ -197,7 +197,7 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
max_credits = max[i];
reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
reg |= refill[i];
reg |= (u32)(refill[i]);
reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)

2
sys/dev/ixgbe/ixgbe_x550.c
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@ -730,7 +730,7 @@ static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
setup[0] |= ixgbe_fw_map[i].fw_speed;
setup[0] |= (u32)(ixgbe_fw_map[i].fw_speed);
}
setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;