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First, The Ricoh 5C47x chips don't have the disable the 3e0 bits.

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Second, the TI 1130 need to have the PCI_INTR set, not cleared.

This gets Soren's machine working with NEWCARD again.

# The whole initialization is a mess and needs to be organized ala OLDCARD.
This commit is contained in:
Warner Losh 2001-08-29 20:33:08 +00:00
parent 466df28c52
commit 9a25341262
1 changed files with 11 additions and 5 deletions
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16
sys/dev/pccbb/pccbb.c
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@ -331,7 +331,6 @@ pccbb_chipinit(struct pccbb_softc *sc)
/* disable Legacy IO */ /* disable Legacy IO */
switch (sc->sc_chipset) { switch (sc->sc_chipset) {
case CB_RF5C46X: case CB_RF5C46X:
case CB_RF5C47X:
PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL, PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL,
& ~(PCCBBM_BRIDGECTRL_RL_3E0_EN | & ~(PCCBBM_BRIDGECTRL_RL_3E0_EN |
PCCBBM_BRIDGECTRL_RL_3E2_EN), 2); PCCBBM_BRIDGECTRL_RL_3E2_EN), 2);
@ -348,12 +347,19 @@ pccbb_chipinit(struct pccbb_softc *sc)
| PCCBBM_BRIDGECTRL_WRITE_POST_EN, | PCCBBM_BRIDGECTRL_WRITE_POST_EN,
2); 2);
/* XXX this should be a function table, ala OLDCARD. */
switch (sc->sc_chipset) { switch (sc->sc_chipset) {
case CB_TI113X: case CB_TI113X:
PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_CBCTRL, /*
& ~PCCBBM_CBCTRL_113X_PCI_INTR, * The TI 1030, TI 1130 and TI 1131 all require another bit
| PCCBBM_CBCTRL_113X_PCI_CSC | * be set to enable PCI routing of interrupts, and then
PCCBBM_CBCTRL_113X_PCI_IRQ_EN, 1); * a bit for each of the CSC and Function interrupts we
* want routed.
*/
PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_CBCTRL,
| PCCBBM_CBCTRL_113X_PCI_INTR |
PCCBBM_CBCTRL_113X_PCI_CSC | PCCBBM_CBCTRL_113X_PCI_IRQ_EN,
1);
PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_DEVCTRL, PCI_MASK_CONFIG(sc->sc_dev, PCCBBR_DEVCTRL,
& ~(PCCBBM_DEVCTRL_INT_SERIAL | & ~(PCCBBM_DEVCTRL_INT_SERIAL |
PCCBBM_DEVCTRL_INT_PCI), 1); PCCBBM_DEVCTRL_INT_PCI), 1);