Add 40 microseconds delay after updating EMAC Mode register as
recommended by Broadcom data sheet.
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3aec794146
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@ -957,6 +957,7 @@ bge_miibus_statchg(device_t dev)
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mac_mode |= BGE_MACMODE_HALF_DUPLEX;
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CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
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DELAY(40);
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CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
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CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
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}
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@ -1434,6 +1435,7 @@ bge_chipinit(struct bge_softc *sc)
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/* Clear the MAC control register */
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CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
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DELAY(40);
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/*
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* Clear the MAC statistics block in the NIC's
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@ -2046,6 +2048,7 @@ bge_blockinit(struct bge_softc *sc)
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/* Turn on DMA, clear stats */
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CSR_WRITE_4(sc, BGE_MAC_MODE, val);
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DELAY(40);
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/* Set misc. local control, enable interrupts on attentions */
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CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
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@ -3752,6 +3755,7 @@ bge_reset(struct bge_softc *sc)
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BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
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CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
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DELAY(40);
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/*
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* The 5704 in TBI mode apparently needs some special
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@ -5148,6 +5152,7 @@ bge_ifmedia_upd_locked(struct ifnet *ifp)
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BGE_SETBIT(sc, BGE_MAC_MODE,
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BGE_MACMODE_HALF_DUPLEX);
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}
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DELAY(40);
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break;
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default:
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return (EINVAL);
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@ -5623,9 +5628,11 @@ bge_link_upd(struct bge_softc *sc)
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if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
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if (!sc->bge_link) {
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sc->bge_link++;
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if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
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if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
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BGE_CLRBIT(sc, BGE_MAC_MODE,
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BGE_MACMODE_TBI_SEND_CFGS);
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DELAY(40);
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}
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CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
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if (bootverbose)
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if_printf(sc->bge_ifp, "link UP\n");
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