Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S
ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
This commit is contained in:
Bill Paul
parent
1569f861d7
commit
9bac70b851
@ -518,6 +518,7 @@ dev/mii/nsphy.c optional miibus
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dev/mii/nsgphy.c optional miibus
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dev/mii/pnphy.c optional miibus
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dev/mii/pnaphy.c optional miibus
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dev/mii/rgephy.c optional miibus
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dev/mii/rlphy.c optional miibus
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dev/mii/ruephy.c optional miibus
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dev/mii/tdkphy.c optional miibus
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@ -91,6 +91,8 @@ oui xxLEVEL1 0x1e0400 Level 1
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/* Don't know what's going on here. */
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oui xxDAVICOM 0x006040 Davicom Semiconductor
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/* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */
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oui xxREALTEK 0x000732
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/*
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* List of known models. Grouped by oui.
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@ -149,6 +151,7 @@ model QUALSEMI QS6612 0x0000 QS6612 10/100 media interface
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/* RealTek Semiconductor PHYs */
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model REALTEK RTL8201L 0x0020 RTL8201L 10/100 media interface
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model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S media interface
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/* Seeq PHYs */
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model xxSEEQ 80220 0x0003 Seeq 80220 10/100 media interface
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483
sys/dev/mii/rgephy.c
Normal file
483
sys/dev/mii/rgephy.c
Normal file
@ -0,0 +1,483 @@
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/*
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* Copyright (c) 2003
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <machine/clock.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/rgephyreg.h>
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#include "miibus_if.h"
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#include <machine/bus.h>
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#include <pci/if_rlreg.h>
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static int rgephy_probe(device_t);
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static int rgephy_attach(device_t);
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static device_method_t rgephy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, rgephy_probe),
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DEVMETHOD(device_attach, rgephy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t rgephy_devclass;
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static driver_t rgephy_driver = {
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"rgephy",
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rgephy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
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static int rgephy_service(struct mii_softc *, struct mii_data *, int);
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static void rgephy_status(struct mii_softc *);
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static int rgephy_mii_phy_auto(struct mii_softc *);
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static void rgephy_reset(struct mii_softc *);
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static void rgephy_loop(struct mii_softc *);
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static void rgephy_load_dspcode(struct mii_softc *);
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static int rgephy_mii_model;
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static int
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rgephy_probe(dev)
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device_t dev;
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{
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struct mii_attach_args *ma;
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ma = device_get_ivars(dev);
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) {
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device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S);
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return(0);
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}
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return(ENXIO);
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}
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static int
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rgephy_attach(dev)
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device_t dev;
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{
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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const char *sep = "";
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sc = device_get_softc(dev);
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = rgephy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOISOLATE;
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mii->mii_instance++;
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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#define PRINT(s) printf("%s%s", sep, s); sep = ", "
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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BMCR_ISO);
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#if 0
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
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BMCR_LOOP|BMCR_S100);
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#endif
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rgephy_mii_model = MII_MODEL(ma->mii_id2);
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rgephy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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sc->mii_capabilities &= ~BMSR_ANEG;
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device_printf(dev, " ");
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mii_add_media(sc);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
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RGEPHY_BMCR_FDX);
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PRINT(", 1000baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
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PRINT("1000baseTX-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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PRINT("auto");
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printf("\n");
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#undef ADD
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#undef PRINT
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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rgephy_service(sc, mii, cmd)
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struct mii_softc *sc;
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struct mii_data *mii;
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int cmd;
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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rgephy_reset(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void) rgephy_mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = RGEPHY_S1000;
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goto setit;
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case IFM_100_TX:
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speed = RGEPHY_S100;
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goto setit;
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case IFM_10_T:
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speed = RGEPHY_S10;
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setit:
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rgephy_loop(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= RGEPHY_BMCR_FDX;
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gig = RGEPHY_1000CTL_AFD;
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} else {
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gig = RGEPHY_1000CTL_AHD;
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}
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
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PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, RGEPHY_MII_BMCR,
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speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
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/*
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* When settning the link manually, one side must
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* be the master and the other the slave. However
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* ifmedia doesn't give us a good way to specify
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* this, so we fake it by using one of the LINK
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* flags. If LINK0 is set, we program the PHY to
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
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} else {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE);
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}
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break;
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#ifdef foo
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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break;
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#endif
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case IFM_100_T4:
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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break;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, RL_GMEDIASTAT);
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if (reg & RL_GMEDIASTAT_LINK)
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break;
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++sc->mii_ticks != 5/*10*/)
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return (0);
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sc->mii_ticks = 0;
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rgephy_mii_phy_auto(sc);
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return (0);
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}
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/* Update the media status. */
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rgephy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* the DSP on the Broadcom PHYs if the media changes.
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*
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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mii_phy_update(sc, cmd);
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rgephy_load_dspcode(sc);
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}
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return (0);
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}
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static void
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rgephy_status(sc)
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struct mii_softc *sc;
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr/*, anlpar*/;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, RL_GMEDIASTAT);
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if (bmsr & RL_GMEDIASTAT_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
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if (bmcr & RGEPHY_BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & RGEPHY_BMCR_AUTOEN) {
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if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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/*
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anlpar = PHY_READ(sc, RL_GMEDIASTAT);
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if (anlpar & RL_GMEDIASTAT_10MBPS)
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mii->mii_media_active |= IFM_10_T;
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if (anlpar & RL_GMEDIASTAT_100MBPS)
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mii->mii_media_active |= IFM_100_TX;
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if (anlpar & RL_GMEDIASTAT_1000MBPS)
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mii->mii_media_active |= IFM_1000_T;
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if (anlpar & RL_GMEDIASTAT_FDX)
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mii->mii_media_active |= IFM_FDX;
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return;
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*/
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}
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bmsr = PHY_READ(sc, RL_GMEDIASTAT);
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if (bmsr & RL_GMEDIASTAT_10MBPS)
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mii->mii_media_active |= IFM_10_T;
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if (bmsr & RL_GMEDIASTAT_100MBPS)
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mii->mii_media_active |= IFM_100_TX;
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if (bmsr & RL_GMEDIASTAT_1000MBPS)
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mii->mii_media_active |= IFM_1000_T;
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if (bmsr & RL_GMEDIASTAT_FDX)
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mii->mii_media_active |= IFM_FDX;
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return;
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}
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||||
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||||
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||||
static int
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rgephy_mii_phy_auto(mii)
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||||
struct mii_softc *mii;
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{
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rgephy_loop(mii);
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rgephy_reset(mii);
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||||
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PHY_WRITE(mii, RGEPHY_MII_ANAR,
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BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_BMCR,
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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DELAY(100);
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||||
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return (EJUSTRETURN);
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||||
}
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||||
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static void
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||||
rgephy_loop(struct mii_softc *sc)
|
||||
{
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||||
u_int32_t bmsr;
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int i;
|
||||
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PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
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DELAY(1000);
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||||
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for (i = 0; i < 15000; i++) {
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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if (!(bmsr & RGEPHY_BMSR_LINK)) {
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#if 0
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device_printf(sc->mii_dev, "looped %d\n", i);
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||||
#endif
|
||||
break;
|
||||
}
|
||||
DELAY(10);
|
||||
}
|
||||
}
|
||||
|
||||
#define PHY_SETBIT(x, y, z) \
|
||||
PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
|
||||
#define PHY_CLRBIT(x, y, z) \
|
||||
PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
|
||||
|
||||
/* Initialize RealTek PHY per datasheet */
|
||||
static void
|
||||
rgephy_load_dspcode(struct mii_softc *sc)
|
||||
{
|
||||
int val;
|
||||
|
||||
PHY_WRITE(sc, 31, 0x0001);
|
||||
PHY_WRITE(sc, 21, 0x1000);
|
||||
PHY_WRITE(sc, 24, 0x65C7);
|
||||
PHY_CLRBIT(sc, 4, 0x0800);
|
||||
val = PHY_READ(sc, 4) & 0xFFF;
|
||||
PHY_WRITE(sc, 4, val);
|
||||
PHY_WRITE(sc, 3, 0x00A1);
|
||||
PHY_WRITE(sc, 2, 0x0008);
|
||||
PHY_WRITE(sc, 1, 0x1020);
|
||||
PHY_WRITE(sc, 0, 0x1000);
|
||||
PHY_SETBIT(sc, 4, 0x0800);
|
||||
PHY_CLRBIT(sc, 4, 0x0800);
|
||||
val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
|
||||
PHY_WRITE(sc, 4, val);
|
||||
PHY_WRITE(sc, 3, 0xFF41);
|
||||
PHY_WRITE(sc, 2, 0xDE60);
|
||||
PHY_WRITE(sc, 1, 0x0140);
|
||||
PHY_WRITE(sc, 0, 0x0077);
|
||||
val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
|
||||
PHY_WRITE(sc, 4, val);
|
||||
PHY_WRITE(sc, 3, 0xDF01);
|
||||
PHY_WRITE(sc, 2, 0xDF20);
|
||||
PHY_WRITE(sc, 1, 0xFF95);
|
||||
PHY_WRITE(sc, 0, 0xFA00);
|
||||
val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
|
||||
PHY_WRITE(sc, 4, val);
|
||||
PHY_WRITE(sc, 3, 0xFF41);
|
||||
PHY_WRITE(sc, 2, 0xDE20);
|
||||
PHY_WRITE(sc, 1, 0x0140);
|
||||
PHY_WRITE(sc, 0, 0x00BB);
|
||||
val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
|
||||
PHY_WRITE(sc, 4, val);
|
||||
PHY_WRITE(sc, 3, 0xDF01);
|
||||
PHY_WRITE(sc, 2, 0xDF20);
|
||||
PHY_WRITE(sc, 1, 0xFF95);
|
||||
PHY_WRITE(sc, 0, 0xBF00);
|
||||
PHY_SETBIT(sc, 4, 0x0800);
|
||||
PHY_CLRBIT(sc, 4, 0x0800);
|
||||
PHY_WRITE(sc, 31, 0x0000);
|
||||
|
||||
DELAY(40);
|
||||
}
|
||||
|
||||
static void
|
||||
rgephy_reset(struct mii_softc *sc)
|
||||
{
|
||||
mii_phy_reset(sc);
|
||||
DELAY(1000);
|
||||
rgephy_load_dspcode(sc);
|
||||
|
||||
return;
|
||||
}
|
||||
142
sys/dev/mii/rgephyreg.h
Normal file
142
sys/dev/mii/rgephyreg.h
Normal file
@ -0,0 +1,142 @@
|
||||
/*
|
||||
* Copyright (c) 2003
|
||||
* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_RGEPHYREG_H_
|
||||
#define _DEV_MII_RGEPHYREG_H_
|
||||
|
||||
/*
|
||||
* RealTek 8169S/8110S gigE PHY registers
|
||||
*/
|
||||
|
||||
#define RGEPHY_MII_BMCR 0x00
|
||||
#define RGEPHY_BMCR_RESET 0x8000
|
||||
#define RGEPHY_BMCR_LOOP 0x4000
|
||||
#define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
|
||||
#define RGEPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define RGEPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define RGEPHY_BMCR_ISO 0x0400 /* Isolate */
|
||||
#define RGEPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define RGEPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define RGEPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
|
||||
#define RGEPHY_S1000 RGEPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define RGEPHY_S100 RGEPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define RGEPHY_S10 0 /* 10mbps */
|
||||
|
||||
#define RGEPHY_MII_BMSR 0x01
|
||||
#define RGEPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
|
||||
#define RGEPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
|
||||
#define RGEPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
|
||||
#define RGEPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
|
||||
#define RGEPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
|
||||
#define RGEPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
|
||||
#define RGEPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
|
||||
#define RGEPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
|
||||
#define RGEPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
|
||||
#define RGEPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
|
||||
#define RGEPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
|
||||
#define RGEPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
|
||||
#define RGEPHY_BMSR_LINK 0x0004 /* Link status */
|
||||
#define RGEPHY_BMSR_JABBER 0x0002 /* Jabber detected */
|
||||
#define RGEPHY_BMSR_EXT 0x0001 /* Extended capability */
|
||||
|
||||
#define RGEPHY_MII_ANAR 0x04
|
||||
#define RGEPHY_ANAR_NP 0x8000 /* Next page */
|
||||
#define RGEPHY_ANAR_RF 0x2000 /* Remote fault */
|
||||
#define RGEPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define RGEPHY_ANAR_PC 0x0400 /* Pause capable */
|
||||
#define RGEPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
|
||||
#define RGEPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
|
||||
#define RGEPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
|
||||
#define RGEPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
|
||||
#define RGEPHY_ANAR_10 0x0020 /* local device supports 10bT */
|
||||
#define RGEPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define RGEPHY_MII_ANLPAR 0x05
|
||||
#define RGEPHY_ANLPAR_NP 0x8000 /* Next page */
|
||||
#define RGEPHY_ANLPAR_RF 0x2000 /* Remote fault */
|
||||
#define RGEPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define RGEPHY_ANLPAR_PC 0x0400 /* Pause capable */
|
||||
#define RGEPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
|
||||
#define RGEPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
|
||||
#define RGEPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
|
||||
#define RGEPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
|
||||
#define RGEPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
|
||||
#define RGEPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define RGEPHY_SEL_TYPE 0x0001 /* ethernet */
|
||||
|
||||
#define RGEPHY_MII_ANER 0x06
|
||||
#define RGEPHY_ANER_PDF 0x0010 /* Parallel detection fault */
|
||||
#define RGEPHY_ANER_LPNP 0x0008 /* Link partner can next page */
|
||||
#define RGEPHY_ANER_NP 0x0004 /* Local PHY can next page */
|
||||
#define RGEPHY_ANER_RX 0x0002 /* Next page received */
|
||||
#define RGEPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
|
||||
|
||||
#define RGEPHY_MII_NEXTP 0x07 /* Next page */
|
||||
|
||||
#define RGEPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
|
||||
|
||||
#define RGEPHY_MII_1000CTL 0x09 /* 1000baseT control */
|
||||
#define RGEPHY_1000CTL_TST 0xE000 /* test modes */
|
||||
#define RGEPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
|
||||
#define RGEPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
|
||||
#define RGEPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
|
||||
#define RGEPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
|
||||
#define RGEPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
|
||||
|
||||
#define RGEPHY_TEST_TX_JITTER 0x2000
|
||||
#define RGEPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
|
||||
#define RGEPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
|
||||
#define RGEPHY_TEST_TX_DISTORTION 0x8000
|
||||
|
||||
#define RGEPHY_MII_1000STS 0x0A /* 1000baseT status */
|
||||
#define RGEPHY_1000STS_MSF 0x8000 /* Master/slave fault */
|
||||
#define RGEPHY_1000STS_MSR 0x4000 /* Master/slave result */
|
||||
#define RGEPHY_1000STS_LRS 0x2000 /* Local receiver status */
|
||||
#define RGEPHY_1000STS_RRS 0x1000 /* Remote receiver status */
|
||||
#define RGEPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
|
||||
#define RGEPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
|
||||
#define RGEPHY_1000STS_IEC 0x00FF /* Idle error count */
|
||||
|
||||
#define RGEPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define RGEPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
|
||||
#define RGEPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
|
||||
#define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
|
||||
#define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
|
||||
|
||||
|
||||
|
||||
#endif /* _DEV_RGEPHY_MIIREG_H_ */
|
||||
@ -393,6 +393,13 @@ re_gmii_readreg(dev, phy, reg)
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
/* Let the rgephy driver read the GMEDIASTAT register */
|
||||
|
||||
if (reg == RL_GMEDIASTAT) {
|
||||
rval = CSR_READ_1(sc, RL_GMEDIASTAT);
|
||||
return(rval);
|
||||
}
|
||||
|
||||
CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
|
||||
DELAY(1000);
|
||||
|
||||
@ -423,7 +430,7 @@ re_gmii_writereg(dev, phy, reg, data)
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
|
||||
(data | RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
|
||||
(data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
|
||||
DELAY(1000);
|
||||
|
||||
for (i = 0; i < RL_TIMEOUT; i++) {
|
||||
@ -1148,6 +1155,7 @@ re_attach(dev)
|
||||
|
||||
/* Reset the adapter. */
|
||||
re_reset(sc);
|
||||
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
|
||||
sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
|
||||
re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
|
||||
if (re_did != 0x8129)
|
||||
@ -1162,6 +1170,8 @@ re_attach(dev)
|
||||
eaddr[(i * 2) + 1] = as[i] >> 8;
|
||||
}
|
||||
|
||||
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
|
||||
|
||||
/*
|
||||
* A RealTek chip was detected. Inform the world.
|
||||
*/
|
||||
@ -1780,6 +1790,11 @@ re_intr(arg)
|
||||
RL_LOCK(sc);
|
||||
ifp = &sc->arpcom.ac_if;
|
||||
|
||||
if (!(ifp->if_flags & IFF_UP)) {
|
||||
RL_UNLOCK(sc);
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef DEVICE_POLLING
|
||||
if (ifp->if_flags & IFF_POLLING)
|
||||
goto done;
|
||||
|
||||
@ -7,7 +7,7 @@ SRCS= mii.c mii_physubr.c ukphy.c ukphy_subr.c bus_if.h pci_if.h
|
||||
SRCS+= miibus_if.h miidevs.h device_if.h miibus_if.c e1000phy.c exphy.c nsphy.c
|
||||
SRCS+= mlphy.c tlphy.c rlphy.c amphy.c dcphy.c pnphy.c inphy.c tdkphy.c
|
||||
SRCS+= bmtphy.c brgphy.c xmphy.c pnaphy.c lxtphy.c qsphy.c acphy.c nsgphy.c
|
||||
SRCS+= ruephy.c
|
||||
SRCS+= rgephy.c ruephy.c
|
||||
|
||||
EXPORT_SYMS= mii_mediachg \
|
||||
mii_tick \
|
||||
|
||||
@ -1105,6 +1105,7 @@ rl_attach(dev)
|
||||
ifp->if_watchdog = rl_watchdog;
|
||||
ifp->if_init = rl_init;
|
||||
ifp->if_baudrate = 10000000;
|
||||
ifp->if_capabilities = IFCAP_VLAN_MTU;
|
||||
ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
|
||||
|
||||
callout_handle_init(&sc->rl_stat_ch);
|
||||
|
||||
@ -381,7 +381,7 @@
|
||||
#define RL_GMEDIASTAT_LINK 0x02 /* link up */
|
||||
#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
|
||||
#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
|
||||
#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */
|
||||
#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
|
||||
#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
|
||||
#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
|
||||
#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user