Move io_apic_{read,write} from apic_ipl.s (where they do not belong) into
mpapic.c. This gives us the benefit of C type checking. These functions are not called in any critical paths and are not used by the interrupt routines.
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@ -58,10 +58,6 @@ extern volatile u_int checkstate_need_ast;
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extern volatile u_int resched_cpus;
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extern void (*cpustop_restartfunc) __P((void));
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/* functions in apic_ipl.s */
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in mp_machdep.c */
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extern int bsp_apic_ready;
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extern int mp_ncpus;
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@ -146,6 +142,9 @@ int ext_int_setup __P((int, int));
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void set_apic_timer __P((int));
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int read_apic_timer __P((void));
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void u_sleep __P((int));
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in init_smp.c */
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extern int invltlb_ok;
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@ -758,3 +758,26 @@ u_sleep(int count)
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while (read_apic_timer())
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/* spin */ ;
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}
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/*
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* IOAPIC access helper functions.
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*/
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u_int
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io_apic_read(int idx, int reg)
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{
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volatile ioapic_t *apic;
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apic = ioapic[idx];
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apic->ioregsel = reg;
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return apic->iowin;
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}
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void
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io_apic_write(int idx, int reg, u_int value)
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{
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volatile ioapic_t *apic;
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apic = ioapic[idx];
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apic->ioregsel = reg;
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apic->iowin = value;
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}
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@ -58,10 +58,6 @@ extern volatile u_int checkstate_need_ast;
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extern volatile u_int resched_cpus;
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extern void (*cpustop_restartfunc) __P((void));
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/* functions in apic_ipl.s */
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in mp_machdep.c */
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extern int bsp_apic_ready;
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extern int mp_ncpus;
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@ -146,6 +142,9 @@ int ext_int_setup __P((int, int));
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void set_apic_timer __P((int));
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int read_apic_timer __P((void));
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void u_sleep __P((int));
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in init_smp.c */
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extern int invltlb_ok;
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@ -130,32 +130,3 @@ ENTRY(INTRDIS)
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IMASK_UNLOCK /* exit critical reg */
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popfl /* restore old state of EI flag */
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ret
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/******************************************************************************
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*
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*/
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/*
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* u_int io_apic_write(int apic, int select);
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*/
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ENTRY(io_apic_read)
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movl 4(%esp), %ecx /* APIC # */
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movl _ioapic, %eax
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movl (%eax,%ecx,4), %edx /* APIC base register address */
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movl 8(%esp), %eax /* target register index */
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movl %eax, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the APIC register data */
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ret /* %eax = register value */
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/*
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* void io_apic_write(int apic, int select, int value);
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*/
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ENTRY(io_apic_write)
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movl 4(%esp), %ecx /* APIC # */
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movl _ioapic, %eax
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movl (%eax,%ecx,4), %edx /* APIC base register address */
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movl 8(%esp), %eax /* target register index */
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movl %eax, (%edx) /* write the target register index */
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movl 12(%esp), %eax /* target register value */
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movl %eax, 16(%edx) /* write the APIC register data */
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ret /* %eax = void */
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@ -58,10 +58,6 @@ extern volatile u_int checkstate_need_ast;
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extern volatile u_int resched_cpus;
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extern void (*cpustop_restartfunc) __P((void));
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/* functions in apic_ipl.s */
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in mp_machdep.c */
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extern int bsp_apic_ready;
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extern int mp_ncpus;
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@ -146,6 +142,9 @@ int ext_int_setup __P((int, int));
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void set_apic_timer __P((int));
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int read_apic_timer __P((void));
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void u_sleep __P((int));
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u_int io_apic_read __P((int, int));
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void io_apic_write __P((int, int, u_int));
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/* global data in init_smp.c */
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extern int invltlb_ok;
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