d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Set the 'FR' bit in the status register for N32 kernels.

Browse Source 
This permits N32 hard-float binaries to use 64-bit floating point
registers (which is what N32 binaries expect) matching the N64 ABI.

Reviewed by:	imp, jmallett
Sponsored by:	DARPA / AFRL
Differential Revision:	https://reviews.freebsd.org/D13830
This commit is contained in:
John Baldwin 2018-01-10 21:08:43 +00:00
parent ed595433c6
commit a27a25f759
4 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sys/mips/mips/exception.S
View File

@ -1110,7 +1110,7 @@ NESTED(MipsFPTrap, CALLFRAME_SIZ, ra)
REG_S ra, CALLFRAME_RA(sp)
.mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
#if defined(__mips_n64)
#if defined(__mips_n32) || defined(__mips_n64)
or t1, t0, MIPS_SR_COP_1_BIT | MIPS_SR_FR
#else
or t1, t0, MIPS_SR_COP_1_BIT

5
sys/mips/mips/locore.S
View File

@ -117,8 +117,11 @@ VECTOR(_locore, unknown)
* Enable FPU
*/
li t1, MIPS_SR_COP_1_BIT
#if defined(__mips_n32) || defined(__mips_n64)
or t1, MIPS_SR_FR
#endif
#ifdef __mips_n64
or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_FR
or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX
#endif
#endif
/*

6
sys/mips/mips/swtch.S
View File

@ -416,7 +416,7 @@ LEAF(MipsSwitchFPState)
.set hardfloat
mfc0 t1, MIPS_COP_0_STATUS # Save old SR
HAZARD_DELAY
#if defined(__mips_n64)
#if defined(__mips_n32) || defined(__mips_n64)
or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR # enable the coprocessor
#else
or t0, t1, MIPS_SR_COP_1_BIT # enable the coprocessor
@ -546,7 +546,7 @@ LEAF(MipsFPID)
.set hardfloat
mfc0 t1, MIPS_COP_0_STATUS # Save the status register.
HAZARD_DELAY
#if defined(__mips_n64)
#if defined(__mips_n32) || defined(__mips_n64)
or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR
#else
or t0, t1, MIPS_SR_COP_1_BIT
@ -585,7 +585,7 @@ LEAF(MipsSaveCurFPState)
PTR_L a0, TD_PCB(a0) # get pointer to pcb for thread
mfc0 t1, MIPS_COP_0_STATUS # Disable interrupts and
HAZARD_DELAY
#if defined(__mips_n64)
#if defined(__mips_n32) || defined(__mips_n64)
or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR # enable the coprocessor
#else
or t0, t1, MIPS_SR_COP_1_BIT # enable the coprocessor

2
sys/mips/mips/trap.c
View File

@ -983,7 +983,7 @@ dofault:
addr = trapframe->pc;
MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
PCPU_SET(fpcurthread, td);
#if defined(__mips_n64)
#if defined(__mips_n32) || defined(__mips_n64)
td->td_frame->sr |= MIPS_SR_COP_1_BIT | MIPS_SR_FR;
#else
td->td_frame->sr |= MIPS_SR_COP_1_BIT;