d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- Add support for Intel Apollo Lake and Bay Trail eMMC controllers.

Browse Source 
Besides slots always having non-removable media, these HCIs require
  a custom hardware reset sequence after power-up.
- Flesh out the support for Intel Braswell eMMC controllers further.
  Apart from also requiring said reset code, the timeout clock needs to
  be hardcoded to 1 MHz for these.
  Both the special reset and timeout clock handlings are implemented as
  global sdhci(4) quirks as the same treatment will be necessary for
  Intel eMMC controllers attached via ACPI (once sdhci(4) grows such a
  front-end).
- In sdhci_init_slot(), use the right capability field for determining
  the announced bus width based on MMC_CAP_*_BIT_DATA.
- Correct inverted sdhci_pci_softc member comments added in r276469. [1]

Submitted by:	Anton Yuzhaninov [1]
MFC after:	5 days
This commit is contained in:
Marius Strobl 2017-01-09 17:07:13 +00:00
parent d119f637fc
commit a2832f9fce
3 changed files with 37 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
sys/dev/sdhci/sdhci.c
View File

@ -376,6 +376,13 @@ sdhci_set_power(struct sdhci_slot *slot, u_char power)
/* Turn on the power. */
pwr |= SDHCI_POWER_ON;
WR1(slot, SDHCI_POWER_CONTROL, pwr);
if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
DELAY(10);
WR1(slot, SDHCI_POWER_CONTROL, pwr);
DELAY(300);
}
}
static void
@ -622,9 +629,11 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
device_printf(dev, "Hardware doesn't specify base clock "
"frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
}
/* Calculate timeout clock frequency. */
/* Calculate/set timeout clock frequency. */
if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
slot->timeout_clk = slot->max_clk / 1000;
} else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
slot->timeout_clk = 1000;
} else {
slot->timeout_clk =
(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
@ -668,6 +677,8 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
slot->opt &= ~SDHCI_HAVE_DMA;
if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
slot->opt |= SDHCI_HAVE_DMA;
if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
slot->opt |= SDHCI_NON_REMOVABLE;
/*
* Use platform-provided transfer backend
@ -680,8 +691,9 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
slot_printf(slot, "%uMHz%s %s%s%s%s %s\n",
slot->max_clk / 1000000,
(caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
(caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
((caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
(slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" :
"1bit"),
(caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
(caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
(caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",

8
sys/dev/sdhci/sdhci.h
View File

@ -66,7 +66,13 @@
/* Alternate clock source is required when supplying a 400 KHz clock. */
#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1<<16)
/* Card insert/remove interrupts don't work, polling required. */
#define SDHCI_QUIRK_POLL_CARD_PRESENT (1<<17)
#define SDHCI_QUIRK_POLL_CARD_PRESENT (1<<17)
/* All controller slots are non-removable. */
#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1<<18)
/* Issue custom Intel controller reset sequence after power-up. */
#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1<<19)
/* Data timeout is invalid, use 1 MHz clock instead. */
#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1<<20)
/*
* Controller registers

19
sys/dev/sdhci/sdhci_pci.c
View File

@ -107,8 +107,19 @@ static const struct sdhci_device {
SDHCI_QUIRK_RESET_AFTER_REQUEST },
{ 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
{ 0x22948086, 0xffff, "Intel Braswell Storage Cluster Control MMC Port",
0 },
{ 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
SDHCI_QUIRK_INTEL_POWER_UP_RESET },
{ 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
SDHCI_QUIRK_INTEL_POWER_UP_RESET },
{ 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
SDHCI_QUIRK_INTEL_POWER_UP_RESET },
{ 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
SDHCI_QUIRK_INTEL_POWER_UP_RESET },
{ 0, 0xffff, NULL,
0 }
};
@ -121,8 +132,8 @@ struct sdhci_pci_softc {
int num_slots; /* Number of slots on this controller */
struct sdhci_slot slots[6];
struct resource *mem_res[6]; /* Memory resource */
uint8_t cfg_freq; /* Saved mode */
uint8_t cfg_mode; /* Saved frequency */
uint8_t cfg_freq; /* Saved frequency */
uint8_t cfg_mode; /* Saved mode */
};
static int sdhci_enable_msi = 1;