Disable the use of the quantum cache in the GICv3 ITS
This uses UMA to allocate space. It causes issues when there are multiple ITS devices in the system where interrupts are not allocated from a low address on some interrupt controllers. Disabling the quantum cache fixes this on the Neoverse N1 SDP. MFC after: 2 weeks Sponsored by: DARPA, AFRL
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@ -800,7 +800,7 @@ gicv3_its_attach(device_t dev)
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* system.
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*/
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sc->sc_irq_alloc = vmem_create("GICv3 ITS IRQs", 0,
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gicv3_get_nirqs(dev), 1, 1, M_FIRSTFIT | M_WAITOK);
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gicv3_get_nirqs(dev), 1, 0, M_FIRSTFIT | M_WAITOK);
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sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length,
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M_GICV3_ITS, M_WAITOK | M_ZERO);
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