Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also
be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
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@ -443,7 +443,6 @@ SMP opt_global.h
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MSGBUF_SIZE opt_msgbuf.h
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# PCI related options
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PCI_ENABLE_IO_MODES opt_pci.h
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PCI_ALLOW_UNSUPPORTED_IO_RANGE opt_pci.h
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# NFS options
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@ -41,6 +41,7 @@
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/queue.h>
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#include <sys/sysctl.h>
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#include <sys/types.h>
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#include <vm/vm.h>
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@ -163,6 +164,17 @@ struct devlist pci_devq;
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u_int32_t pci_generation;
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u_int32_t pci_numdevs = 0;
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/* sysctl vars */
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SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
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int pci_enable_io_modes = 1;
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TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes);
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SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
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&pci_enable_io_modes, 1,
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"Enable I/O and memory bits in the config register. Some BIOSes do not\n\
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enable these bits correctly. We'd like to do this all the time, but there\n\
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are some peripherals that this causes problems with.");
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/* Find a device_t by bus/slot/function */
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device_t
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@ -663,9 +675,7 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg,
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int32_t testval;
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#ifdef PCI_ENABLE_IO_MODES
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u_int16_t cmd;
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#endif
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int type;
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map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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@ -707,25 +717,24 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg,
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* peripherals respond oddly to having these bits
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* enabled. Leave them alone by default.
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*/
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#ifdef PCI_ENABLE_IO_MODES
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/* Turn on resources that have been left off by a lazy BIOS */
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_PORTEN;
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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if (pci_enable_io_modes) {
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/* Turn on resources that have been left off by a lazy BIOS */
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_PORTEN;
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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}
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_MEMEN;
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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}
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} else {
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
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return (1);
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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return (1);
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}
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_MEMEN;
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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}
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#else
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
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return (1);
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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return (1);
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#endif
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resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1,
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(1 << ln2size));
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@ -1186,6 +1195,12 @@ pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
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struct resource_list *rl = &dinfo->resources;
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pcicfgregs *cfg = &dinfo->cfg;
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/*
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* You can share PCI interrupts.
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*/
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if (type == SYS_RES_IRQ)
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flags |= RF_SHAREABLE;
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/*
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* Perform lazy resource allocation
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*
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