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When sending cache flushing IPIs, don't try to IPI the triggering CPU

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itself; this causes undefined behaviour on UltraSPARCs. In particular,
the interrupt packet data words will not necessarily be delivered
correctly, which would result in a crash.
This bug also caused the cache-flushing work to be done twice on the
triggering CPU (when it did not cause crashes).

Reviewed by:	jake
This commit is contained in:
Thomas Moestl 2002-07-12 16:26:49 +00:00
parent 737d08f31e
commit a935ed4fae
1 changed files with 4 additions and 4 deletions
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8
sys/sparc64/include/smp.h
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@ -116,8 +116,8 @@ ipi_dcache_page_inval(vm_offset_t pa)
ica = &ipi_cache_args;
ica->ica_mask = all_cpus;
ica->ica_pa = pa;
cpu_ipi_selected(all_cpus, 0, (u_long)tl_ipi_dcache_page_inval,
(u_long)ica);
cpu_ipi_selected(PCPU_GET(other_cpus), 0,
(u_long)tl_ipi_dcache_page_inval, (u_long)ica);
return (&ica->ica_mask);
}
@ -131,8 +131,8 @@ ipi_icache_page_inval(vm_offset_t pa)
ica = &ipi_cache_args;
ica->ica_mask = all_cpus;
ica->ica_pa = pa;
cpu_ipi_selected(all_cpus, 0, (u_long)tl_ipi_icache_page_inval,
(u_long)ica);
cpu_ipi_selected(PCPU_GET(other_cpus), 0,
(u_long)tl_ipi_icache_page_inval, (u_long)ica);
return (&ica->ica_mask);
}