Add support for the memory-mapped PCI Express configuration mechanism. This
actually is a property of the northbridge and applies to all PCI/PCI-X/PCIe devices in the system, though only PCIe devices will respond to registers higher than 256. This uses per-CPU pools of temporary mappings so that the whole 256MB of configuration space doesn't have to be mapped all at once. While the sf_buf API was considered for this, the fact that it requires sleep locks and can return failure made it unsuitable for this use. For now only the Intel Grantsdale and Lindenhurst (925 and 752x) chipsets are supported. Since there doesn't appear to be a compatible way to determine northbridge support, new chipsets will have to be explicitely added in the future.
This commit is contained in:
Scott Long
parent
6550c6569b
commit
aa2ea23220
@ -34,24 +34,54 @@ __FBSDID("$FreeBSD$");
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/pc/bios.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_extern.h>
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#include <vm/pmap.h>
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#include <machine/pmap.h>
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#define PRVERB(a) do { \
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if (bootverbose) \
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printf a ; \
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} while(0)
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#define PCIE_CACHE 8
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struct pcie_cfg_elem {
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TAILQ_ENTRY(pcie_cfg_elem) elem;
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vm_offset_t vapage;
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vm_paddr_t papage;
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};
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enum {
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CFGMECH_NONE = 0,
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CFGMECH_1,
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CFGMECH_2,
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CFGMECH_PCIE,
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};
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static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
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static uint32_t pciebar;
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static int cfgmech;
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static int devmax;
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static struct mtx pcicfg_mtx;
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static struct mtx pcicfg_mtx;
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static int pciereg_cfgopen(void);
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static int pciereg_cfgread(int bus, int slot, int func, int reg,
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int bytes);
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static void pciereg_cfgwrite(int bus, int slot, int func, int reg,
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int data, int bytes);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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@ -96,6 +126,7 @@ int
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pci_cfgregopen(void)
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{
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static int opened = 0;
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u_int16_t vid, did;
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u_int16_t v;
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if (opened)
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@ -114,6 +145,24 @@ pci_cfgregopen(void)
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/* $PIR requires PCI BIOS 2.10 or greater. */
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if (v >= 0x0210)
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pci_pir_open();
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/*
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* Grope around in the PCI config space to see if this is a
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* chipset that is capable of doing memory-mapped config cycles.
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* This also implies that it can do PCIe extended config cycles.
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*/
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/* Check for the Intel 7520 and 925 chipsets */
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vid = pci_cfgregread(0, 0, 0, 0x0, 2);
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did = pci_cfgregread(0, 0, 0, 0x2, 2);
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if ((vid == 0x8086) && (did == 0x3590)) {
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pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
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pciereg_cfgopen();
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} else if ((vid == 0x8086) && (did == 0x2580)) {
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pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
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pciereg_cfgopen();
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}
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return(1);
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}
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@ -165,13 +214,13 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (unsigned) bytes <= 4
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&& (reg & (bytes - 1)) == 0) {
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switch (cfgmech) {
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case 1:
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case CFGMECH_1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case 2:
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case CFGMECH_2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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@ -186,10 +235,10 @@ static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case 1:
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case CFGMECH_1:
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outl(CONF1_ADDR_PORT, 0);
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break;
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case 2:
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case CFGMECH_2:
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outb(CONF2_ENABLE_PORT, 0);
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outb(CONF2_FORWARD_PORT, 0);
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break;
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@ -202,6 +251,11 @@ pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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int data = -1;
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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data = pciereg_cfgread(bus, slot, func, reg, bytes);
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return (data);
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -227,6 +281,11 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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return;
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -309,7 +368,7 @@ pcireg_cfgopen(void)
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = 1;
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cfgmech = CFGMECH_1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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@ -349,7 +408,7 @@ pcireg_cfgopen(void)
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = 2;
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cfgmech = CFGMECH_2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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@ -369,8 +428,152 @@ pcireg_cfgopen(void)
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}
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}
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cfgmech = 0;
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cfgmech = CFGMECH_NONE;
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devmax = 0;
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return (cfgmech);
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}
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static int
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pciereg_cfgopen(void)
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{
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struct pcie_cfg_list *pcielist;
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struct pcie_cfg_elem *pcie_array, *elem;
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#ifdef SMP
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struct pcpu *pc;
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#endif
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vm_offset_t va;
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int i;
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if (bootverbose)
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printf("Setting up PCIe mappings for BAR 0x%x\n", pciebar);
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#ifdef SMP
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SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
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#endif
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{
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pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
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M_DEVBUF, M_NOWAIT);
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if (pcie_array == NULL)
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return (0);
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va = kmem_alloc_nofault(kernel_map, PCIE_CACHE * PAGE_SIZE);
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if (va == 0) {
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free(pcie_array, M_DEVBUF);
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return (0);
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}
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#ifdef SMP
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pcielist = &pcie_list[pc->pc_cpuid];
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#else
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pcielist = &pcie_list[0];
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#endif
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TAILQ_INIT(pcielist);
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for (i = 0; i < PCIE_CACHE; i++) {
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elem = &pcie_array[i];
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elem->vapage = va + (i * PAGE_SIZE);
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elem->papage = 0;
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TAILQ_INSERT_HEAD(pcielist, elem, elem);
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}
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}
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cfgmech = CFGMECH_PCIE;
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devmax = 32;
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return (1);
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}
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#define PCIE_PADDR(bar, reg, bus, slot, func) \
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((bar) | \
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(((bus) & 0xff) << 20) | \
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(((slot) & 0x1f) << 15) | \
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(((func) & 0x7) << 12) | \
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((reg) & 0xfff))
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/*
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* Find an element in the cache that matches the physical page desired, or
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* create a new mapping from the least recently used element.
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* A very simple LRU algorithm is used here, does it need to be more
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* efficient?
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*/
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static __inline struct pcie_cfg_elem *
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pciereg_findelem(vm_paddr_t papage)
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{
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struct pcie_cfg_list *pcielist;
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struct pcie_cfg_elem *elem;
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critical_enter();
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pcielist = &pcie_list[PCPU_GET(cpuid)];
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TAILQ_FOREACH(elem, pcielist, elem) {
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if (elem->papage == papage)
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break;
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}
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if (elem == NULL) {
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elem = TAILQ_LAST(pcielist, pcie_cfg_list);
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if (elem->papage != 0) {
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pmap_kremove(elem->vapage);
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invlpg(elem->vapage);
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}
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pmap_kenter(elem->vapage, papage);
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elem->papage = papage;
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}
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if (elem != TAILQ_FIRST(pcielist)) {
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TAILQ_REMOVE(pcielist, elem, elem);
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TAILQ_INSERT_HEAD(pcielist, elem, elem);
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}
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critical_exit();
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return (elem);
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}
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static int
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pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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struct pcie_cfg_elem *elem;
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volatile vm_offset_t va;
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vm_paddr_t pa, papage;
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pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
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papage = pa & ~PAGE_MASK;
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elem = pciereg_findelem(papage);
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va = elem->vapage | (pa & PAGE_MASK);
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switch (bytes) {
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case 4:
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return (*(volatile uint32_t *)(va));
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case 2:
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return (*(volatile uint16_t *)(va));
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case 1:
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return (*(volatile uint8_t *)(va));
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default:
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panic("pciereg_cfgread: invalid width");
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}
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}
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static void
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pciereg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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struct pcie_cfg_elem *elem;
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volatile vm_offset_t va;
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vm_paddr_t pa, papage;
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pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
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papage = pa & ~PAGE_MASK;
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elem = pciereg_findelem(papage);
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va = elem->vapage | (pa & PAGE_MASK);
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switch (bytes) {
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case 4:
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*(volatile uint32_t *)(va) = data;
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break;
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case 2:
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*(volatile uint16_t *)(va) = data;
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break;
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case 1:
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*(volatile uint8_t *)(va) = data;
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break;
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default:
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panic("pciereg_cfgwrite: invalid width");
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}
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}
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