diff --git a/sys/arm64/rockchip/rk3328_codec.c b/sys/arm64/rockchip/rk3328_codec.c
new file mode 100644
index 000000000000..940b3b8bb9e8
--- /dev/null
+++ b/sys/arm64/rockchip/rk3328_codec.c
@@ -0,0 +1,593 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
+ * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/resource.h>
+#include <machine/bus.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/syscon/syscon.h>
+
+#include "syscon_if.h"
+
+#include "opt_snd.h"
+#include <dev/sound/pcm/sound.h>
+#include <dev/sound/fdt/audio_dai.h>
+#include "audio_dai_if.h"
+#include "mixer_if.h"
+
+#define	RKCODEC_MIXER_DEVS		(1 << SOUND_MIXER_VOLUME)
+
+#define	GRF_SOC_CON2			0x0408
+#define	 SOC_CON2_I2S_ACODEC_EN			(1 << 14)
+#define	 SOC_CON2_I2S_ACODEC_EN_MASK		((1 << 14) << 16)
+#define	GRF_SOC_CON10			0x0428
+#define	 SOC_CON10_GPIOMUT			(1 << 1)
+#define	 SOC_CON10_GPIOMUT_MASK			((1 << 1) << 16)
+#define	 SOC_CON10_GPIOMUT_EN			(1 << 0)
+#define	 SOC_CON10_GPIOMUT_EN_MASK			((1 << 0) << 16)
+
+#define	CODEC_RESET			0x00
+#define	 RESET_DIG_CORE_RST			(1 << 1)
+#define	 RESET_SYS_RST				(1 << 0)
+#define	CODEC_DAC_INIT_CTRL1		0x0c
+#define	 DAC_INIT_CTRL1_DIRECTION_IN		(0 << 5)
+#define	 DAC_INIT_CTRL1_DIRECTION_OUT		(1 << 5)
+#define	 DAC_INIT_CTRL1_DAC_I2S_MODE_SLAVE	(0 << 4)
+#define	 DAC_INIT_CTRL1_DAC_I2S_MODE_MASTER	(1 << 4)
+#define	 DAC_INIT_CTRL1_MODE_MASK		(3 << 4)
+#define	CODEC_DAC_INIT_CTRL2		0x10
+#define	 DAC_INIT_CTRL2_DAC_VDL_16BITS		(0 << 5)
+#define	 DAC_INIT_CTRL2_DAC_VDL_20BITS		(1 << 5)
+#define	 DAC_INIT_CTRL2_DAC_VDL_24BITS		(2 << 5)
+#define	 DAC_INIT_CTRL2_DAC_VDL_32BITS		(3 << 5)
+#define	 DAC_INIT_CTRL2_DAC_VDL_MASK		(3 << 5)
+#define	 DAC_INIT_CTRL2_DAC_MODE_RJM		(0 << 3)
+#define	 DAC_INIT_CTRL2_DAC_MODE_LJM		(1 << 3)
+#define	 DAC_INIT_CTRL2_DAC_MODE_I2S		(2 << 3)
+#define	 DAC_INIT_CTRL2_DAC_MODE_PCM		(3 << 3)
+#define	 DAC_INIT_CTRL2_DAC_MODE_MASK		(3 << 3)
+#define	CODEC_DAC_INIT_CTRL3		0x14
+#define	 DAC_INIT_CTRL3_WL_16BITS		(0 << 2)
+#define	 DAC_INIT_CTRL3_WL_20BITS		(1 << 2)
+#define	 DAC_INIT_CTRL3_WL_24BITS		(2 << 2)
+#define	 DAC_INIT_CTRL3_WL_32BITS		(3 << 2)
+#define	 DAC_INIT_CTRL3_WL_MASK			(3 << 2)
+#define	 DAC_INIT_CTRL3_RST_MASK		(1 << 1)
+#define	 DAC_INIT_CTRL3_RST_DIS			(1 << 1)
+#define	 DAC_INIT_CTRL3_DAC_BCP_REVERSAL	(1 << 0)
+#define	 DAC_INIT_CTRL3_DAC_BCP_NORMAL		(0 << 0)
+#define	 DAC_INIT_CTRL3_DAC_BCP_MASK		(1 << 0)
+#define	CODEC_DAC_PRECHARGE_CTRL	0x88
+#define	 DAC_PRECHARGE_CTRL_DAC_CHARGE_PRECHARGE	(1 << 7)
+#define	 DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_I	(1 << 0)
+#define	 DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_ALL	(0x7f)
+#define	CODEC_DAC_PWR_CTRL		0x8c
+#define	 DAC_PWR_CTRL_DAC_PWR			(1 << 6)
+#define	 DAC_PWR_CTRL_DACL_PATH_REFV		(1 << 5)
+#define	 DAC_PWR_CTRL_HPOUTL_ZERO_CROSSING	(1 << 4)
+#define	 DAC_PWR_CTRL_DACR_PATH_REFV		(1 << 1)
+#define	 DAC_PWR_CTRL_HPOUTR_ZERO_CROSSING	(1 << 0)
+#define	CODEC_DAC_CLK_CTRL		0x90
+#define	 DAC_CLK_CTRL_DACL_REFV_ON		(1 << 7)
+#define	 DAC_CLK_CTRL_DACL_CLK_ON		(1 << 6)
+#define	 DAC_CLK_CTRL_DACL_ON			(1 << 5)
+#define	 DAC_CLK_CTRL_DACL_INIT_ON		(1 << 4)
+#define	 DAC_CLK_CTRL_DACR_REFV_ON		(1 << 3)
+#define	 DAC_CLK_CTRL_DACR_CLK_ON		(1 << 2)
+#define	 DAC_CLK_CTRL_DACR_ON			(1 << 1)
+#define	 DAC_CLK_CTRL_DACR_INIT_ON		(1 << 0)
+#define	CODEC_HPMIX_CTRL		0x94
+#define	 HPMIX_CTRL_HPMIXL_EN			(1 << 6)
+#define	 HPMIX_CTRL_HPMIXL_INIT_EN		(1 << 5)
+#define	 HPMIX_CTRL_HPMIXL_INIT2_EN		(1 << 4)
+#define	 HPMIX_CTRL_HPMIXR_EN			(1 << 2)
+#define	 HPMIX_CTRL_HPMIXR_INIT_EN		(1 << 1)
+#define	 HPMIX_CTRL_HPMIXR_INIT2_EN		(1 << 0)
+#define	CODEC_DAC_SELECT		0x98
+#define	 DAC_SELECT_DACL_SELECT			(1 << 4)
+#define	 DAC_SELECT_DACR_SELECT			(1 << 0)
+#define	CODEC_HPOUT_CTRL		0x9c
+#define	 HPOUT_CTRL_HPOUTL_EN			(1 << 7)
+#define	 HPOUT_CTRL_HPOUTL_INIT_EN		(1 << 6)
+#define	 HPOUT_CTRL_HPOUTL_UNMUTE		(1 << 5)
+#define	 HPOUT_CTRL_HPOUTR_EN			(1 << 4)
+#define	 HPOUT_CTRL_HPOUTR_INIT_EN		(1 << 3)
+#define	 HPOUT_CTRL_HPOUTR_UNMUTE		(1 << 2)
+#define	CODEC_HPOUTL_GAIN_CTRL		0xa0
+#define	CODEC_HPOUTR_GAIN_CTRL		0xa4
+#define	CODEC_HPOUT_POP_CTRL		0xa8
+#define	 HPOUT_POP_CTRL_HPOUTR_POP		(1 << 5)
+#define	 HPOUT_POP_CTRL_HPOUTR_POP_XCHARGE	(1 << 4)
+#define	 HPOUT_POP_CTRL_HPOUTL_POP		(1 << 1)
+#define	 HPOUT_POP_CTRL_HPOUTL_POP_XCHARGE	(1 << 0)
+
+#define	DEFAULT_RATE			(48000 * 256)
+
+static struct ofw_compat_data compat_data[] = {
+	{ "rockchip,rk3328-codec",	1},
+	{ NULL,				0 }
+};
+
+struct rkcodec_softc {
+	device_t	dev;
+	struct resource	*res;
+	struct mtx	mtx;
+	clk_t		mclk;
+	clk_t		pclk;
+	struct syscon	*grf;
+	u_int	regaddr;	/* address for the sysctl */
+};
+
+#define	RKCODEC_LOCK(sc)		mtx_lock(&(sc)->mtx)
+#define	RKCODEC_UNLOCK(sc)		mtx_unlock(&(sc)->mtx)
+#define	RKCODEC_READ(sc, reg)		bus_read_4((sc)->res, (reg))
+#define	RKCODEC_WRITE(sc, reg, val)	bus_write_4((sc)->res, (reg), (val))
+
+static int rkcodec_probe(device_t dev);
+static int rkcodec_attach(device_t dev);
+static int rkcodec_detach(device_t dev);
+
+static void
+rkcodec_set_power(struct rkcodec_softc *sc, bool poweron)
+{
+	uint32_t val;
+	val = RKCODEC_READ(sc, CODEC_DAC_PRECHARGE_CTRL);
+	if (poweron)
+		val |= DAC_PRECHARGE_CTRL_DAC_CHARGE_PRECHARGE;
+	else
+		val &= ~(DAC_PRECHARGE_CTRL_DAC_CHARGE_PRECHARGE);
+	RKCODEC_WRITE(sc, CODEC_DAC_PRECHARGE_CTRL, val);
+	DELAY(10);
+	if (poweron)
+		val |= DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_ALL;
+	else
+		val &= ~(DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_ALL);
+	RKCODEC_WRITE(sc, CODEC_DAC_PRECHARGE_CTRL, val);
+
+}
+
+static void
+rkcodec_set_mute(struct rkcodec_softc *sc, bool muted)
+{
+	uint32_t val;
+	val = SOC_CON10_GPIOMUT_MASK;
+	if (!muted)
+		val |= SOC_CON10_GPIOMUT;
+	SYSCON_WRITE_4(sc->grf, GRF_SOC_CON10, val);
+}
+
+static void
+rkcodec_reset(struct rkcodec_softc *sc)
+{
+
+	RKCODEC_WRITE(sc, CODEC_RESET, 0);
+	DELAY(10);
+	RKCODEC_WRITE(sc, CODEC_RESET, RESET_DIG_CORE_RST | RESET_SYS_RST);
+}
+
+static int
+rkcodec_probe(device_t dev)
+{
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+		return (ENXIO);
+
+	device_set_desc(dev, "Rockchip RK3328 CODEC");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+rkcodec_attach(device_t dev)
+{
+	struct rkcodec_softc *sc;
+	int error, rid;
+	phandle_t node;
+	uint32_t val;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+	rid = 0;
+	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (!sc->res) {
+		device_printf(dev, "could not allocate resource for device\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	node = ofw_bus_get_node(dev);
+	if (syscon_get_by_ofw_property(dev, node,
+	    "rockchip,grf", &sc->grf) != 0) {
+		device_printf(dev, "cannot get rockchip,grf handle\n");
+		return (ENXIO);
+	}
+
+	val = SOC_CON2_I2S_ACODEC_EN_MASK  | (SOC_CON2_I2S_ACODEC_EN << 16);
+	SYSCON_WRITE_4(sc->grf, GRF_SOC_CON2, val);
+
+	val = 0 | (SOC_CON10_GPIOMUT_EN << 16);
+	SYSCON_WRITE_4(sc->grf, GRF_SOC_CON10, val);
+
+	error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
+	if (error != 0) {
+		device_printf(dev, "could not get pclk clock\n");
+		goto fail;
+	}
+
+	error = clk_get_by_ofw_name(dev, 0, "mclk", &sc->mclk);
+	if (error != 0) {
+		device_printf(dev, "could not get mclk clock\n");
+		goto fail;
+	}
+
+	error = clk_enable(sc->pclk);
+	if (error != 0) {
+		device_printf(sc->dev, "could not enable pclk clock\n");
+		goto fail;
+	}
+
+	error = clk_enable(sc->mclk);
+	if (error != 0) {
+		device_printf(sc->dev, "could not enable mclk clock\n");
+		goto fail;
+	}
+
+#if 0
+	error = clk_set_freq(sc->mclk, DEFAULT_RATE, 0);
+	if (error != 0) {
+		device_printf(sc->dev, "could not set frequency for mclk clock\n");
+		goto fail;
+	}
+#endif
+
+	/* TODO: handle mute-gpios */
+
+	rkcodec_reset(sc);
+	rkcodec_set_power(sc, true);
+
+	val = RKCODEC_READ(sc, CODEC_DAC_PWR_CTRL);
+	val |= DAC_PWR_CTRL_DAC_PWR;
+	RKCODEC_WRITE(sc, CODEC_DAC_PWR_CTRL, val);
+
+	val |= DAC_PWR_CTRL_DACL_PATH_REFV |
+	    DAC_PWR_CTRL_DACR_PATH_REFV;
+	RKCODEC_WRITE(sc, CODEC_DAC_PWR_CTRL, val);
+
+	val |= DAC_PWR_CTRL_HPOUTL_ZERO_CROSSING |
+	    DAC_PWR_CTRL_HPOUTR_ZERO_CROSSING;
+	RKCODEC_WRITE(sc, CODEC_DAC_PWR_CTRL, val);
+
+	val = RKCODEC_READ(sc, CODEC_HPOUT_POP_CTRL);
+	val |= HPOUT_POP_CTRL_HPOUTR_POP | HPOUT_POP_CTRL_HPOUTL_POP;
+	val &= ~(HPOUT_POP_CTRL_HPOUTR_POP_XCHARGE | HPOUT_POP_CTRL_HPOUTL_POP_XCHARGE);
+	RKCODEC_WRITE(sc, CODEC_HPOUT_POP_CTRL, val);
+
+	val = RKCODEC_READ(sc, CODEC_HPMIX_CTRL);
+	val |= HPMIX_CTRL_HPMIXL_EN | HPMIX_CTRL_HPMIXR_EN;
+	RKCODEC_WRITE(sc, CODEC_HPMIX_CTRL, val);
+
+	val |= HPMIX_CTRL_HPMIXL_INIT_EN | HPMIX_CTRL_HPMIXR_INIT_EN;
+	RKCODEC_WRITE(sc, CODEC_HPMIX_CTRL, val);
+
+	val = RKCODEC_READ(sc, CODEC_HPOUT_CTRL);
+	val |= HPOUT_CTRL_HPOUTL_EN | HPOUT_CTRL_HPOUTR_EN;
+	RKCODEC_WRITE(sc, CODEC_HPOUT_CTRL, val);
+
+	val |= HPOUT_CTRL_HPOUTL_INIT_EN | HPOUT_CTRL_HPOUTR_INIT_EN;
+	RKCODEC_WRITE(sc, CODEC_HPOUT_CTRL, val);
+
+	val = RKCODEC_READ(sc, CODEC_DAC_CLK_CTRL);
+	val |= DAC_CLK_CTRL_DACL_REFV_ON | DAC_CLK_CTRL_DACR_REFV_ON;
+	RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val);
+
+	val |= DAC_CLK_CTRL_DACL_CLK_ON | DAC_CLK_CTRL_DACR_CLK_ON;
+	RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val);
+
+	val |= DAC_CLK_CTRL_DACL_ON | DAC_CLK_CTRL_DACR_ON;
+	RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val);
+
+	val |= DAC_CLK_CTRL_DACL_INIT_ON | DAC_CLK_CTRL_DACR_INIT_ON;
+	RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val);
+
+	val = RKCODEC_READ(sc, CODEC_DAC_SELECT);
+	val |= DAC_SELECT_DACL_SELECT | DAC_SELECT_DACR_SELECT;
+	RKCODEC_WRITE(sc, CODEC_DAC_SELECT, val);
+
+	val = RKCODEC_READ(sc, CODEC_HPMIX_CTRL);
+	val |= HPMIX_CTRL_HPMIXL_INIT2_EN | HPMIX_CTRL_HPMIXR_INIT2_EN;
+	RKCODEC_WRITE(sc, CODEC_HPMIX_CTRL, val);
+
+	val = RKCODEC_READ(sc, CODEC_HPOUT_CTRL);
+	val |= HPOUT_CTRL_HPOUTL_UNMUTE | HPOUT_CTRL_HPOUTR_UNMUTE;
+	RKCODEC_WRITE(sc, CODEC_HPOUT_CTRL, val);
+
+	RKCODEC_WRITE(sc, CODEC_HPOUTL_GAIN_CTRL, 0x1f);
+	RKCODEC_WRITE(sc, CODEC_HPOUTR_GAIN_CTRL, 0x1f);
+
+	rkcodec_set_mute(sc, false);
+
+	node = ofw_bus_get_node(dev);
+	OF_device_register_xref(OF_xref_from_node(node), dev);
+
+	return (0);
+
+fail:
+	rkcodec_detach(dev);
+	return (error);
+}
+
+static int
+rkcodec_detach(device_t dev)
+{
+	struct rkcodec_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	if (sc->res)
+		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
+	mtx_destroy(&sc->mtx);
+
+	return (0);
+}
+
+static int
+rkcodec_mixer_init(struct snd_mixer *m)
+{
+
+	mix_setdevs(m, RKCODEC_MIXER_DEVS);
+
+	return (0);
+}
+
+static int
+rkcodec_mixer_uninit(struct snd_mixer *m)
+{
+
+	return (0);
+}
+
+static int
+rkcodec_mixer_reinit(struct snd_mixer *m)
+{
+
+	return (0);
+}
+
+static int
+rkcodec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
+{
+	struct rkcodec_softc *sc;
+	struct mtx *mixer_lock;
+	uint8_t do_unlock;
+
+	sc = device_get_softc(mix_getdevinfo(m));
+	mixer_lock = mixer_get_lock(m);
+
+	if (mtx_owned(mixer_lock)) {
+		do_unlock = 0;
+	} else {
+		do_unlock = 1;
+		mtx_lock(mixer_lock);
+	}
+
+	right = left;
+
+	RKCODEC_LOCK(sc);
+	switch(dev) {
+	case SOUND_MIXER_VOLUME:
+		printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__);
+		break;
+
+	case SOUND_MIXER_MIC:
+		printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__);
+		break;
+	default:
+		break;
+	}
+	RKCODEC_UNLOCK(sc);
+
+	if (do_unlock) {
+		mtx_unlock(mixer_lock);
+	}
+
+	return (left | (right << 8));
+}
+
+static unsigned
+rkcodec_mixer_setrecsrc(struct snd_mixer *m, unsigned src)
+{
+
+	return (0);
+}
+
+static kobj_method_t rkcodec_mixer_methods[] = {
+	KOBJMETHOD(mixer_init,		rkcodec_mixer_init),
+	KOBJMETHOD(mixer_uninit,	rkcodec_mixer_uninit),
+	KOBJMETHOD(mixer_reinit,	rkcodec_mixer_reinit),
+	KOBJMETHOD(mixer_set,		rkcodec_mixer_set),
+	KOBJMETHOD(mixer_setrecsrc,	rkcodec_mixer_setrecsrc),
+	KOBJMETHOD_END
+};
+
+MIXER_DECLARE(rkcodec_mixer);
+
+static int
+rkcodec_dai_init(device_t dev, uint32_t format)
+{
+	struct rkcodec_softc *sc;
+	int fmt, pol, clk;
+	uint32_t ctrl1, ctrl2, ctrl3;
+
+	sc = device_get_softc(dev);
+
+	fmt = AUDIO_DAI_FORMAT_FORMAT(format);
+	pol = AUDIO_DAI_FORMAT_POLARITY(format);
+	clk = AUDIO_DAI_FORMAT_CLOCK(format);
+
+	ctrl1 = RKCODEC_READ(sc, CODEC_DAC_INIT_CTRL1);
+	ctrl2 = RKCODEC_READ(sc, CODEC_DAC_INIT_CTRL2);
+	ctrl3 = RKCODEC_READ(sc, CODEC_DAC_INIT_CTRL3);
+
+	ctrl3 &= ~(DAC_INIT_CTRL3_DAC_BCP_MASK);
+	switch (pol) {
+	case AUDIO_DAI_POLARITY_IB_NF:
+		ctrl3 |= DAC_INIT_CTRL3_DAC_BCP_REVERSAL;
+		break;
+	case AUDIO_DAI_POLARITY_NB_NF:
+		ctrl3 |= DAC_INIT_CTRL3_DAC_BCP_NORMAL;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	ctrl1 &= ~(DAC_INIT_CTRL1_MODE_MASK);
+	switch (clk) {
+	case AUDIO_DAI_CLOCK_CBM_CFM:
+		ctrl1 |= DAC_INIT_CTRL1_DIRECTION_OUT |
+		    DAC_INIT_CTRL1_DAC_I2S_MODE_SLAVE;
+		break;
+	case AUDIO_DAI_CLOCK_CBS_CFS:
+		ctrl1 |= DAC_INIT_CTRL1_DIRECTION_IN |
+		    DAC_INIT_CTRL1_DAC_I2S_MODE_SLAVE;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	ctrl2 &= ~(DAC_INIT_CTRL2_DAC_VDL_MASK | DAC_INIT_CTRL2_DAC_MODE_MASK);
+	ctrl2 |= DAC_INIT_CTRL2_DAC_VDL_16BITS;
+	ctrl3 &= ~(DAC_INIT_CTRL3_WL_MASK);
+	ctrl3 |= DAC_INIT_CTRL3_WL_32BITS;
+	switch (fmt) {
+	case AUDIO_DAI_FORMAT_I2S:
+		ctrl2 |= DAC_INIT_CTRL2_DAC_MODE_I2S;
+		break;
+	case AUDIO_DAI_FORMAT_LJ:
+		ctrl2 |= DAC_INIT_CTRL2_DAC_MODE_LJM;
+		break;
+	case AUDIO_DAI_FORMAT_RJ:
+		ctrl2 |= DAC_INIT_CTRL2_DAC_MODE_RJM;
+		break;
+	default:
+		return EINVAL;
+	}
+
+	ctrl3 &= ~(DAC_INIT_CTRL3_RST_MASK);
+	ctrl3 |= DAC_INIT_CTRL3_RST_DIS;
+
+	RKCODEC_WRITE(sc, CODEC_DAC_INIT_CTRL1, ctrl1);
+	RKCODEC_WRITE(sc, CODEC_DAC_INIT_CTRL2, ctrl2);
+	RKCODEC_WRITE(sc, CODEC_DAC_INIT_CTRL3, ctrl3);
+
+	return (0);
+}
+
+static int
+rkcodec_dai_trigger(device_t dev, int go, int pcm_dir)
+{
+	// struct rkcodec_softc 	*sc = device_get_softc(dev);
+
+	if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC))
+		return (EINVAL);
+
+	switch (go) {
+	case PCMTRIG_START:
+		if (pcm_dir == PCMDIR_PLAY) {
+			printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__);
+		}
+		else if (pcm_dir == PCMDIR_REC) {
+			printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__);
+		}
+		break;
+
+	case PCMTRIG_STOP:
+	case PCMTRIG_ABORT:
+		if (pcm_dir == PCMDIR_PLAY) {
+			printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__);
+		}
+		else if (pcm_dir == PCMDIR_REC) {
+			printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__);
+		}
+		break;
+	}
+
+	return (0);
+}
+
+static int
+rkcodec_dai_setup_mixer(device_t dev, device_t pcmdev)
+{
+
+	mixer_init(pcmdev, &rkcodec_mixer_class, dev);
+
+	return (0);
+}
+
+static device_method_t rkcodec_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		rkcodec_probe),
+	DEVMETHOD(device_attach,	rkcodec_attach),
+	DEVMETHOD(device_detach,	rkcodec_detach),
+
+	DEVMETHOD(audio_dai_init,	rkcodec_dai_init),
+	DEVMETHOD(audio_dai_setup_mixer,	rkcodec_dai_setup_mixer),
+	DEVMETHOD(audio_dai_trigger,	rkcodec_dai_trigger),
+
+	DEVMETHOD_END
+};
+
+static driver_t rkcodec_driver = {
+	"rk3328codec",
+	rkcodec_methods,
+	sizeof(struct rkcodec_softc),
+};
+
+static devclass_t rkcodec_devclass;
+
+DRIVER_MODULE(rkcodec, simplebus, rkcodec_driver, rkcodec_devclass, 0, 0);
+SIMPLEBUS_PNP_INFO(compat_data);
diff --git a/sys/arm64/rockchip/rk_i2s.c b/sys/arm64/rockchip/rk_i2s.c
new file mode 100644
index 000000000000..8f53d8581d5c
--- /dev/null
+++ b/sys/arm64/rockchip/rk_i2s.c
@@ -0,0 +1,657 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/resource.h>
+#include <machine/bus.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/hwreset/hwreset.h>
+#include <dev/extres/syscon/syscon.h>
+
+#include "syscon_if.h"
+
+#include "opt_snd.h"
+#include <dev/sound/pcm/sound.h>
+#include <dev/sound/fdt/audio_dai.h>
+#include "audio_dai_if.h"
+
+#define	AUDIO_BUFFER_SIZE	48000 * 4
+
+#define	I2S_TXCR	0x0000
+#define		I2S_CSR_2		(0 << 15)
+#define		I2S_CSR_4		(1 << 15)
+#define		I2S_CSR_6		(2 << 15)
+#define		I2S_CSR_8		(3 << 15)
+#define		I2S_TXCR_IBM_NORMAL	(0 << 9)
+#define		I2S_TXCR_IBM_LJ		(1 << 9)
+#define		I2S_TXCR_IBM_RJ		(2 << 9)
+#define		I2S_TXCR_PBM_NODELAY	(0 << 7)
+#define		I2S_TXCR_PBM_1		(1 << 7)
+#define		I2S_TXCR_PBM_2		(2 << 7)
+#define		I2S_TXCR_PBM_3		(3 << 7)
+#define		I2S_TXCR_TFS_I2S	(0 << 5)
+#define		I2S_TXCR_TFS_PCM	(1 << 5)
+#define		I2S_TXCR_VDW_16		(0xf << 0)
+#define	I2S_RXCR	0x0004
+#define		I2S_RXCR_IBM_NORMAL	(0 << 9)
+#define		I2S_RXCR_IBM_LJ		(1 << 9)
+#define		I2S_RXCR_IBM_RJ		(2 << 9)
+#define		I2S_RXCR_PBM_NODELAY	(0 << 7)
+#define		I2S_RXCR_PBM_1		(1 << 7)
+#define		I2S_RXCR_PBM_2		(2 << 7)
+#define		I2S_RXCR_PBM_3		(3 << 7)
+#define		I2S_RXCR_TFS_I2S	(0 << 5)
+#define		I2S_RXCR_TFS_PCM	(1 << 5)
+#define		I2S_RXCR_VDW_16		(0xf << 0)
+#define	I2S_CKR		0x0008
+#define		I2S_CKR_MSS_MASK	(1 << 27)
+#define		I2S_CKR_MSS_MASTER	(0 << 27)
+#define		I2S_CKR_MSS_SLAVE	(1 << 27)
+#define		I2S_CKR_CKP		(1 << 26)
+#define		I2S_CKR_MDIV(n)		(((n) - 1) << 16)
+#define		I2S_CKR_MDIV_MASK	(0xff << 16)
+#define		I2S_CKR_RSD(n)		(((n) - 1) << 8)
+#define		I2S_CKR_RSD_MASK	(0xff << 8)
+#define		I2S_CKR_TSD(n)		(((n) - 1) << 0)
+#define		I2S_CKR_TSD_MASK	(0xff << 0)
+#define	I2S_TXFIFOLR	0x000c
+#define		TXFIFO0LR_MASK		0x3f
+#define	I2S_DMACR	0x0010
+#define		I2S_DMACR_RDE_ENABLE	(1 << 24)
+#define		I2S_DMACR_RDL(n)	((n) << 16)
+#define		I2S_DMACR_TDE_ENABLE	(1 << 8)
+#define		I2S_DMACR_TDL(n)	((n) << 0)
+#define	I2S_INTCR	0x0014
+#define		I2S_INTCR_RFT(n)	(((n) - 1) << 20)
+#define		I2S_INTCR_TFT(n)	(((n) - 1) << 4)
+#define		I2S_INTCR_RXFIE		(1 << 16)
+#define		I2S_INTCR_TXUIC		(1 << 2)
+#define		I2S_INTCR_TXEIE		(1 << 0)
+#define	I2S_INTSR	0x0018
+#define		I2S_INTSR_RXFI		(1 << 16)
+#define		I2S_INTSR_TXUI		(1 << 1)
+#define		I2S_INTSR_TXEI		(1 << 0)
+#define	I2S_XFER	0x001c
+#define		I2S_XFER_RXS_START	(1 << 1)
+#define		I2S_XFER_TXS_START	(1 << 0)
+#define	I2S_CLR		0x0020
+#define		I2S_CLR_RXC		(1 << 1)
+#define		I2S_CLR_TXC		(1 << 0)
+#define	I2S_TXDR	0x0024
+#define	I2S_RXDR	0x0028
+#define	I2S_RXFIFOLR	0x002c
+#define		RXFIFO0LR_MASK		0x3f
+
+/* syscon */
+#define	GRF_SOC_CON8			0xe220
+#define	I2S_IO_DIRECTION_MASK		7
+#define	I2S_IO_DIRECTION_SHIFT		11
+#define	I2S_IO_8CH_OUT_2CH_IN		0
+#define	I2S_IO_6CH_OUT_4CH_IN		4
+#define	I2S_IO_4CH_OUT_6CH_IN		6
+#define	I2S_IO_2CH_OUT_8CH_IN		7
+
+#define DIV_ROUND_CLOSEST(n,d)  (((n) + (d) / 2) / (d))
+
+#define	RK_I2S_SAMPLING_RATE	48000
+#define	FIFO_SIZE	32
+
+static struct ofw_compat_data compat_data[] = {
+	{ "rockchip,rk3066-i2s",		1 },
+	{ "rockchip,rk3399-i2s",		1 },
+	{ NULL,					0 }
+};
+
+static struct resource_spec rk_i2s_spec[] = {
+	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
+	{ SYS_RES_IRQ,		0,	RF_ACTIVE | RF_SHAREABLE },
+	{ -1, 0 }
+};
+
+struct rk_i2s_softc {
+	device_t	dev;
+	struct resource	*res[2];
+	struct mtx	mtx;
+	clk_t		clk;
+	clk_t		hclk;
+	void *		intrhand;
+	struct syscon	*grf;
+	/* pointers to playback/capture buffers */
+	uint32_t	play_ptr;
+	uint32_t	rec_ptr;
+};
+
+#define	RK_I2S_LOCK(sc)			mtx_lock(&(sc)->mtx)
+#define	RK_I2S_UNLOCK(sc)		mtx_unlock(&(sc)->mtx)
+#define	RK_I2S_READ_4(sc, reg)		bus_read_4((sc)->res[0], (reg))
+#define	RK_I2S_WRITE_4(sc, reg, val)	bus_write_4((sc)->res[0], (reg), (val))
+
+static int rk_i2s_probe(device_t dev);
+static int rk_i2s_attach(device_t dev);
+static int rk_i2s_detach(device_t dev);
+
+static uint32_t sc_fmt[] = {
+	SND_FORMAT(AFMT_S16_LE, 2, 0),
+	0
+};
+static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0};
+
+
+static int
+rk_i2s_init(struct rk_i2s_softc *sc)
+{
+	uint32_t val;
+	int error;
+
+	clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256,
+	    CLK_SET_ROUND_DOWN);
+	error = clk_enable(sc->clk);
+	if (error != 0) {
+		device_printf(sc->dev, "cannot enable i2s_clk clock\n");
+		return (ENXIO);
+	}
+
+	val = I2S_INTCR_TFT(FIFO_SIZE/2);
+	val |= I2S_INTCR_RFT(FIFO_SIZE/2);
+	RK_I2S_WRITE_4(sc, I2S_INTCR, val);
+
+	if (sc->grf) {
+		val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT);
+		val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16;
+		SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val);
+
+		#if 0
+		// HACK: enable IO domain
+		val = (1 << 1);
+		val |= (1 << 1) << 16;
+		SYSCON_WRITE_4(sc->grf, 0xe640, val);
+		#endif
+	}
+
+	RK_I2S_WRITE_4(sc, I2S_XFER, 0);
+
+	return (0);
+}
+
+static int
+rk_i2s_probe(device_t dev)
+{
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+		return (ENXIO);
+
+	device_set_desc(dev, "Rockchip I2S");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+rk_i2s_attach(device_t dev)
+{
+	struct rk_i2s_softc *sc;
+	int error;
+	phandle_t node;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+	if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) {
+		device_printf(dev, "cannot allocate resources for device\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk);
+	if (error != 0) {
+		device_printf(dev, "cannot get i2s_hclk clock\n");
+		goto fail;
+	}
+
+	error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk);
+	if (error != 0) {
+		device_printf(dev, "cannot get i2s_clk clock\n");
+		goto fail;
+	}
+
+	/* Activate the module clock. */
+	error = clk_enable(sc->hclk);
+	if (error != 0) {
+		device_printf(dev, "cannot enable i2s_hclk clock\n");
+		goto fail;
+	}
+
+	node = ofw_bus_get_node(dev);
+	if (OF_hasprop(node, "rockchip,grf") &&
+	    syscon_get_by_ofw_property(dev, node,
+	    "rockchip,grf", &sc->grf) != 0) {
+		device_printf(dev, "cannot get grf driver handle\n");
+		return (ENXIO);
+	}
+
+	rk_i2s_init(sc);
+
+	OF_device_register_xref(OF_xref_from_node(node), dev);
+
+	return (0);
+
+fail:
+	rk_i2s_detach(dev);
+	return (error);
+}
+
+static int
+rk_i2s_detach(device_t dev)
+{
+	struct rk_i2s_softc *i2s;
+
+	i2s = device_get_softc(dev);
+
+	if (i2s->hclk != NULL)
+		clk_release(i2s->hclk);
+	if (i2s->clk)
+		clk_release(i2s->clk);
+
+	if (i2s->intrhand != NULL)
+		bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand);
+
+	bus_release_resources(dev, rk_i2s_spec, i2s->res);
+	mtx_destroy(&i2s->mtx);
+
+	return (0);
+}
+
+static int
+rk_i2s_dai_init(device_t dev, uint32_t format)
+{
+	uint32_t val, txcr, rxcr;
+	struct rk_i2s_softc *sc;
+	int fmt, pol, clk;
+
+	sc = device_get_softc(dev);
+
+	fmt = AUDIO_DAI_FORMAT_FORMAT(format);
+	pol = AUDIO_DAI_FORMAT_POLARITY(format);
+	clk = AUDIO_DAI_FORMAT_CLOCK(format);
+
+	/* Set format */
+	val = RK_I2S_READ_4(sc, I2S_CKR);
+
+	val &= ~(I2S_CKR_MSS_MASK);
+	switch (clk) {
+	case AUDIO_DAI_CLOCK_CBM_CFM:
+		val |= I2S_CKR_MSS_MASTER;
+		break;
+	case AUDIO_DAI_CLOCK_CBS_CFS:
+		val |= I2S_CKR_MSS_SLAVE;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	switch (pol) {
+	case AUDIO_DAI_POLARITY_IB_NF:
+		val |= I2S_CKR_CKP;
+		break;
+	case AUDIO_DAI_POLARITY_NB_NF:
+		val &= ~I2S_CKR_CKP;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	RK_I2S_WRITE_4(sc, I2S_CKR, val);
+
+	txcr = I2S_TXCR_VDW_16 | I2S_CSR_2;
+	rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2;
+
+	switch (fmt) {
+	case AUDIO_DAI_FORMAT_I2S:
+		txcr |= I2S_TXCR_IBM_NORMAL;
+		rxcr |= I2S_RXCR_IBM_NORMAL;
+		break;
+	case AUDIO_DAI_FORMAT_LJ:
+		txcr |= I2S_TXCR_IBM_LJ;
+		rxcr |= I2S_RXCR_IBM_LJ;
+		break;
+	case AUDIO_DAI_FORMAT_RJ:
+		txcr |= I2S_TXCR_IBM_RJ;
+		rxcr |= I2S_RXCR_IBM_RJ;
+		break;
+	case AUDIO_DAI_FORMAT_DSPA:
+		txcr |= I2S_TXCR_TFS_PCM;
+		rxcr |= I2S_RXCR_TFS_PCM;
+		txcr |= I2S_TXCR_PBM_1;
+		rxcr |= I2S_RXCR_PBM_1;
+		break;
+	case AUDIO_DAI_FORMAT_DSPB:
+		txcr |= I2S_TXCR_TFS_PCM;
+		rxcr |= I2S_RXCR_TFS_PCM;
+		txcr |= I2S_TXCR_PBM_2;
+		rxcr |= I2S_RXCR_PBM_2;
+		break;
+	default:
+		return EINVAL;
+	}
+
+	RK_I2S_WRITE_4(sc, I2S_TXCR, txcr);
+	RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr);
+
+	RK_I2S_WRITE_4(sc, I2S_XFER, 0);
+
+	return (0);
+}
+
+
+static int
+rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf)
+{
+	struct rk_i2s_softc *sc;
+	uint32_t status;
+	uint32_t level;
+	uint32_t val = 0x00;
+	int ret = 0;
+
+	sc = device_get_softc(dev);
+
+	RK_I2S_LOCK(sc);
+	status = RK_I2S_READ_4(sc, I2S_INTSR);
+
+	if (status & I2S_INTSR_TXEI) {
+		level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK;
+		uint8_t *samples;
+		uint32_t count, size, readyptr, written;
+		count = sndbuf_getready(play_buf);
+		size = sndbuf_getsize(play_buf);
+		readyptr = sndbuf_getreadyptr(play_buf);
+
+		/* FIXME: check actual count size */
+		samples = (uint8_t*)sndbuf_getbuf(play_buf);
+		written = 0;
+		for (; level < FIFO_SIZE - 1; level++) {
+			val  = (samples[readyptr++ % size] << 0);
+			val |= (samples[readyptr++ % size] << 8);
+			val |= (samples[readyptr++ % size] << 16);
+			val |= (samples[readyptr++ % size] << 24);
+			written += 4;
+			RK_I2S_WRITE_4(sc, I2S_TXDR, val);
+		}
+		sc->play_ptr += written;
+		sc->play_ptr %= size;
+		ret |= AUDIO_DAI_PLAY_INTR;
+	}
+
+	if (status & I2S_INTSR_RXFI) {
+		level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK;
+		uint8_t *samples;
+		uint32_t count, size, freeptr, recorded;
+		count = sndbuf_getfree(rec_buf);
+		size = sndbuf_getsize(rec_buf);
+		freeptr = sndbuf_getfreeptr(rec_buf);
+		samples = (uint8_t*)sndbuf_getbuf(rec_buf);
+		recorded = 0;
+		if (level > count / 4)
+			level = count / 4;
+
+		for (; level > 0; level--) {
+			val = RK_I2S_READ_4(sc, I2S_RXDR);
+			samples[freeptr++ % size] = val & 0xff;
+			samples[freeptr++ % size] = (val >> 8) & 0xff;
+			samples[freeptr++ % size] = (val >> 16) & 0xff;
+			samples[freeptr++ % size] = (val >> 24) & 0xff;
+			recorded += 4;
+		}
+		sc->rec_ptr += recorded;
+		sc->rec_ptr %= size;
+		ret |= AUDIO_DAI_REC_INTR;
+	}
+
+	RK_I2S_UNLOCK(sc);
+
+	return (ret);
+}
+
+static struct pcmchan_caps *
+rk_i2s_dai_get_caps(device_t dev)
+{
+	return (&rk_i2s_caps);
+}
+
+static int
+rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir)
+{
+	struct rk_i2s_softc 	*sc = device_get_softc(dev);
+	uint32_t val;
+	uint32_t clear_bit;
+
+	if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC))
+		return (EINVAL);
+
+	switch (go) {
+	case PCMTRIG_START:
+		val = RK_I2S_READ_4(sc, I2S_INTCR);
+		if (pcm_dir == PCMDIR_PLAY)
+			val |= I2S_INTCR_TXEIE;
+		else if (pcm_dir == PCMDIR_REC)
+			val |= I2S_INTCR_RXFIE;
+		RK_I2S_WRITE_4(sc, I2S_INTCR, val);
+
+		val = I2S_XFER_TXS_START | I2S_XFER_RXS_START;
+		RK_I2S_WRITE_4(sc, I2S_XFER, val);
+		break;
+
+	case PCMTRIG_STOP:
+	case PCMTRIG_ABORT:
+		val = RK_I2S_READ_4(sc, I2S_INTCR);
+		if (pcm_dir == PCMDIR_PLAY)
+			val &= ~I2S_INTCR_TXEIE;
+		else if (pcm_dir == PCMDIR_REC)
+			val &= ~I2S_INTCR_RXFIE;
+		RK_I2S_WRITE_4(sc, I2S_INTCR, val);
+
+		/*
+		 * If there is no other activity going on, stop transfers
+		 */
+		if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) {
+			RK_I2S_WRITE_4(sc, I2S_XFER, 0);
+
+			if (pcm_dir == PCMDIR_PLAY)
+				clear_bit = I2S_CLR_TXC;
+			else if (pcm_dir == PCMDIR_REC)
+				clear_bit = I2S_CLR_RXC;
+			else
+				return (EINVAL);
+
+			val = RK_I2S_READ_4(sc, I2S_CLR);
+			val |= clear_bit;
+			RK_I2S_WRITE_4(sc, I2S_CLR, val);
+
+			while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0)
+				DELAY(1);
+		}
+
+		RK_I2S_LOCK(sc);
+		if (pcm_dir == PCMDIR_PLAY)
+			sc->play_ptr = 0;
+		else
+			sc->rec_ptr = 0;
+		RK_I2S_UNLOCK(sc);
+		break;
+	}
+
+	return (0);
+}
+
+static uint32_t
+rk_i2s_dai_get_ptr(device_t dev, int pcm_dir)
+{
+	struct rk_i2s_softc *sc;
+	uint32_t ptr;
+
+	sc = device_get_softc(dev);
+
+	RK_I2S_LOCK(sc);
+	if (pcm_dir == PCMDIR_PLAY)
+		ptr = sc->play_ptr;
+	else
+		ptr = sc->rec_ptr;
+	RK_I2S_UNLOCK(sc);
+
+	return ptr;
+}
+
+static int
+rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg)
+{
+	struct rk_i2s_softc 	*sc = device_get_softc(dev);
+
+	if (bus_setup_intr(dev, sc->res[1],
+	    INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg,
+	    &sc->intrhand)) {
+		device_printf(dev, "cannot setup interrupt handler\n");
+		return (ENXIO);
+	}
+
+	return (0);
+}
+
+static uint32_t
+rk_i2s_dai_set_chanformat(device_t dev, uint32_t format)
+{
+
+	return (0);
+}
+
+static int
+rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir)
+{
+	struct rk_i2s_softc *sc;
+	int error;
+
+	sc = device_get_softc(dev);
+	error = clk_disable(sc->clk);
+	if (error != 0) {
+		device_printf(sc->dev, "could not disable i2s_clk clock\n");
+		return (error);
+	}
+
+	error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN);
+	if (error != 0)
+		device_printf(sc->dev, "could not set i2s_clk freq\n");
+
+	error = clk_enable(sc->clk);
+	if (error != 0) {
+		device_printf(sc->dev, "could not enable i2s_clk clock\n");
+		return (error);
+	}
+
+	return (0);
+}
+
+static uint32_t
+rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed)
+{
+	struct rk_i2s_softc *sc;
+	int error;
+	uint32_t val;
+	uint32_t bus_clock_div, lr_clock_div;
+	uint64_t bus_clk_freq;
+	uint64_t clk_freq;
+
+	 sc = device_get_softc(dev);
+
+	/* Set format */
+	val = RK_I2S_READ_4(sc, I2S_CKR);
+
+	if ((val & I2S_CKR_MSS_SLAVE) == 0) {
+		error = clk_get_freq(sc->clk, &clk_freq);
+		if (error != 0) {
+			device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error);
+			return (error);
+		}
+		bus_clk_freq = 2 * 32 * speed;
+		bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq);
+		lr_clock_div = bus_clk_freq / speed;
+
+		val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK);
+		val |= I2S_CKR_MDIV(bus_clock_div);
+		val |= I2S_CKR_RSD(lr_clock_div);
+		val |= I2S_CKR_TSD(lr_clock_div);
+
+		RK_I2S_WRITE_4(sc, I2S_CKR, val);
+	}
+
+	return (speed);
+}
+
+static device_method_t rk_i2s_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		rk_i2s_probe),
+	DEVMETHOD(device_attach,	rk_i2s_attach),
+	DEVMETHOD(device_detach,	rk_i2s_detach),
+
+	DEVMETHOD(audio_dai_init,	rk_i2s_dai_init),
+	DEVMETHOD(audio_dai_setup_intr,	rk_i2s_dai_setup_intr),
+	DEVMETHOD(audio_dai_set_sysclk,	rk_i2s_dai_set_sysclk),
+	DEVMETHOD(audio_dai_set_chanspeed,	rk_i2s_dai_set_chanspeed),
+	DEVMETHOD(audio_dai_set_chanformat,	rk_i2s_dai_set_chanformat),
+	DEVMETHOD(audio_dai_intr,	rk_i2s_dai_intr),
+	DEVMETHOD(audio_dai_get_caps,	rk_i2s_dai_get_caps),
+	DEVMETHOD(audio_dai_trigger,	rk_i2s_dai_trigger),
+	DEVMETHOD(audio_dai_get_ptr,	rk_i2s_dai_get_ptr),
+
+	DEVMETHOD_END
+};
+
+static driver_t rk_i2s_driver = {
+	"i2s",
+	rk_i2s_methods,
+	sizeof(struct rk_i2s_softc),
+};
+
+static devclass_t rk_i2s_devclass;
+
+DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, rk_i2s_devclass, 0, 0);
+SIMPLEBUS_PNP_INFO(compat_data);
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 4e96cd7a76f6..bb356c1babc1 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -533,9 +533,11 @@ dev/ahci/ahci_fsl_fdt.c				optional SOC_NXP_LS ahci fdt
 arm64/qualcomm/qcom_gcc.c			optional qcom_gcc fdt
 
 # RockChip Drivers
+arm64/rockchip/rk3328_codec.c			optional fdt rk3328codec soc_rockchip_rk3328
 arm64/rockchip/rk3399_emmcphy.c			optional fdt rk_emmcphy soc_rockchip_rk3399
 arm64/rockchip/rk_dwc3.c			optional fdt rk_dwc3 soc_rockchip_rk3399
 arm64/rockchip/rk_i2c.c				optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399
+arm64/rockchip/rk_i2s.c				optional fdt sound soc_rockchip_rk3328 | fdt sound soc_rockchip_rk3399
 arm64/rockchip/rk805.c				optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399
 arm64/rockchip/rk_grf.c				optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/rk_pinctrl.c			optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399