Added support driver state capture/retrieval
MFC after:5 days
This commit is contained in:
David C Somayajulu
parent
d7d2f0d4d1
commit
ab142b3f49
@ -201,7 +201,6 @@ struct qla_host {
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qla_rx_buf_t *rxb_free;
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uint32_t rxb_free_count;
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volatile uint32_t posting;
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/* stats */
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uint32_t err_m_getcl;
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@ -112,4 +112,8 @@ extern unsigned int ql83xx_resetseq_len;
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extern unsigned char ql83xx_minidump[];
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extern unsigned int ql83xx_minidump_len;
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extern void ql_alloc_drvr_state_buffer(qla_host_t *ha);
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extern void ql_free_drvr_state_buffer(qla_host_t *ha);
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extern void ql_capture_drvr_state(qla_host_t *ha);
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#endif /* #ifndef_QL_GLBL_H_ */
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@ -1703,6 +1703,9 @@ typedef struct _qla_hw {
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uint32_t mdump_buffer_size;
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void *mdump_template;
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uint32_t mdump_template_size;
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/* driver state related */
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void *drvr_state;
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} qla_hw_t;
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#define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
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@ -39,7 +39,11 @@ __FBSDID("$FreeBSD$");
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#include "ql_inline.h"
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#include "ql_glbl.h"
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#include "ql_ioctl.h"
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#include "ql_ver.h"
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#include "ql_dbg.h"
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static int ql_drvr_state(qla_host_t *ha, qla_driver_state_t *drvr_state);
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static uint32_t ql_drvr_state_size(qla_host_t *ha);
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static int ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td);
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@ -279,6 +283,10 @@ ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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rval = ENXIO;
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break;
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case QLA_RD_DRVR_STATE:
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rval = ql_drvr_state(ha, (qla_driver_state_t *)data);
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break;
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case QLA_RD_PCI_IDS:
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pci_ids = (qla_rd_pci_ids_t *)data;
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pci_ids->ven_id = pci_get_vendor(pci_dev);
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@ -295,3 +303,223 @@ ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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return rval;
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}
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static int
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ql_drvr_state(qla_host_t *ha, qla_driver_state_t *state)
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{
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int rval = 0;
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uint32_t drvr_state_size;
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qla_drvr_state_hdr_t *hdr;
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drvr_state_size = ql_drvr_state_size(ha);
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if (state->buffer == NULL) {
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state->size = drvr_state_size;
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return (0);
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}
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if (state->size < drvr_state_size)
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return (ENXIO);
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if (ha->hw.drvr_state == NULL)
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return (ENOMEM);
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hdr = ha->hw.drvr_state;
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if (!hdr->drvr_version_major)
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ql_capture_drvr_state(ha);
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rval = copyout(ha->hw.drvr_state, state->buffer, drvr_state_size);
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bzero(ha->hw.drvr_state, drvr_state_size);
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return (rval);
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}
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static uint32_t
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ql_drvr_state_size(qla_host_t *ha)
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{
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uint32_t drvr_state_size;
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uint32_t size;
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size = sizeof (qla_drvr_state_hdr_t);
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drvr_state_size = QL_ALIGN(size, 64);
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size = ha->hw.num_tx_rings * (sizeof (qla_drvr_state_tx_t));
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drvr_state_size += QL_ALIGN(size, 64);
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size = ha->hw.num_rds_rings * (sizeof (qla_drvr_state_rx_t));
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drvr_state_size += QL_ALIGN(size, 64);
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size = ha->hw.num_sds_rings * (sizeof (qla_drvr_state_sds_t));
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drvr_state_size += QL_ALIGN(size, 64);
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size = sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS * ha->hw.num_tx_rings;
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drvr_state_size += QL_ALIGN(size, 64);
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size = sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS * ha->hw.num_rds_rings;
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drvr_state_size += QL_ALIGN(size, 64);
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size = sizeof(q80_stat_desc_t) * NUM_STATUS_DESCRIPTORS *
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ha->hw.num_sds_rings;
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drvr_state_size += QL_ALIGN(size, 64);
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return (drvr_state_size);
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}
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static void
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ql_get_tx_state(qla_host_t *ha, qla_drvr_state_tx_t *tx_state)
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{
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int i;
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for (i = 0; i < ha->hw.num_tx_rings; i++) {
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tx_state->base_p_addr = ha->hw.tx_cntxt[i].tx_ring_paddr;
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tx_state->cons_p_addr = ha->hw.tx_cntxt[i].tx_cons_paddr;
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tx_state->tx_prod_reg = ha->hw.tx_cntxt[i].tx_prod_reg;
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tx_state->tx_cntxt_id = ha->hw.tx_cntxt[i].tx_cntxt_id;
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tx_state->txr_free = ha->hw.tx_cntxt[i].txr_free;
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tx_state->txr_next = ha->hw.tx_cntxt[i].txr_next;
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tx_state->txr_comp = ha->hw.tx_cntxt[i].txr_comp;
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tx_state++;
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}
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return;
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}
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static void
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ql_get_rx_state(qla_host_t *ha, qla_drvr_state_rx_t *rx_state)
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{
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int i;
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for (i = 0; i < ha->hw.num_rds_rings; i++) {
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rx_state->prod_std = ha->hw.rds[i].prod_std;
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rx_state->rx_next = ha->hw.rds[i].rx_next;
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rx_state++;
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}
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return;
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}
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static void
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ql_get_sds_state(qla_host_t *ha, qla_drvr_state_sds_t *sds_state)
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{
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int i;
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for (i = 0; i < ha->hw.num_sds_rings; i++) {
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sds_state->sdsr_next = ha->hw.sds[i].sdsr_next;
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sds_state->sds_consumer = ha->hw.sds[i].sds_consumer;
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sds_state++;
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}
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return;
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}
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void
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ql_capture_drvr_state(qla_host_t *ha)
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{
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uint8_t *state_buffer;
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uint8_t *ptr;
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uint32_t drvr_state_size;
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qla_drvr_state_hdr_t *hdr;
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uint32_t size;
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int i;
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drvr_state_size = ql_drvr_state_size(ha);
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state_buffer = ha->hw.drvr_state;
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if (state_buffer == NULL)
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return;
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bzero(state_buffer, drvr_state_size);
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hdr = (qla_drvr_state_hdr_t *)state_buffer;
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hdr->drvr_version_major = QLA_VERSION_MAJOR;
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hdr->drvr_version_minor = QLA_VERSION_MINOR;
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hdr->drvr_version_build = QLA_VERSION_BUILD;
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bcopy(ha->hw.mac_addr, hdr->mac_addr, ETHER_ADDR_LEN);
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hdr->link_speed = ha->hw.link_speed;
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hdr->cable_length = ha->hw.cable_length;
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hdr->cable_oui = ha->hw.cable_oui;
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hdr->link_up = ha->hw.link_up;
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hdr->module_type = ha->hw.module_type;
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hdr->link_faults = ha->hw.link_faults;
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hdr->rcv_intr_coalesce = ha->hw.rcv_intr_coalesce;
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hdr->xmt_intr_coalesce = ha->hw.xmt_intr_coalesce;
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size = sizeof (qla_drvr_state_hdr_t);
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hdr->tx_state_offset = QL_ALIGN(size, 64);
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ptr = state_buffer + hdr->tx_state_offset;
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ql_get_tx_state(ha, (qla_drvr_state_tx_t *)ptr);
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size = ha->hw.num_tx_rings * (sizeof (qla_drvr_state_tx_t));
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hdr->rx_state_offset = hdr->tx_state_offset + QL_ALIGN(size, 64);
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ptr = state_buffer + hdr->rx_state_offset;
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ql_get_rx_state(ha, (qla_drvr_state_rx_t *)ptr);
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size = ha->hw.num_rds_rings * (sizeof (qla_drvr_state_rx_t));
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hdr->sds_state_offset = hdr->rx_state_offset + QL_ALIGN(size, 64);
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ptr = state_buffer + hdr->sds_state_offset;
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ql_get_sds_state(ha, (qla_drvr_state_sds_t *)ptr);
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size = ha->hw.num_sds_rings * (sizeof (qla_drvr_state_sds_t));
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hdr->txr_offset = hdr->sds_state_offset + QL_ALIGN(size, 64);
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ptr = state_buffer + hdr->txr_offset;
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hdr->num_tx_rings = ha->hw.num_tx_rings;
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hdr->txr_size = sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS;
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hdr->txr_entries = NUM_TX_DESCRIPTORS;
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size = hdr->num_tx_rings * hdr->txr_size;
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bcopy(ha->hw.dma_buf.tx_ring.dma_b, ptr, size);
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hdr->rxr_offset = hdr->txr_offset + QL_ALIGN(size, 64);
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ptr = state_buffer + hdr->rxr_offset;
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hdr->rxr_size = sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS;
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hdr->rxr_entries = NUM_RX_DESCRIPTORS;
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hdr->num_rx_rings = ha->hw.num_rds_rings;
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for (i = 0; i < ha->hw.num_rds_rings; i++) {
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bcopy(ha->hw.dma_buf.rds_ring[i].dma_b, ptr, hdr->rxr_size);
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ptr += hdr->rxr_size;
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}
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size = hdr->rxr_size * hdr->num_rx_rings;
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hdr->sds_offset = hdr->rxr_offset + QL_ALIGN(size, 64);
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hdr->sds_ring_size = sizeof(q80_stat_desc_t) * NUM_STATUS_DESCRIPTORS;
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hdr->sds_entries = NUM_STATUS_DESCRIPTORS;
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hdr->num_sds_rings = ha->hw.num_sds_rings;
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ptr = state_buffer + hdr->sds_offset;
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for (i = 0; i < ha->hw.num_sds_rings; i++) {
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bcopy(ha->hw.dma_buf.sds_ring[i].dma_b, ptr, hdr->sds_ring_size);
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ptr += hdr->sds_ring_size;
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}
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return;
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}
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void
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ql_alloc_drvr_state_buffer(qla_host_t *ha)
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{
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uint32_t drvr_state_size;
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drvr_state_size = ql_drvr_state_size(ha);
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ha->hw.drvr_state = malloc(drvr_state_size, M_QLA83XXBUF, M_NOWAIT);
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return;
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}
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void
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ql_free_drvr_state_buffer(qla_host_t *ha)
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{
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if (ha->hw.drvr_state != NULL)
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free(ha->hw.drvr_state, M_QLA83XXBUF);
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return;
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}
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@ -93,6 +93,72 @@ struct qla_rd_fw_dump {
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};
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typedef struct qla_rd_fw_dump qla_rd_fw_dump_t;
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struct qla_drvr_state_tx {
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uint64_t base_p_addr;
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uint64_t cons_p_addr;
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uint32_t tx_prod_reg;
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uint32_t tx_cntxt_id;
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uint32_t txr_free;
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uint32_t txr_next;
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uint32_t txr_comp;
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};
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typedef struct qla_drvr_state_tx qla_drvr_state_tx_t;
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struct qla_drvr_state_sds {
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uint32_t sdsr_next; /* next entry in SDS ring to process */
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uint32_t sds_consumer;
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};
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typedef struct qla_drvr_state_sds qla_drvr_state_sds_t;
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struct qla_drvr_state_rx {
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uint32_t prod_std;
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uint32_t rx_next; /* next standard rcv ring to arm fw */;
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};
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typedef struct qla_drvr_state_rx qla_drvr_state_rx_t;
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struct qla_drvr_state_hdr {
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uint32_t drvr_version_major;
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uint32_t drvr_version_minor;
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uint32_t drvr_version_build;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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uint16_t link_speed;
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uint16_t cable_length;
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uint32_t cable_oui;
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uint8_t link_up;
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uint8_t module_type;
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uint8_t link_faults;
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uint32_t rcv_intr_coalesce;
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uint32_t xmt_intr_coalesce;
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uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */
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uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */
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uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */
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uint32_t num_tx_rings; /* number of tx rings */
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uint32_t txr_size; /* size of each tx ring in bytes */
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uint32_t txr_entries; /* number of descriptors in each tx ring */
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uint32_t txr_offset; /* start of tx ring [0 - #rings] content */
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uint32_t num_rx_rings; /* number of rx rings */
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uint32_t rxr_size; /* size of each rx ring in bytes */
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uint32_t rxr_entries; /* number of descriptors in each rx ring */
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uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */
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uint32_t num_sds_rings; /* number of sds rings */
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uint32_t sds_ring_size; /* size of each sds ring in bytes */
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uint32_t sds_entries; /* number of descriptors in each sds ring */
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uint32_t sds_offset; /* start of sds ring [0 - #rings] content */
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};
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typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t;
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struct qla_driver_state {
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uint32_t size;
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void *buffer;
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};
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typedef struct qla_driver_state qla_driver_state_t;
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/*
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* Read/Write Register
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*/
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@ -133,4 +199,10 @@ typedef struct qla_rd_fw_dump qla_rd_fw_dump_t;
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*/
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#define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t)
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/*
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* Read Driver State
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*/
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#define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t)
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#endif /* #ifndef _QL_IOCTL_H_ */
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@ -492,6 +492,7 @@ qla_pci_attach(device_t dev)
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device_printf(dev, "%s: ql_minidump_init failed\n", __func__);
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goto qla_pci_attach_err;
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}
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ql_alloc_drvr_state_buffer(ha);
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/* create the o.s ethernet interface */
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qla_init_ifnet(dev, ha);
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@ -645,6 +646,7 @@ qla_release(qla_host_t *ha)
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if (ha->ifp != NULL)
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ether_ifdetach(ha->ifp);
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ql_free_drvr_state_buffer(ha);
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ql_free_dma(ha);
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qla_free_parent_dma_tag(ha);
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@ -36,6 +36,6 @@
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#define QLA_VERSION_MAJOR 3
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#define QLA_VERSION_MINOR 10
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#define QLA_VERSION_BUILD 34
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#define QLA_VERSION_BUILD 35
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#endif /* #ifndef _QL_VER_H_ */
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