How hard can it be to implement a 24bit counter in hardware ?
Make sure we read a likely value from the PIIX timecounter. This should fix a large fraction of the "calcru: negative time" warnings produced by SMP machines. Another hole in one by: bde Didn't belive Bruce: phk
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@ -6,6 +6,29 @@
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* Just when we thought life were beautiful, reality pops its grim face over
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* the edge again:
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*
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* ] 20. ACPI Timer Errata
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* ]
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* ] Problem: The power management timer may return improper result when
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* ] read. Although the timer value settles properly after incrementing,
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* ] while incrementing there is a 3nS window every 69.8nS where the
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* ] timer value is indeterminate (a 4.2% chance that the data will be
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* ] incorrect when read). As a result, the ACPI free running count up
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* ] timer specification is violated due to erroneous reads. Implication:
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* ] System hangs due to the "inaccuracy" of the timer when used by
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* ] software for time critical events and delays.
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* ]
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* ] Workaround: Read the register twice and compare.
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* ] Status: This will not be fixed in the PIIX4 or PIIX4E.
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*
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* The counter is in other words not latched to the PCI bus clock when
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* read. Notice the workaround isn't: We need to read until we have
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* three monotonic samples and then use the middle one, otherwise we are
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* not protected against the fact that the bits can be wrong in two
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* directions. If we only cared about monosity two reads would be enough.
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*
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* $FreeBSD$
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*
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*/
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@ -63,7 +86,16 @@ SYSCTL_PROC(_machdep, OID_AUTO, piix_freq, CTLTYPE_INT | CTLFLAG_RW,
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static unsigned
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piix_get_timecount(struct timecounter *tc)
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{
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return (inl(piix_timecounter_address));
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unsigned u1, u2, u3;
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u2 = inl(piix_timecounter_address);
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u3 = inl(piix_timecounter_address);
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do {
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u1 = u2;
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u2 = u3;
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u3 = inl(piix_timecounter_address);
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} while (u1 > u2 || u2 > u3);
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return (u2);
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}
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static int
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