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arge_mdio: add explicit read barriers for MDIO_READs.

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The mips74k programmers guide notes that reads can be re-ordered, even
uncached ones, so we need an explicit SYNC between them.

Yes, this is a case of a driver author actively doing a bus barrier
operation.

This ends up being necessary when the mips74k core is run in write-back
mode rather than write-through mode.  That's coming in an upcoming
commit.

Tested:

* mips74k, QCA9558 SoC (AP135 reference board), arge<->arge interface
  routing traffic tests.
This commit is contained in:
Adrian Chadd 2015-10-30 23:00:47 +00:00
parent 47ed24efe2
commit ab2477c2c1
1 changed files with 7 additions and 2 deletions
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9
sys/mips/atheros/if_arge.c
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@ -1081,8 +1081,10 @@ arge_miibus_readreg(device_t dev, int phy, int reg)
i = ARGE_MII_TIMEOUT;
while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
MAC_MII_INDICATOR_BUSY) && (i--))
MAC_MII_INDICATOR_BUSY) && (i--)) {
ARGE_MDIO_BARRIER_READ(sc);
DELAY(5);
}
if (i < 0) {
mtx_unlock(&miibus_mtx);
@ -1092,6 +1094,7 @@ arge_miibus_readreg(device_t dev, int phy, int reg)
}
result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
ARGE_MDIO_BARRIER_READ(sc);
ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
mtx_unlock(&miibus_mtx);
@ -1119,8 +1122,10 @@ arge_miibus_writereg(device_t dev, int phy, int reg, int data)
i = ARGE_MII_TIMEOUT;
while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
MAC_MII_INDICATOR_BUSY) && (i--))
MAC_MII_INDICATOR_BUSY) && (i--)) {
ARGE_MDIO_BARRIER_READ(sc);
DELAY(5);
}
mtx_unlock(&miibus_mtx);