hwpmc: deorbit mips support
Sponsored by: Netflix
This commit is contained in:
Warner Losh
parent
373d5df3e3
commit
abae2c01c5
@ -1,540 +0,0 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_hwpmc_hooks.h"
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#include <sys/param.h>
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#include <sys/pmckern.h>
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#include <dev/hwpmc/hwpmc_beri.h>
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#define BERI_NCOUNTERS 56
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#define BERI_PMC_CAPS (PMC_CAP_USER | PMC_CAP_SYSTEM | \
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PMC_CAP_READ | PMC_CAP_WRITE )
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struct beri_event_code_map {
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uint32_t pe_ev; /* enum value */
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uint64_t (*get_func)(void);
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};
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const struct beri_event_code_map beri_event_codes[BERI_NCOUNTERS] = {
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{ PMC_EV_BERI_CYCLE,
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statcounters_get_cycle_count },
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{ PMC_EV_BERI_INST,
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statcounters_get_inst_count },
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{ PMC_EV_BERI_INST_USER,
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statcounters_get_inst_user_count },
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{ PMC_EV_BERI_INST_KERNEL,
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statcounters_get_inst_kernel_count },
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{ PMC_EV_BERI_IMPRECISE_SETBOUNDS,
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statcounters_get_imprecise_setbounds_count },
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{ PMC_EV_BERI_UNREPRESENTABLE_CAPS,
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statcounters_get_unrepresentable_caps_count },
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{ PMC_EV_BERI_ITLB_MISS,
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statcounters_get_itlb_miss_count },
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{ PMC_EV_BERI_DTLB_MISS,
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statcounters_get_dtlb_miss_count },
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{ PMC_EV_BERI_ICACHE_WRITE_HIT,
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statcounters_get_icache_write_hit_count },
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{ PMC_EV_BERI_ICACHE_WRITE_MISS,
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statcounters_get_icache_write_miss_count },
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{ PMC_EV_BERI_ICACHE_READ_HIT,
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statcounters_get_icache_read_hit_count },
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{ PMC_EV_BERI_ICACHE_READ_MISS,
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statcounters_get_icache_read_miss_count },
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{ PMC_EV_BERI_ICACHE_EVICT,
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statcounters_get_icache_evict_count },
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{ PMC_EV_BERI_DCACHE_WRITE_HIT,
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statcounters_get_dcache_write_hit_count },
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{ PMC_EV_BERI_DCACHE_WRITE_MISS,
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statcounters_get_dcache_write_miss_count },
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{ PMC_EV_BERI_DCACHE_READ_HIT,
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statcounters_get_dcache_read_hit_count },
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{ PMC_EV_BERI_DCACHE_READ_MISS,
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statcounters_get_dcache_read_miss_count },
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{ PMC_EV_BERI_DCACHE_EVICT,
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statcounters_get_dcache_evict_count },
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{ PMC_EV_BERI_DCACHE_SET_TAG_WRITE,
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statcounters_get_dcache_set_tag_write_count },
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{ PMC_EV_BERI_DCACHE_SET_TAG_READ,
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statcounters_get_dcache_set_tag_read_count },
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{ PMC_EV_BERI_L2CACHE_WRITE_HIT,
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statcounters_get_l2cache_write_hit_count },
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{ PMC_EV_BERI_L2CACHE_WRITE_MISS,
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statcounters_get_l2cache_write_miss_count },
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{ PMC_EV_BERI_L2CACHE_READ_HIT,
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statcounters_get_l2cache_read_hit_count },
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{ PMC_EV_BERI_L2CACHE_READ_MISS,
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statcounters_get_l2cache_read_miss_count },
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{ PMC_EV_BERI_L2CACHE_EVICT,
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statcounters_get_l2cache_evict_count },
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{ PMC_EV_BERI_L2CACHE_SET_TAG_WRITE,
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statcounters_get_l2cache_set_tag_write_count },
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{ PMC_EV_BERI_L2CACHE_SET_TAG_READ,
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statcounters_get_l2cache_set_tag_read_count },
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{ PMC_EV_BERI_MEM_BYTE_READ,
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statcounters_get_mem_byte_read_count },
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{ PMC_EV_BERI_MEM_BYTE_WRITE,
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statcounters_get_mem_byte_write_count },
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{ PMC_EV_BERI_MEM_HWORD_READ,
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statcounters_get_mem_hword_read_count },
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{ PMC_EV_BERI_MEM_HWORD_WRITE,
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statcounters_get_mem_hword_write_count },
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{ PMC_EV_BERI_MEM_WORD_READ,
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statcounters_get_mem_word_read_count },
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{ PMC_EV_BERI_MEM_WORD_WRITE,
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statcounters_get_mem_word_write_count },
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{ PMC_EV_BERI_MEM_DWORD_READ,
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statcounters_get_mem_dword_read_count },
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{ PMC_EV_BERI_MEM_DWORD_WRITE,
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statcounters_get_mem_dword_write_count },
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{ PMC_EV_BERI_MEM_CAP_READ,
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statcounters_get_mem_cap_read_count },
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{ PMC_EV_BERI_MEM_CAP_WRITE,
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statcounters_get_mem_cap_write_count },
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{ PMC_EV_BERI_MEM_CAP_READ_TAG_SET,
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statcounters_get_mem_cap_read_tag_set_count },
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{ PMC_EV_BERI_MEM_CAP_WRITE_TAG_SET,
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statcounters_get_mem_cap_write_tag_set_count },
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{ PMC_EV_BERI_TAGCACHE_WRITE_HIT,
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statcounters_get_tagcache_write_hit_count },
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{ PMC_EV_BERI_TAGCACHE_WRITE_MISS,
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statcounters_get_tagcache_write_miss_count },
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{ PMC_EV_BERI_TAGCACHE_READ_HIT,
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statcounters_get_tagcache_read_hit_count },
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{ PMC_EV_BERI_TAGCACHE_READ_MISS,
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statcounters_get_tagcache_read_miss_count },
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{ PMC_EV_BERI_TAGCACHE_EVICT,
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statcounters_get_tagcache_evict_count },
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{ PMC_EV_BERI_L2CACHEMASTER_READ_REQ,
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statcounters_get_l2cachemaster_read_req_count },
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{ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ,
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statcounters_get_l2cachemaster_write_req_count },
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{ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLIT,
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statcounters_get_l2cachemaster_write_req_flit_count },
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{ PMC_EV_BERI_L2CACHEMASTER_READ_RSP,
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statcounters_get_l2cachemaster_read_rsp_count },
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{ PMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLIT,
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statcounters_get_l2cachemaster_read_rsp_flit_count },
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{ PMC_EV_BERI_L2CACHEMASTER_WRITE_RSP,
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statcounters_get_l2cachemaster_write_rsp_count },
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{ PMC_EV_BERI_TAGCACHEMASTER_READ_REQ,
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statcounters_get_tagcachemaster_read_req_count },
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{ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ,
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statcounters_get_tagcachemaster_write_req_count },
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{ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLIT,
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statcounters_get_tagcachemaster_write_req_flit_count },
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{ PMC_EV_BERI_TAGCACHEMASTER_READ_RSP,
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statcounters_get_tagcachemaster_read_rsp_count },
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{ PMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLIT,
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statcounters_get_tagcachemaster_read_rsp_flit_count },
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{ PMC_EV_BERI_TAGCACHEMASTER_WRITE_RSP,
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statcounters_get_tagcachemaster_write_rsp_count },
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};
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struct mips_pmc_spec beri_pmc_spec = {
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.ps_cpuclass = PMC_CLASS_BERI,
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.ps_cputype = PMC_CPU_MIPS_BERI,
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.ps_capabilities = BERI_PMC_CAPS,
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.ps_counter_width = 64
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};
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/*
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* Per-processor information.
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*/
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struct beri_cpu {
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struct pmc_hw *pc_beripmcs;
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uint64_t start_values[BERI_NCOUNTERS];
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uint64_t stop_values[BERI_NCOUNTERS];
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uint64_t saved_values[BERI_NCOUNTERS];
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};
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int beri_npmcs;
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static struct beri_cpu **beri_pcpu;
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static int
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beri_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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uint32_t config;
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int i;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[beri,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < beri_npmcs,
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("[beri,%d] illegal row index %d", __LINE__, ri));
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if (a->pm_class != beri_pmc_spec.ps_cpuclass)
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return (EINVAL);
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for (i = 0; i < BERI_NCOUNTERS; i++) {
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if (beri_event_codes[i].pe_ev == a->pm_ev) {
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config = i;
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break;
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}
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}
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if (i == BERI_NCOUNTERS)
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return (EINVAL);
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pm->pm_md.pm_mips_evsel = config;
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PMCDBG2(MDP,ALL,2,"beri-allocate ri=%d -> config=0x%x", ri, config);
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return (0);
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}
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static int
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beri_read_pmc(int cpu, int ri, pmc_value_t *v)
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{
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uint32_t config;
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struct pmc *pm;
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pmc_value_t new;
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pmc_value_t start_val;
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pmc_value_t stop_val;
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pmc_value_t saved_val;
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pmc_value_t result;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[beri,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < beri_npmcs,
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("[beri,%d] illegal row index %d", __LINE__, ri));
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pm = beri_pcpu[cpu]->pc_beripmcs[ri].phw_pmc;
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config = pm->pm_md.pm_mips_evsel;
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start_val = beri_pcpu[cpu]->start_values[config];
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if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
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stop_val = beri_event_codes[config].get_func();
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} else
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stop_val = beri_pcpu[cpu]->stop_values[config];
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if (start_val <= stop_val)
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result = stop_val - start_val;
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else {
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if (config == 0) /* CYCLE counter is 48 bit */
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result = 0x00ffffffffffffffUL;
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else
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result = 0xffffffffffffffffUL;
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result -= start_val;
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result += stop_val;
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}
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saved_val = beri_pcpu[cpu]->saved_values[config];
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*v = result + saved_val;
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return (0);
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}
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static int
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beri_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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struct pmc *pm;
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uint32_t config;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[beri,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < beri_npmcs,
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("[beri,%d] illegal row-index %d", __LINE__, ri));
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pm = beri_pcpu[cpu]->pc_beripmcs[ri].phw_pmc;
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config = pm->pm_md.pm_mips_evsel;
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = (1UL << (beri_pmc_spec.ps_counter_width - 1)) - v;
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PMCDBG3(MDP,WRI,1,"beri-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm)))
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beri_pcpu[cpu]->saved_values[config] = 0;
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else
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beri_pcpu[cpu]->saved_values[config] = v;
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return (0);
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}
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static int
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beri_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[beri,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < beri_npmcs,
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("[beri,%d] illegal row-index %d", __LINE__, ri));
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phw = &beri_pcpu[cpu]->pc_beripmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[beri,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return (0);
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}
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static int
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beri_start_pmc(int cpu, int ri)
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{
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uint32_t config;
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struct pmc *pm;
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struct pmc_hw *phw;
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pmc_value_t v;
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phw = &beri_pcpu[cpu]->pc_beripmcs[ri];
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pm = phw->phw_pmc;
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config = pm->pm_md.pm_mips_evsel;
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v = beri_event_codes[config].get_func();
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beri_pcpu[cpu]->start_values[config] = v;
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return (0);
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}
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static int
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beri_stop_pmc(int cpu, int ri)
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{
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uint32_t config;
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struct pmc *pm;
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struct pmc_hw *phw;
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pmc_value_t v;
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phw = &beri_pcpu[cpu]->pc_beripmcs[ri];
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pm = phw->phw_pmc;
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config = pm->pm_md.pm_mips_evsel;
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v = beri_event_codes[config].get_func();
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beri_pcpu[cpu]->stop_values[config] = v;
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return (0);
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}
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static int
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beri_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[beri,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < beri_npmcs,
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("[beri,%d] illegal row-index %d", __LINE__, ri));
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phw = &beri_pcpu[cpu]->pc_beripmcs[ri];
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KASSERT(phw->phw_pmc == NULL,
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("[beri,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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return (0);
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}
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static int
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beri_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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struct pmc_hw *phw;
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char beri_name[PMC_NAME_MAX];
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int error;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[beri,%d], illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < beri_npmcs,
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("[beri,%d] row-index %d out of range", __LINE__, ri));
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phw = &beri_pcpu[cpu]->pc_beripmcs[ri];
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snprintf(beri_name, sizeof(beri_name), "MIPS-%d", ri);
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if ((error = copystr(beri_name, pi->pm_name, PMC_NAME_MAX,
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NULL)) != 0)
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return error;
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pi->pm_class = beri_pmc_spec.ps_cpuclass;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
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pi->pm_enabled = TRUE;
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*ppmc = phw->phw_pmc;
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} else {
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pi->pm_enabled = FALSE;
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*ppmc = NULL;
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}
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return (0);
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}
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static int
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beri_get_config(int cpu, int ri, struct pmc **ppm)
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{
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*ppm = beri_pcpu[cpu]->pc_beripmcs[ri].phw_pmc;
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return (0);
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}
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static int
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beri_pmc_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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return (0);
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}
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static int
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beri_pmc_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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return (0);
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}
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||||
|
||||
static int
|
||||
beri_pcpu_init(struct pmc_mdep *md, int cpu)
|
||||
{
|
||||
int first_ri, i;
|
||||
struct pmc_cpu *pc;
|
||||
struct beri_cpu *pac;
|
||||
struct pmc_hw *phw;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[beri,%d] wrong cpu number %d", __LINE__, cpu));
|
||||
PMCDBG1(MDP,INI,1,"beri-init cpu=%d", cpu);
|
||||
|
||||
beri_pcpu[cpu] = pac = malloc(sizeof(struct beri_cpu), M_PMC,
|
||||
M_WAITOK|M_ZERO);
|
||||
pac->pc_beripmcs = malloc(sizeof(struct pmc_hw) * beri_npmcs,
|
||||
M_PMC, M_WAITOK|M_ZERO);
|
||||
pc = pmc_pcpu[cpu];
|
||||
first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS].pcd_ri;
|
||||
KASSERT(pc != NULL, ("[beri,%d] NULL per-cpu pointer", __LINE__));
|
||||
|
||||
for (i = 0, phw = pac->pc_beripmcs; i < beri_npmcs; i++, phw++) {
|
||||
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
||||
PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
|
||||
phw->phw_pmc = NULL;
|
||||
pc->pc_hwpmcs[i + first_ri] = phw;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
beri_pcpu_fini(struct pmc_mdep *md, int cpu)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
struct pmc_mdep *
|
||||
pmc_beri_initialize()
|
||||
{
|
||||
struct pmc_mdep *pmc_mdep;
|
||||
struct pmc_classdep *pcd;
|
||||
|
||||
snprintf(pmc_cpuid, sizeof(pmc_cpuid), "beri");
|
||||
|
||||
beri_npmcs = 2;
|
||||
|
||||
PMCDBG1(MDP,INI,1,"beri-init npmcs=%d", beri_npmcs);
|
||||
|
||||
/*
|
||||
* Allocate space for pointers to PMC HW descriptors and for
|
||||
* the MDEP structure used by MI code.
|
||||
*/
|
||||
beri_pcpu = malloc(sizeof(struct beri_cpu *) * pmc_cpu_max(), M_PMC,
|
||||
M_WAITOK|M_ZERO);
|
||||
|
||||
/* Just one class */
|
||||
pmc_mdep = pmc_mdep_alloc(1);
|
||||
|
||||
pmc_mdep->pmd_cputype = beri_pmc_spec.ps_cputype;
|
||||
|
||||
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS];
|
||||
pcd->pcd_caps = beri_pmc_spec.ps_capabilities;
|
||||
pcd->pcd_class = beri_pmc_spec.ps_cpuclass;
|
||||
pcd->pcd_num = beri_npmcs;
|
||||
pcd->pcd_ri = pmc_mdep->pmd_npmc;
|
||||
pcd->pcd_width = beri_pmc_spec.ps_counter_width;
|
||||
|
||||
pcd->pcd_allocate_pmc = beri_allocate_pmc;
|
||||
pcd->pcd_config_pmc = beri_config_pmc;
|
||||
pcd->pcd_pcpu_fini = beri_pcpu_fini;
|
||||
pcd->pcd_pcpu_init = beri_pcpu_init;
|
||||
pcd->pcd_describe = beri_describe;
|
||||
pcd->pcd_get_config = beri_get_config;
|
||||
pcd->pcd_read_pmc = beri_read_pmc;
|
||||
pcd->pcd_release_pmc = beri_release_pmc;
|
||||
pcd->pcd_start_pmc = beri_start_pmc;
|
||||
pcd->pcd_stop_pmc = beri_stop_pmc;
|
||||
pcd->pcd_write_pmc = beri_write_pmc;
|
||||
|
||||
pmc_mdep->pmd_intr = NULL;
|
||||
pmc_mdep->pmd_switch_in = beri_pmc_switch_in;
|
||||
pmc_mdep->pmd_switch_out = beri_pmc_switch_out;
|
||||
|
||||
pmc_mdep->pmd_npmc += beri_npmcs;
|
||||
|
||||
return (pmc_mdep);
|
||||
}
|
||||
|
||||
void
|
||||
pmc_beri_finalize(struct pmc_mdep *md)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
struct pmc_mdep *
|
||||
pmc_md_initialize()
|
||||
{
|
||||
|
||||
return (pmc_beri_initialize());
|
||||
}
|
||||
|
||||
void
|
||||
pmc_md_finalize(struct pmc_mdep *md)
|
||||
{
|
||||
|
||||
return (pmc_beri_finalize(md));
|
||||
}
|
||||
|
||||
int
|
||||
pmc_save_kernel_callchain(uintptr_t *cc, int nframes,
|
||||
struct trapframe *tf)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
pmc_save_user_callchain(uintptr_t *cc, int nframes,
|
||||
struct trapframe *tf)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -1,107 +0,0 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Alex Richardson
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory (Department of Computer Science and
|
||||
* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
|
||||
* DARPA SSITH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_HWPMC_HWPMC_BERI_H_
|
||||
#define _DEV_HWPMC_HWPMC_BERI_H_
|
||||
|
||||
#define STATCOUNTER_ITEM(name, X, Y) \
|
||||
static inline uint64_t statcounters_get_##name##_count(void) \
|
||||
{ \
|
||||
uint64_t ret; \
|
||||
__asm __volatile( \
|
||||
".word (0x1f << 26) | (0x0 << 21) | \
|
||||
(12 << 16) | ("#X" << 11) | \
|
||||
( "#Y" << 6) | 0x3b\n\t" \
|
||||
"move %0,$12" : "=r" (ret) :: "$12"); \
|
||||
return (ret); \
|
||||
}
|
||||
|
||||
STATCOUNTER_ITEM(cycle,2,0)
|
||||
STATCOUNTER_ITEM(inst,4,0)
|
||||
STATCOUNTER_ITEM(inst_user,4,1)
|
||||
STATCOUNTER_ITEM(inst_kernel,4,2)
|
||||
STATCOUNTER_ITEM(imprecise_setbounds,4,3)
|
||||
STATCOUNTER_ITEM(unrepresentable_caps,4,4)
|
||||
STATCOUNTER_ITEM(itlb_miss,5,0)
|
||||
STATCOUNTER_ITEM(dtlb_miss,6,0)
|
||||
STATCOUNTER_ITEM(icache_write_hit,8,0)
|
||||
STATCOUNTER_ITEM(icache_write_miss,8,1)
|
||||
STATCOUNTER_ITEM(icache_read_hit,8,2)
|
||||
STATCOUNTER_ITEM(icache_read_miss,8,3)
|
||||
STATCOUNTER_ITEM(icache_evict,8,6)
|
||||
STATCOUNTER_ITEM(dcache_write_hit,9,0)
|
||||
STATCOUNTER_ITEM(dcache_write_miss,9,1)
|
||||
STATCOUNTER_ITEM(dcache_read_hit,9,2)
|
||||
STATCOUNTER_ITEM(dcache_read_miss,9,3)
|
||||
STATCOUNTER_ITEM(dcache_evict,9,6)
|
||||
STATCOUNTER_ITEM(dcache_set_tag_write,9,8)
|
||||
STATCOUNTER_ITEM(dcache_set_tag_read,9,9)
|
||||
STATCOUNTER_ITEM(l2cache_write_hit,10,0)
|
||||
STATCOUNTER_ITEM(l2cache_write_miss,10,1)
|
||||
STATCOUNTER_ITEM(l2cache_read_hit,10,2)
|
||||
STATCOUNTER_ITEM(l2cache_read_miss,10,3)
|
||||
STATCOUNTER_ITEM(l2cache_evict,10,6)
|
||||
STATCOUNTER_ITEM(l2cache_set_tag_write,10,8)
|
||||
STATCOUNTER_ITEM(l2cache_set_tag_read,10,9)
|
||||
STATCOUNTER_ITEM(mem_byte_read,11,0)
|
||||
STATCOUNTER_ITEM(mem_byte_write,11,1)
|
||||
STATCOUNTER_ITEM(mem_hword_read,11,2)
|
||||
STATCOUNTER_ITEM(mem_hword_write,11,3)
|
||||
STATCOUNTER_ITEM(mem_word_read,11,4)
|
||||
STATCOUNTER_ITEM(mem_word_write,11,5)
|
||||
STATCOUNTER_ITEM(mem_dword_read,11,6)
|
||||
STATCOUNTER_ITEM(mem_dword_write,11,7)
|
||||
STATCOUNTER_ITEM(mem_cap_read,11,8)
|
||||
STATCOUNTER_ITEM(mem_cap_write,11,9)
|
||||
STATCOUNTER_ITEM(mem_cap_read_tag_set,11,10)
|
||||
STATCOUNTER_ITEM(mem_cap_write_tag_set,11,11)
|
||||
STATCOUNTER_ITEM(tagcache_write_hit,12,0)
|
||||
STATCOUNTER_ITEM(tagcache_write_miss,12,1)
|
||||
STATCOUNTER_ITEM(tagcache_read_hit,12,2)
|
||||
STATCOUNTER_ITEM(tagcache_read_miss,12,3)
|
||||
STATCOUNTER_ITEM(tagcache_evict,12,6)
|
||||
STATCOUNTER_ITEM(l2cachemaster_read_req,13,0)
|
||||
STATCOUNTER_ITEM(l2cachemaster_write_req,13,1)
|
||||
STATCOUNTER_ITEM(l2cachemaster_write_req_flit,13,2)
|
||||
STATCOUNTER_ITEM(l2cachemaster_read_rsp,13,3)
|
||||
STATCOUNTER_ITEM(l2cachemaster_read_rsp_flit,13,4)
|
||||
STATCOUNTER_ITEM(l2cachemaster_write_rsp,13,5)
|
||||
STATCOUNTER_ITEM(tagcachemaster_read_req,14,0)
|
||||
STATCOUNTER_ITEM(tagcachemaster_write_req,14,1)
|
||||
STATCOUNTER_ITEM(tagcachemaster_write_req_flit,14,2)
|
||||
STATCOUNTER_ITEM(tagcachemaster_read_rsp,14,3)
|
||||
STATCOUNTER_ITEM(tagcachemaster_read_rsp_flit,14,4)
|
||||
STATCOUNTER_ITEM(tagcachemaster_write_rsp,14,5)
|
||||
|
||||
#endif /* !_DEV_HWPMC_HWPMC_BERI_H_ */
|
||||
@ -1,809 +0,0 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 2010, George V. Neville-Neil <gnn@freebsd.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "opt_hwpmc_hooks.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/pmc.h>
|
||||
#include <sys/pmckern.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <machine/pmc_mdep.h>
|
||||
#include <machine/md_var.h>
|
||||
#include <machine/mips_opcode.h>
|
||||
#include <machine/vmparam.h>
|
||||
|
||||
int mips_npmcs;
|
||||
|
||||
/*
|
||||
* Per-processor information.
|
||||
*/
|
||||
struct mips_cpu {
|
||||
struct pmc_hw *pc_mipspmcs;
|
||||
};
|
||||
|
||||
static struct mips_cpu **mips_pcpu;
|
||||
|
||||
#if defined(__mips_n64)
|
||||
# define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
|
||||
((vm_offset_t)(reg) >= MIPS_XKPHYS_START))
|
||||
#else
|
||||
# define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
|
||||
((vm_offset_t)(reg) >= MIPS_KSEG0_START))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We need some reasonable default to prevent backtrace code
|
||||
* from wandering too far
|
||||
*/
|
||||
#define MAX_FUNCTION_SIZE 0x10000
|
||||
#define MAX_PROLOGUE_SIZE 0x100
|
||||
|
||||
static int
|
||||
mips_allocate_pmc(int cpu, int ri, struct pmc *pm,
|
||||
const struct pmc_op_pmcallocate *a)
|
||||
{
|
||||
enum pmc_event pe;
|
||||
uint32_t caps, config, counter;
|
||||
uint32_t event;
|
||||
int i;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] illegal CPU value %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] illegal row index %d", __LINE__, ri));
|
||||
|
||||
caps = a->pm_caps;
|
||||
if (a->pm_class != mips_pmc_spec.ps_cpuclass)
|
||||
return (EINVAL);
|
||||
pe = a->pm_ev;
|
||||
counter = MIPS_CTR_ALL;
|
||||
event = 0;
|
||||
for (i = 0; i < mips_event_codes_size; i++) {
|
||||
if (mips_event_codes[i].pe_ev == pe) {
|
||||
event = mips_event_codes[i].pe_code;
|
||||
counter = mips_event_codes[i].pe_counter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == mips_event_codes_size)
|
||||
return (EINVAL);
|
||||
|
||||
if ((counter != MIPS_CTR_ALL) && (counter != ri))
|
||||
return (EINVAL);
|
||||
|
||||
config = mips_get_perfctl(cpu, ri, event, caps);
|
||||
|
||||
pm->pm_md.pm_mips_evsel = config;
|
||||
|
||||
PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri, config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
mips_read_pmc(int cpu, int ri, pmc_value_t *v)
|
||||
{
|
||||
struct pmc *pm;
|
||||
pmc_value_t tmp;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] illegal CPU value %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] illegal row index %d", __LINE__, ri));
|
||||
|
||||
pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
|
||||
tmp = mips_pmcn_read(ri);
|
||||
PMCDBG2(MDP,REA,2,"mips-read id=%d -> %jd", ri, tmp);
|
||||
|
||||
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
|
||||
*v = tmp - (1UL << (mips_pmc_spec.ps_counter_width - 1));
|
||||
else
|
||||
*v = tmp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_write_pmc(int cpu, int ri, pmc_value_t v)
|
||||
{
|
||||
struct pmc *pm;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] illegal CPU value %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] illegal row-index %d", __LINE__, ri));
|
||||
|
||||
pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
|
||||
|
||||
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
|
||||
v = (1UL << (mips_pmc_spec.ps_counter_width - 1)) - v;
|
||||
|
||||
PMCDBG3(MDP,WRI,1,"mips-write cpu=%d ri=%d v=%jx", cpu, ri, v);
|
||||
|
||||
mips_pmcn_write(ri, v);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_config_pmc(int cpu, int ri, struct pmc *pm)
|
||||
{
|
||||
struct pmc_hw *phw;
|
||||
|
||||
PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] illegal CPU value %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] illegal row-index %d", __LINE__, ri));
|
||||
|
||||
phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
|
||||
|
||||
KASSERT(pm == NULL || phw->phw_pmc == NULL,
|
||||
("[mips,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
|
||||
__LINE__, pm, phw->phw_pmc));
|
||||
|
||||
phw->phw_pmc = pm;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_start_pmc(int cpu, int ri)
|
||||
{
|
||||
uint32_t config;
|
||||
struct pmc *pm;
|
||||
struct pmc_hw *phw;
|
||||
|
||||
phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
|
||||
pm = phw->phw_pmc;
|
||||
config = pm->pm_md.pm_mips_evsel;
|
||||
|
||||
/* Enable the PMC. */
|
||||
switch (ri) {
|
||||
case 0:
|
||||
mips_wr_perfcnt0(config);
|
||||
break;
|
||||
case 1:
|
||||
mips_wr_perfcnt2(config);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_stop_pmc(int cpu, int ri)
|
||||
{
|
||||
struct pmc *pm;
|
||||
struct pmc_hw *phw;
|
||||
|
||||
phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
|
||||
pm = phw->phw_pmc;
|
||||
|
||||
/*
|
||||
* Disable the PMCs.
|
||||
*
|
||||
* Clearing the entire register turns the counter off as well
|
||||
* as removes the previously sampled event.
|
||||
*/
|
||||
switch (ri) {
|
||||
case 0:
|
||||
mips_wr_perfcnt0(0);
|
||||
break;
|
||||
case 1:
|
||||
mips_wr_perfcnt2(0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_release_pmc(int cpu, int ri, struct pmc *pmc)
|
||||
{
|
||||
struct pmc_hw *phw;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] illegal CPU value %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] illegal row-index %d", __LINE__, ri));
|
||||
|
||||
phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
|
||||
KASSERT(phw->phw_pmc == NULL,
|
||||
("[mips,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_pmc_intr(struct trapframe *tf)
|
||||
{
|
||||
int error;
|
||||
int retval, ri, cpu;
|
||||
struct pmc *pm;
|
||||
struct mips_cpu *pc;
|
||||
uint32_t r0, r2;
|
||||
pmc_value_t r;
|
||||
|
||||
cpu = curcpu;
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] CPU %d out of range", __LINE__, cpu));
|
||||
|
||||
retval = 0;
|
||||
pc = mips_pcpu[cpu];
|
||||
|
||||
/* Stop PMCs without clearing the counter */
|
||||
r0 = mips_rd_perfcnt0();
|
||||
mips_wr_perfcnt0(r0 & ~(0x1f));
|
||||
r2 = mips_rd_perfcnt2();
|
||||
mips_wr_perfcnt2(r2 & ~(0x1f));
|
||||
|
||||
for (ri = 0; ri < mips_npmcs; ri++) {
|
||||
pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
|
||||
if (pm == NULL)
|
||||
continue;
|
||||
if (! PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
|
||||
continue;
|
||||
|
||||
r = mips_pmcn_read(ri);
|
||||
|
||||
/* If bit 31 is set, the counter has overflowed */
|
||||
if ((r & (1UL << (mips_pmc_spec.ps_counter_width - 1))) == 0)
|
||||
continue;
|
||||
|
||||
retval = 1;
|
||||
if (pm->pm_state != PMC_STATE_RUNNING)
|
||||
continue;
|
||||
error = pmc_process_interrupt(PMC_HR, pm, tf);
|
||||
if (error) {
|
||||
/* Clear/disable the relevant counter */
|
||||
if (ri == 0)
|
||||
r0 = 0;
|
||||
else if (ri == 1)
|
||||
r2 = 0;
|
||||
mips_stop_pmc(cpu, ri);
|
||||
}
|
||||
|
||||
/* Reload sampling count */
|
||||
mips_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
|
||||
}
|
||||
|
||||
/*
|
||||
* Re-enable the PMC counters where they left off.
|
||||
*
|
||||
* Any counter which overflowed will have its sample count
|
||||
* reloaded in the loop above.
|
||||
*/
|
||||
mips_wr_perfcnt0(r0);
|
||||
mips_wr_perfcnt2(r2);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
|
||||
{
|
||||
int error;
|
||||
struct pmc_hw *phw;
|
||||
char mips_name[PMC_NAME_MAX];
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d], illegal CPU %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] row-index %d out of range", __LINE__, ri));
|
||||
|
||||
phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
|
||||
snprintf(mips_name, sizeof(mips_name), "MIPS-%d", ri);
|
||||
if ((error = copystr(mips_name, pi->pm_name, PMC_NAME_MAX,
|
||||
NULL)) != 0)
|
||||
return error;
|
||||
pi->pm_class = mips_pmc_spec.ps_cpuclass;
|
||||
if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
|
||||
pi->pm_enabled = TRUE;
|
||||
*ppmc = phw->phw_pmc;
|
||||
} else {
|
||||
pi->pm_enabled = FALSE;
|
||||
*ppmc = NULL;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
mips_get_config(int cpu, int ri, struct pmc **ppm)
|
||||
{
|
||||
*ppm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX don't know what we should do here.
|
||||
*/
|
||||
static int
|
||||
mips_pmc_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_pmc_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_pcpu_init(struct pmc_mdep *md, int cpu)
|
||||
{
|
||||
int first_ri, i;
|
||||
struct pmc_cpu *pc;
|
||||
struct mips_cpu *pac;
|
||||
struct pmc_hw *phw;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] wrong cpu number %d", __LINE__, cpu));
|
||||
PMCDBG1(MDP,INI,1,"mips-init cpu=%d", cpu);
|
||||
|
||||
mips_pcpu[cpu] = pac = malloc(sizeof(struct mips_cpu), M_PMC,
|
||||
M_WAITOK|M_ZERO);
|
||||
pac->pc_mipspmcs = malloc(sizeof(struct pmc_hw) * mips_npmcs,
|
||||
M_PMC, M_WAITOK|M_ZERO);
|
||||
pc = pmc_pcpu[cpu];
|
||||
first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS].pcd_ri;
|
||||
KASSERT(pc != NULL, ("[mips,%d] NULL per-cpu pointer", __LINE__));
|
||||
|
||||
for (i = 0, phw = pac->pc_mipspmcs; i < mips_npmcs; i++, phw++) {
|
||||
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
||||
PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
|
||||
phw->phw_pmc = NULL;
|
||||
pc->pc_hwpmcs[i + first_ri] = phw;
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear the counter control register which has the effect
|
||||
* of disabling counting.
|
||||
*/
|
||||
for (i = 0; i < mips_npmcs; i++)
|
||||
mips_pmcn_write(i, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mips_pcpu_fini(struct pmc_mdep *md, int cpu)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pmc_mdep *
|
||||
pmc_mips_initialize()
|
||||
{
|
||||
struct pmc_mdep *pmc_mdep;
|
||||
struct pmc_classdep *pcd;
|
||||
|
||||
/*
|
||||
* TODO: Use More bit of PerfCntlX register to detect actual
|
||||
* number of counters
|
||||
*/
|
||||
mips_npmcs = 2;
|
||||
|
||||
PMCDBG1(MDP,INI,1,"mips-init npmcs=%d", mips_npmcs);
|
||||
|
||||
/*
|
||||
* Allocate space for pointers to PMC HW descriptors and for
|
||||
* the MDEP structure used by MI code.
|
||||
*/
|
||||
mips_pcpu = malloc(sizeof(struct mips_cpu *) * pmc_cpu_max(), M_PMC,
|
||||
M_WAITOK|M_ZERO);
|
||||
|
||||
/* Just one class */
|
||||
pmc_mdep = pmc_mdep_alloc(1);
|
||||
|
||||
pmc_mdep->pmd_cputype = mips_pmc_spec.ps_cputype;
|
||||
|
||||
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS];
|
||||
pcd->pcd_caps = mips_pmc_spec.ps_capabilities;
|
||||
pcd->pcd_class = mips_pmc_spec.ps_cpuclass;
|
||||
pcd->pcd_num = mips_npmcs;
|
||||
pcd->pcd_ri = pmc_mdep->pmd_npmc;
|
||||
pcd->pcd_width = mips_pmc_spec.ps_counter_width;
|
||||
|
||||
pcd->pcd_allocate_pmc = mips_allocate_pmc;
|
||||
pcd->pcd_config_pmc = mips_config_pmc;
|
||||
pcd->pcd_pcpu_fini = mips_pcpu_fini;
|
||||
pcd->pcd_pcpu_init = mips_pcpu_init;
|
||||
pcd->pcd_describe = mips_describe;
|
||||
pcd->pcd_get_config = mips_get_config;
|
||||
pcd->pcd_read_pmc = mips_read_pmc;
|
||||
pcd->pcd_release_pmc = mips_release_pmc;
|
||||
pcd->pcd_start_pmc = mips_start_pmc;
|
||||
pcd->pcd_stop_pmc = mips_stop_pmc;
|
||||
pcd->pcd_write_pmc = mips_write_pmc;
|
||||
|
||||
pmc_mdep->pmd_intr = mips_pmc_intr;
|
||||
pmc_mdep->pmd_switch_in = mips_pmc_switch_in;
|
||||
pmc_mdep->pmd_switch_out = mips_pmc_switch_out;
|
||||
|
||||
pmc_mdep->pmd_npmc += mips_npmcs;
|
||||
|
||||
return (pmc_mdep);
|
||||
}
|
||||
|
||||
void
|
||||
pmc_mips_finalize(struct pmc_mdep *md)
|
||||
{
|
||||
(void) md;
|
||||
}
|
||||
|
||||
#ifdef HWPMC_MIPS_BACKTRACE
|
||||
|
||||
static int
|
||||
pmc_next_frame(register_t *pc, register_t *sp)
|
||||
{
|
||||
InstFmt i;
|
||||
uintptr_t va;
|
||||
uint32_t instr, mask;
|
||||
int more, stksize;
|
||||
register_t ra = 0;
|
||||
|
||||
/* Jump here after a nonstandard (interrupt handler) frame */
|
||||
stksize = 0;
|
||||
|
||||
/* check for bad SP: could foul up next frame */
|
||||
if (!MIPS_IS_VALID_KERNELADDR(*sp)) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* check for bad PC */
|
||||
if (!MIPS_IS_VALID_KERNELADDR(*pc)) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find the beginning of the current subroutine by scanning
|
||||
* backwards from the current PC for the end of the previous
|
||||
* subroutine.
|
||||
*/
|
||||
va = *pc - sizeof(int);
|
||||
while (1) {
|
||||
instr = *((uint32_t *)va);
|
||||
|
||||
/* [d]addiu sp,sp,-X */
|
||||
if (((instr & 0xffff8000) == 0x27bd8000)
|
||||
|| ((instr & 0xffff8000) == 0x67bd8000))
|
||||
break;
|
||||
|
||||
/* jr ra */
|
||||
if (instr == 0x03e00008) {
|
||||
/* skip over branch-delay slot instruction */
|
||||
va += 2 * sizeof(int);
|
||||
break;
|
||||
}
|
||||
|
||||
va -= sizeof(int);
|
||||
}
|
||||
|
||||
/* skip over nulls which might separate .o files */
|
||||
while ((instr = *((uint32_t *)va)) == 0)
|
||||
va += sizeof(int);
|
||||
|
||||
/* scan forwards to find stack size and any saved registers */
|
||||
stksize = 0;
|
||||
more = 3;
|
||||
mask = 0;
|
||||
for (; more; va += sizeof(int),
|
||||
more = (more == 3) ? 3 : more - 1) {
|
||||
/* stop if hit our current position */
|
||||
if (va >= *pc)
|
||||
break;
|
||||
instr = *((uint32_t *)va);
|
||||
i.word = instr;
|
||||
switch (i.JType.op) {
|
||||
case OP_SPECIAL:
|
||||
switch (i.RType.func) {
|
||||
case OP_JR:
|
||||
case OP_JALR:
|
||||
more = 2; /* stop after next instruction */
|
||||
break;
|
||||
|
||||
case OP_SYSCALL:
|
||||
case OP_BREAK:
|
||||
more = 1; /* stop now */
|
||||
}
|
||||
break;
|
||||
|
||||
case OP_BCOND:
|
||||
case OP_J:
|
||||
case OP_JAL:
|
||||
case OP_BEQ:
|
||||
case OP_BNE:
|
||||
case OP_BLEZ:
|
||||
case OP_BGTZ:
|
||||
more = 2; /* stop after next instruction */
|
||||
break;
|
||||
|
||||
case OP_COP0:
|
||||
case OP_COP1:
|
||||
case OP_COP2:
|
||||
case OP_COP3:
|
||||
switch (i.RType.rs) {
|
||||
case OP_BCx:
|
||||
case OP_BCy:
|
||||
more = 2; /* stop after next instruction */
|
||||
}
|
||||
break;
|
||||
|
||||
case OP_SW:
|
||||
case OP_SD:
|
||||
/*
|
||||
* SP is being saved using S8(FP). Most likely it indicates
|
||||
* that SP is modified in the function and we can't get
|
||||
* its value safely without emulating code backward
|
||||
* So just bail out on functions like this
|
||||
*/
|
||||
if ((i.IType.rs == 30) && (i.IType.rt = 29))
|
||||
return (-1);
|
||||
|
||||
/* look for saved registers on the stack */
|
||||
if (i.IType.rs != 29)
|
||||
break;
|
||||
/* only restore the first one */
|
||||
if (mask & (1 << i.IType.rt))
|
||||
break;
|
||||
mask |= (1 << i.IType.rt);
|
||||
if (i.IType.rt == 31)
|
||||
ra = *((register_t *)(*sp + (short)i.IType.imm));
|
||||
break;
|
||||
|
||||
case OP_ADDI:
|
||||
case OP_ADDIU:
|
||||
case OP_DADDI:
|
||||
case OP_DADDIU:
|
||||
/* look for stack pointer adjustment */
|
||||
if (i.IType.rs != 29 || i.IType.rt != 29)
|
||||
break;
|
||||
stksize = -((short)i.IType.imm);
|
||||
}
|
||||
}
|
||||
|
||||
if (!MIPS_IS_VALID_KERNELADDR(ra))
|
||||
return (-1);
|
||||
|
||||
*pc = ra;
|
||||
*sp += stksize;
|
||||
|
||||
return (0);
|
||||
|
||||
error:
|
||||
return (-1);
|
||||
}
|
||||
|
||||
static int
|
||||
pmc_next_uframe(register_t *pc, register_t *sp, register_t *ra)
|
||||
{
|
||||
int offset, registers_on_stack;
|
||||
uint32_t opcode, mask;
|
||||
register_t function_start;
|
||||
int stksize;
|
||||
InstFmt i;
|
||||
|
||||
registers_on_stack = 0;
|
||||
mask = 0;
|
||||
function_start = 0;
|
||||
offset = 0;
|
||||
stksize = 0;
|
||||
|
||||
while (offset < MAX_FUNCTION_SIZE) {
|
||||
opcode = fuword32((void *)(*pc - offset));
|
||||
|
||||
/* [d]addiu sp, sp, -X*/
|
||||
if (((opcode & 0xffff8000) == 0x27bd8000)
|
||||
|| ((opcode & 0xffff8000) == 0x67bd8000)) {
|
||||
function_start = *pc - offset;
|
||||
registers_on_stack = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
/* lui gp, X */
|
||||
if ((opcode & 0xffff8000) == 0x3c1c0000) {
|
||||
/*
|
||||
* Function might start with this instruction
|
||||
* Keep an eye on "jr ra" and sp correction
|
||||
* with positive value further on
|
||||
*/
|
||||
function_start = *pc - offset;
|
||||
}
|
||||
|
||||
if (function_start) {
|
||||
/*
|
||||
* Stop looking further. Possible end of
|
||||
* function instruction: it means there is no
|
||||
* stack modifications, sp is unchanged
|
||||
*/
|
||||
|
||||
/* [d]addiu sp,sp,X */
|
||||
if (((opcode & 0xffff8000) == 0x27bd0000)
|
||||
|| ((opcode & 0xffff8000) == 0x67bd0000))
|
||||
break;
|
||||
|
||||
if (opcode == 0x03e00008)
|
||||
break;
|
||||
}
|
||||
|
||||
offset += sizeof(int);
|
||||
}
|
||||
|
||||
if (!function_start)
|
||||
return (-1);
|
||||
|
||||
if (registers_on_stack) {
|
||||
offset = 0;
|
||||
while ((offset < MAX_PROLOGUE_SIZE)
|
||||
&& ((function_start + offset) < *pc)) {
|
||||
i.word = fuword32((void *)(function_start + offset));
|
||||
switch (i.JType.op) {
|
||||
case OP_SW:
|
||||
/* look for saved registers on the stack */
|
||||
if (i.IType.rs != 29)
|
||||
break;
|
||||
/* only restore the first one */
|
||||
if (mask & (1 << i.IType.rt))
|
||||
break;
|
||||
mask |= (1 << i.IType.rt);
|
||||
if (i.IType.rt == 31)
|
||||
*ra = fuword32((void *)(*sp + (short)i.IType.imm));
|
||||
break;
|
||||
|
||||
#if defined(__mips_n64)
|
||||
case OP_SD:
|
||||
/* look for saved registers on the stack */
|
||||
if (i.IType.rs != 29)
|
||||
break;
|
||||
/* only restore the first one */
|
||||
if (mask & (1 << i.IType.rt))
|
||||
break;
|
||||
mask |= (1 << i.IType.rt);
|
||||
/* ra */
|
||||
if (i.IType.rt == 31)
|
||||
*ra = fuword64((void *)(*sp + (short)i.IType.imm));
|
||||
break;
|
||||
#endif
|
||||
|
||||
case OP_ADDI:
|
||||
case OP_ADDIU:
|
||||
case OP_DADDI:
|
||||
case OP_DADDIU:
|
||||
/* look for stack pointer adjustment */
|
||||
if (i.IType.rs != 29 || i.IType.rt != 29)
|
||||
break;
|
||||
stksize = -((short)i.IType.imm);
|
||||
}
|
||||
|
||||
offset += sizeof(int);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* We reached the end of backtrace
|
||||
*/
|
||||
if (*pc == *ra)
|
||||
return (-1);
|
||||
|
||||
*pc = *ra;
|
||||
*sp += stksize;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#endif /* HWPMC_MIPS_BACKTRACE */
|
||||
|
||||
struct pmc_mdep *
|
||||
pmc_md_initialize()
|
||||
{
|
||||
return pmc_mips_initialize();
|
||||
}
|
||||
|
||||
void
|
||||
pmc_md_finalize(struct pmc_mdep *md)
|
||||
{
|
||||
return pmc_mips_finalize(md);
|
||||
}
|
||||
|
||||
int
|
||||
pmc_save_kernel_callchain(uintptr_t *cc, int nframes,
|
||||
struct trapframe *tf)
|
||||
{
|
||||
register_t pc, ra, sp;
|
||||
int frames = 0;
|
||||
|
||||
pc = tf->pc;
|
||||
sp = tf->sp;
|
||||
ra = tf->ra;
|
||||
|
||||
cc[frames++] = pc;
|
||||
|
||||
#ifdef HWPMC_MIPS_BACKTRACE
|
||||
/*
|
||||
* Unwind, and unwind, and unwind
|
||||
*/
|
||||
while (1) {
|
||||
if (frames >= nframes)
|
||||
break;
|
||||
|
||||
if (pmc_next_frame(&pc, &sp) < 0)
|
||||
break;
|
||||
|
||||
cc[frames++] = pc;
|
||||
}
|
||||
#endif
|
||||
|
||||
return (frames);
|
||||
}
|
||||
|
||||
int
|
||||
pmc_save_user_callchain(uintptr_t *cc, int nframes,
|
||||
struct trapframe *tf)
|
||||
{
|
||||
register_t pc, ra, sp;
|
||||
int frames = 0;
|
||||
|
||||
pc = tf->pc;
|
||||
sp = tf->sp;
|
||||
ra = tf->ra;
|
||||
|
||||
cc[frames++] = pc;
|
||||
|
||||
#ifdef HWPMC_MIPS_BACKTRACE
|
||||
|
||||
/*
|
||||
* Unwind, and unwind, and unwind
|
||||
*/
|
||||
while (1) {
|
||||
if (frames >= nframes)
|
||||
break;
|
||||
|
||||
if (pmc_next_uframe(&pc, &sp, &ra) < 0)
|
||||
break;
|
||||
|
||||
cc[frames++] = pc;
|
||||
}
|
||||
#endif
|
||||
|
||||
return (frames);
|
||||
}
|
||||
@ -1,230 +0,0 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 2010 George V. Neville-Neil <gnn@freebsd.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/pmc.h>
|
||||
#include <sys/pmckern.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/pmc_mdep.h>
|
||||
|
||||
#define MIPS24K_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
|
||||
PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
|
||||
PMC_CAP_THRESHOLD | PMC_CAP_READ | \
|
||||
PMC_CAP_WRITE | PMC_CAP_INVERT | \
|
||||
PMC_CAP_QUALIFIER)
|
||||
|
||||
#define MIPS24K_PMC_INTERRUPT_ENABLE 0x10 /* Enable interrupts */
|
||||
#define MIPS24K_PMC_USER_ENABLE 0x08 /* Count in USER mode */
|
||||
#define MIPS24K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */
|
||||
#define MIPS24K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */
|
||||
#define MIPS24K_PMC_ENABLE (MIPS24K_PMC_USER_ENABLE | \
|
||||
MIPS24K_PMC_SUPER_ENABLE | \
|
||||
MIPS24K_PMC_KERNEL_ENABLE)
|
||||
|
||||
#define MIPS24K_PMC_SELECT 5 /* Which bit position the event starts at. */
|
||||
|
||||
const struct mips_event_code_map mips_event_codes[] = {
|
||||
{ PMC_EV_MIPS24K_CYCLE, MIPS_CTR_ALL, 0},
|
||||
{ PMC_EV_MIPS24K_INSTR_EXECUTED, MIPS_CTR_ALL, 1},
|
||||
{ PMC_EV_MIPS24K_BRANCH_COMPLETED, MIPS_CTR_0, 2},
|
||||
{ PMC_EV_MIPS24K_BRANCH_MISPRED, MIPS_CTR_1, 2},
|
||||
{ PMC_EV_MIPS24K_RETURN, MIPS_CTR_0, 3},
|
||||
{ PMC_EV_MIPS24K_RETURN_MISPRED, MIPS_CTR_1, 3},
|
||||
{ PMC_EV_MIPS24K_RETURN_NOT_31, MIPS_CTR_0, 4},
|
||||
{ PMC_EV_MIPS24K_RETURN_NOTPRED, MIPS_CTR_1, 4},
|
||||
{ PMC_EV_MIPS24K_ITLB_ACCESS, MIPS_CTR_0, 5},
|
||||
{ PMC_EV_MIPS24K_ITLB_MISS, MIPS_CTR_1, 5},
|
||||
{ PMC_EV_MIPS24K_DTLB_ACCESS, MIPS_CTR_0, 6},
|
||||
{ PMC_EV_MIPS24K_DTLB_MISS, MIPS_CTR_1, 6},
|
||||
{ PMC_EV_MIPS24K_JTLB_IACCESS, MIPS_CTR_0, 7},
|
||||
{ PMC_EV_MIPS24K_JTLB_IMISS, MIPS_CTR_1, 7},
|
||||
{ PMC_EV_MIPS24K_JTLB_DACCESS, MIPS_CTR_0, 8},
|
||||
{ PMC_EV_MIPS24K_JTLB_DMISS, MIPS_CTR_1, 8},
|
||||
{ PMC_EV_MIPS24K_IC_FETCH, MIPS_CTR_0, 9},
|
||||
{ PMC_EV_MIPS24K_IC_MISS, MIPS_CTR_1, 9},
|
||||
{ PMC_EV_MIPS24K_DC_LOADSTORE, MIPS_CTR_0, 10},
|
||||
{ PMC_EV_MIPS24K_DC_WRITEBACK, MIPS_CTR_1, 10},
|
||||
{ PMC_EV_MIPS24K_DC_MISS, MIPS_CTR_ALL, 11},
|
||||
/* 12 reserved */
|
||||
{ PMC_EV_MIPS24K_STORE_MISS, MIPS_CTR_0, 13},
|
||||
{ PMC_EV_MIPS24K_LOAD_MISS, MIPS_CTR_1, 13},
|
||||
{ PMC_EV_MIPS24K_INTEGER_COMPLETED, MIPS_CTR_0, 14},
|
||||
{ PMC_EV_MIPS24K_FP_COMPLETED, MIPS_CTR_1, 14},
|
||||
{ PMC_EV_MIPS24K_LOAD_COMPLETED, MIPS_CTR_0, 15},
|
||||
{ PMC_EV_MIPS24K_STORE_COMPLETED, MIPS_CTR_1, 15},
|
||||
{ PMC_EV_MIPS24K_BARRIER_COMPLETED, MIPS_CTR_0, 16},
|
||||
{ PMC_EV_MIPS24K_MIPS16_COMPLETED, MIPS_CTR_1, 16},
|
||||
{ PMC_EV_MIPS24K_NOP_COMPLETED, MIPS_CTR_0, 17},
|
||||
{ PMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETED, MIPS_CTR_1, 17},
|
||||
{ PMC_EV_MIPS24K_RF_STALL, MIPS_CTR_0, 18},
|
||||
{ PMC_EV_MIPS24K_INSTR_REFETCH, MIPS_CTR_1, 18},
|
||||
{ PMC_EV_MIPS24K_STORE_COND_COMPLETED, MIPS_CTR_0, 19},
|
||||
{ PMC_EV_MIPS24K_STORE_COND_FAILED, MIPS_CTR_1, 19},
|
||||
{ PMC_EV_MIPS24K_ICACHE_REQUESTS, MIPS_CTR_0, 20},
|
||||
{ PMC_EV_MIPS24K_ICACHE_HIT, MIPS_CTR_1, 20},
|
||||
{ PMC_EV_MIPS24K_L2_WRITEBACK, MIPS_CTR_0, 21},
|
||||
{ PMC_EV_MIPS24K_L2_ACCESS, MIPS_CTR_1, 21},
|
||||
{ PMC_EV_MIPS24K_L2_MISS, MIPS_CTR_0, 22},
|
||||
{ PMC_EV_MIPS24K_L2_ERR_CORRECTED, MIPS_CTR_1, 22},
|
||||
{ PMC_EV_MIPS24K_EXCEPTIONS, MIPS_CTR_0, 23},
|
||||
/* Event 23 on COP0 1/3 is undefined */
|
||||
{ PMC_EV_MIPS24K_RF_CYCLES_STALLED, MIPS_CTR_0, 24},
|
||||
{ PMC_EV_MIPS24K_IFU_CYCLES_STALLED, MIPS_CTR_0, 25},
|
||||
{ PMC_EV_MIPS24K_ALU_CYCLES_STALLED, MIPS_CTR_1, 25},
|
||||
/* Events 26 through 32 undefined or reserved to customers */
|
||||
{ PMC_EV_MIPS24K_UNCACHED_LOAD, MIPS_CTR_0, 33},
|
||||
{ PMC_EV_MIPS24K_UNCACHED_STORE, MIPS_CTR_1, 33},
|
||||
{ PMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETED, MIPS_CTR_0, 35},
|
||||
{ PMC_EV_MIPS24K_MFTC_COMPLETED, MIPS_CTR_1, 35},
|
||||
/* Event 36 reserved */
|
||||
{ PMC_EV_MIPS24K_IC_BLOCKED_CYCLES, MIPS_CTR_0, 37},
|
||||
{ PMC_EV_MIPS24K_DC_BLOCKED_CYCLES, MIPS_CTR_1, 37},
|
||||
{ PMC_EV_MIPS24K_L2_IMISS_STALL_CYCLES, MIPS_CTR_0, 38},
|
||||
{ PMC_EV_MIPS24K_L2_DMISS_STALL_CYCLES, MIPS_CTR_1, 38},
|
||||
{ PMC_EV_MIPS24K_DMISS_CYCLES, MIPS_CTR_0, 39},
|
||||
{ PMC_EV_MIPS24K_L2_MISS_CYCLES, MIPS_CTR_1, 39},
|
||||
{ PMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLES, MIPS_CTR_0, 40},
|
||||
{ PMC_EV_MIPS24K_MDU_STALL_CYCLES, MIPS_CTR_0, 41},
|
||||
{ PMC_EV_MIPS24K_FPU_STALL_CYCLES, MIPS_CTR_1, 41},
|
||||
{ PMC_EV_MIPS24K_CP2_STALL_CYCLES, MIPS_CTR_0, 42},
|
||||
{ PMC_EV_MIPS24K_COREXTEND_STALL_CYCLES, MIPS_CTR_1, 42},
|
||||
{ PMC_EV_MIPS24K_ISPRAM_STALL_CYCLES, MIPS_CTR_0, 43},
|
||||
{ PMC_EV_MIPS24K_DSPRAM_STALL_CYCLES, MIPS_CTR_1, 43},
|
||||
{ PMC_EV_MIPS24K_CACHE_STALL_CYCLES, MIPS_CTR_0, 44},
|
||||
/* Event 44 undefined on 1/3 */
|
||||
{ PMC_EV_MIPS24K_LOAD_TO_USE_STALLS, MIPS_CTR_0, 45},
|
||||
{ PMC_EV_MIPS24K_BASE_MISPRED_STALLS, MIPS_CTR_1, 45},
|
||||
{ PMC_EV_MIPS24K_CPO_READ_STALLS, MIPS_CTR_0, 46},
|
||||
{ PMC_EV_MIPS24K_BRANCH_MISPRED_CYCLES, MIPS_CTR_1, 46},
|
||||
/* Event 47 reserved */
|
||||
{ PMC_EV_MIPS24K_IFETCH_BUFFER_FULL, MIPS_CTR_0, 48},
|
||||
{ PMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATED, MIPS_CTR_1, 48},
|
||||
{ PMC_EV_MIPS24K_EJTAG_ITRIGGER, MIPS_CTR_0, 49},
|
||||
{ PMC_EV_MIPS24K_EJTAG_DTRIGGER, MIPS_CTR_1, 49},
|
||||
{ PMC_EV_MIPS24K_FSB_LT_QUARTER, MIPS_CTR_0, 50},
|
||||
{ PMC_EV_MIPS24K_FSB_QUARTER_TO_HALF, MIPS_CTR_1, 50},
|
||||
{ PMC_EV_MIPS24K_FSB_GT_HALF, MIPS_CTR_0, 51},
|
||||
{ PMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLS, MIPS_CTR_1, 51},
|
||||
{ PMC_EV_MIPS24K_LDQ_LT_QUARTER, MIPS_CTR_0, 52},
|
||||
{ PMC_EV_MIPS24K_LDQ_QUARTER_TO_HALF, MIPS_CTR_1, 52},
|
||||
{ PMC_EV_MIPS24K_LDQ_GT_HALF, MIPS_CTR_0, 53},
|
||||
{ PMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLS, MIPS_CTR_1, 53},
|
||||
{ PMC_EV_MIPS24K_WBB_LT_QUARTER, MIPS_CTR_0, 54},
|
||||
{ PMC_EV_MIPS24K_WBB_QUARTER_TO_HALF, MIPS_CTR_1, 54},
|
||||
{ PMC_EV_MIPS24K_WBB_GT_HALF, MIPS_CTR_0, 55},
|
||||
{ PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS, MIPS_CTR_1, 55},
|
||||
/* Events 56-63 reserved */
|
||||
{ PMC_EV_MIPS24K_REQUEST_LATENCY, MIPS_CTR_0, 61},
|
||||
{ PMC_EV_MIPS24K_REQUEST_COUNT, MIPS_CTR_1, 61}
|
||||
|
||||
};
|
||||
|
||||
const int mips_event_codes_size = nitems(mips_event_codes);
|
||||
|
||||
struct mips_pmc_spec mips_pmc_spec = {
|
||||
.ps_cpuclass = PMC_CLASS_MIPS24K,
|
||||
.ps_cputype = PMC_CPU_MIPS_24K,
|
||||
.ps_capabilities = MIPS24K_PMC_CAPS,
|
||||
.ps_counter_width = 32
|
||||
};
|
||||
|
||||
/*
|
||||
* Performance Count Register N
|
||||
*/
|
||||
uint64_t
|
||||
mips_pmcn_read(unsigned int pmc)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips24k,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
/* The counter value is the next value after the control register. */
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
reg = mips_rd_perfcnt1();
|
||||
break;
|
||||
case 1:
|
||||
reg = mips_rd_perfcnt3();
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint64_t
|
||||
mips_pmcn_write(unsigned int pmc, uint64_t reg)
|
||||
{
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips24k,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
mips_wr_perfcnt1(reg);
|
||||
break;
|
||||
case 1:
|
||||
mips_wr_perfcnt3(reg);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
|
||||
{
|
||||
uint32_t config;
|
||||
|
||||
config = event;
|
||||
|
||||
config <<= MIPS24K_PMC_SELECT;
|
||||
|
||||
if (caps & PMC_CAP_SYSTEM)
|
||||
config |= (MIPS24K_PMC_SUPER_ENABLE |
|
||||
MIPS24K_PMC_KERNEL_ENABLE);
|
||||
if (caps & PMC_CAP_USER)
|
||||
config |= MIPS24K_PMC_USER_ENABLE;
|
||||
if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
|
||||
config |= MIPS24K_PMC_ENABLE;
|
||||
if (caps & PMC_CAP_INTERRUPT)
|
||||
config |= MIPS24K_PMC_INTERRUPT_ENABLE;
|
||||
|
||||
PMCDBG2(MDP,ALL,2,"mips24k-get_perfctl ri=%d -> config=0x%x", ri, config);
|
||||
|
||||
return (config);
|
||||
}
|
||||
@ -1,260 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2010 George V. Neville-Neil <gnn@freebsd.org>
|
||||
* Copyright (c) 2015 Adrian Chadd <adrian@freebsd.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/pmc.h>
|
||||
#include <sys/pmckern.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/pmc_mdep.h>
|
||||
|
||||
#define MIPS74K_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
|
||||
PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
|
||||
PMC_CAP_THRESHOLD | PMC_CAP_READ | \
|
||||
PMC_CAP_WRITE | PMC_CAP_INVERT | \
|
||||
PMC_CAP_QUALIFIER)
|
||||
|
||||
/* 0x1 - Exception_enable */
|
||||
#define MIPS74K_PMC_INTERRUPT_ENABLE 0x10 /* Enable interrupts */
|
||||
#define MIPS74K_PMC_USER_ENABLE 0x08 /* Count in USER mode */
|
||||
#define MIPS74K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */
|
||||
#define MIPS74K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */
|
||||
#define MIPS74K_PMC_ENABLE (MIPS74K_PMC_USER_ENABLE | \
|
||||
MIPS74K_PMC_SUPER_ENABLE | \
|
||||
MIPS74K_PMC_KERNEL_ENABLE)
|
||||
|
||||
#define MIPS74K_PMC_SELECT 5 /* Which bit position the event starts at. */
|
||||
|
||||
const struct mips_event_code_map mips_event_codes[] = {
|
||||
{ PMC_EV_MIPS74K_CYCLES, MIPS_CTR_ALL, 0 },
|
||||
{ PMC_EV_MIPS74K_INSTR_EXECUTED, MIPS_CTR_ALL, 1 },
|
||||
{ PMC_EV_MIPS74K_PREDICTED_JR_31, MIPS_CTR_0, 2 },
|
||||
{ PMC_EV_MIPS74K_JR_31_MISPREDICTIONS, MIPS_CTR_1, 2 },
|
||||
{ PMC_EV_MIPS74K_REDIRECT_STALLS, MIPS_CTR_0, 3 },
|
||||
{ PMC_EV_MIPS74K_JR_31_NO_PREDICTIONS, MIPS_CTR_1, 3 },
|
||||
{ PMC_EV_MIPS74K_ITLB_ACCESSES, MIPS_CTR_0, 4 },
|
||||
{ PMC_EV_MIPS74K_ITLB_MISSES, MIPS_CTR_1, 4 },
|
||||
{ PMC_EV_MIPS74K_JTLB_INSN_MISSES, MIPS_CTR_1, 5 },
|
||||
{ PMC_EV_MIPS74K_ICACHE_ACCESSES, MIPS_CTR_0, 6 },
|
||||
{ PMC_EV_MIPS74K_ICACHE_MISSES, MIPS_CTR_1, 6 },
|
||||
{ PMC_EV_MIPS74K_ICACHE_MISS_STALLS, MIPS_CTR_0, 7 },
|
||||
{ PMC_EV_MIPS74K_UNCACHED_IFETCH_STALLS, MIPS_CTR_0, 8 },
|
||||
{ PMC_EV_MIPS74K_PDTRACE_BACK_STALLS, MIPS_CTR_1, 8 },
|
||||
{ PMC_EV_MIPS74K_IFU_REPLAYS, MIPS_CTR_0, 9 },
|
||||
{ PMC_EV_MIPS74K_KILLED_FETCH_SLOTS, MIPS_CTR_1, 9 },
|
||||
{ PMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLES, MIPS_CTR_0, 11 },
|
||||
{ PMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLES, MIPS_CTR_1, 11 },
|
||||
{ PMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLES, MIPS_CTR_0, 12 },
|
||||
{ PMC_EV_MIPS74K_DDQ0_FULL_DR_STALLS, MIPS_CTR_0, 13 },
|
||||
{ PMC_EV_MIPS74K_DDQ1_FULL_DR_STALLS, MIPS_CTR_1, 13 },
|
||||
{ PMC_EV_MIPS74K_ALCB_FULL_DR_STALLS, MIPS_CTR_0, 14 },
|
||||
{ PMC_EV_MIPS74K_AGCB_FULL_DR_STALLS, MIPS_CTR_1, 14 },
|
||||
{ PMC_EV_MIPS74K_CLDQ_FULL_DR_STALLS, MIPS_CTR_0, 15 },
|
||||
{ PMC_EV_MIPS74K_IODQ_FULL_DR_STALLS, MIPS_CTR_1, 15 },
|
||||
{ PMC_EV_MIPS74K_ALU_EMPTY_CYCLES, MIPS_CTR_0, 16 },
|
||||
{ PMC_EV_MIPS74K_AGEN_EMPTY_CYCLES, MIPS_CTR_1, 16 },
|
||||
{ PMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLES, MIPS_CTR_0, 17 },
|
||||
{ PMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLES, MIPS_CTR_1, 17 },
|
||||
{ PMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLES, MIPS_CTR_0, 18 },
|
||||
{ PMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLES, MIPS_CTR_1, 18 },
|
||||
{ PMC_EV_MIPS74K_ALU_BUBBLE_CYCLES, MIPS_CTR_0, 19 },
|
||||
{ PMC_EV_MIPS74K_AGEN_BUBBLE_CYCLES, MIPS_CTR_1, 19 },
|
||||
{ PMC_EV_MIPS74K_SINGLE_ISSUE_CYCLES, MIPS_CTR_0, 20 },
|
||||
{ PMC_EV_MIPS74K_DUAL_ISSUE_CYCLES, MIPS_CTR_1, 20 },
|
||||
{ PMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLES, MIPS_CTR_0, 21 },
|
||||
{ PMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLES, MIPS_CTR_1, 21 },
|
||||
{ PMC_EV_MIPS74K_JALR_JALR_HB_INSNS, MIPS_CTR_0, 22 },
|
||||
{ PMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTS, MIPS_CTR_1, 22 },
|
||||
{ PMC_EV_MIPS74K_DCACHE_LOAD_ACCESSES, MIPS_CTR_0, 23 },
|
||||
{ PMC_EV_MIPS74K_DCACHE_ACCESSES, MIPS_CTR_1, 23 },
|
||||
{ PMC_EV_MIPS74K_DCACHE_WRITEBACKS, MIPS_CTR_0, 24 },
|
||||
{ PMC_EV_MIPS74K_DCACHE_MISSES, MIPS_CTR_1, 24 },
|
||||
{ PMC_EV_MIPS74K_JTLB_DATA_ACCESSES, MIPS_CTR_0, 25 },
|
||||
{ PMC_EV_MIPS74K_JTLB_DATA_MISSES, MIPS_CTR_1, 25 },
|
||||
{ PMC_EV_MIPS74K_LOAD_STORE_REPLAYS, MIPS_CTR_0, 26 },
|
||||
{ PMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASES, MIPS_CTR_1, 26 },
|
||||
{ PMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLES, MIPS_CTR_0, 27 },
|
||||
{ PMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTS, MIPS_CTR_1, 27 },
|
||||
{ PMC_EV_MIPS74K_L2_CACHE_WRITEBACKS, MIPS_CTR_0, 28 },
|
||||
{ PMC_EV_MIPS74K_L2_CACHE_ACCESSES, MIPS_CTR_1, 28 },
|
||||
{ PMC_EV_MIPS74K_L2_CACHE_MISSES, MIPS_CTR_0, 29 },
|
||||
{ PMC_EV_MIPS74K_L2_CACHE_MISS_CYCLES, MIPS_CTR_1, 29 },
|
||||
{ PMC_EV_MIPS74K_FSB_FULL_STALLS, MIPS_CTR_0, 30 },
|
||||
{ PMC_EV_MIPS74K_FSB_OVER_50_FULL, MIPS_CTR_1, 30 },
|
||||
{ PMC_EV_MIPS74K_LDQ_FULL_STALLS, MIPS_CTR_0, 31 },
|
||||
{ PMC_EV_MIPS74K_LDQ_OVER_50_FULL, MIPS_CTR_1, 31 },
|
||||
{ PMC_EV_MIPS74K_WBB_FULL_STALLS, MIPS_CTR_0, 32 },
|
||||
{ PMC_EV_MIPS74K_WBB_OVER_50_FULL, MIPS_CTR_1, 32 },
|
||||
{ PMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYS, MIPS_CTR_0, 35 },
|
||||
{ PMC_EV_MIPS74K_CP1_CP2_LOAD_INSNS, MIPS_CTR_1, 35 },
|
||||
{ PMC_EV_MIPS74K_JR_NON_31_INSNS, MIPS_CTR_0, 36 },
|
||||
{ PMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNS, MIPS_CTR_1, 36 },
|
||||
{ PMC_EV_MIPS74K_BRANCH_INSNS, MIPS_CTR_0, 37 },
|
||||
{ PMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNS, MIPS_CTR_1, 37 },
|
||||
{ PMC_EV_MIPS74K_BRANCH_LIKELY_INSNS, MIPS_CTR_0, 38 },
|
||||
{ PMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNS, MIPS_CTR_1, 38 },
|
||||
{ PMC_EV_MIPS74K_COND_BRANCH_INSNS, MIPS_CTR_0, 39 },
|
||||
{ PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS, MIPS_CTR_1, 39 },
|
||||
{ PMC_EV_MIPS74K_INTEGER_INSNS, MIPS_CTR_0, 40 },
|
||||
{ PMC_EV_MIPS74K_FPU_INSNS, MIPS_CTR_1, 40 },
|
||||
{ PMC_EV_MIPS74K_LOAD_INSNS, MIPS_CTR_0, 41 },
|
||||
{ PMC_EV_MIPS74K_STORE_INSNS, MIPS_CTR_1, 41 },
|
||||
{ PMC_EV_MIPS74K_J_JAL_INSNS, MIPS_CTR_0, 42 },
|
||||
{ PMC_EV_MIPS74K_MIPS16_INSNS, MIPS_CTR_1, 42 },
|
||||
{ PMC_EV_MIPS74K_NOP_INSNS, MIPS_CTR_0, 43 },
|
||||
{ PMC_EV_MIPS74K_NT_MUL_DIV_INSNS, MIPS_CTR_1, 43 },
|
||||
{ PMC_EV_MIPS74K_DSP_INSNS, MIPS_CTR_0, 44 },
|
||||
{ PMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNS, MIPS_CTR_1, 44 },
|
||||
{ PMC_EV_MIPS74K_DSP_BRANCH_INSNS, MIPS_CTR_0, 45 },
|
||||
{ PMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNS, MIPS_CTR_1, 45 },
|
||||
{ PMC_EV_MIPS74K_UNCACHED_LOAD_INSNS, MIPS_CTR_0, 46 },
|
||||
{ PMC_EV_MIPS74K_UNCACHED_STORE_INSNS, MIPS_CTR_1, 46 },
|
||||
{ PMC_EV_MIPS74K_EJTAG_INSN_TRIGGERS, MIPS_CTR_0, 49 },
|
||||
{ PMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONS, MIPS_CTR_0, 50 },
|
||||
{ PMC_EV_MIPS74K_SC_INSNS, MIPS_CTR_0, 51 },
|
||||
{ PMC_EV_MIPS74K_FAILED_SC_INSNS, MIPS_CTR_1, 51 },
|
||||
{ PMC_EV_MIPS74K_PREFETCH_INSNS, MIPS_CTR_0, 52 },
|
||||
{ PMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNS, MIPS_CTR_1, 52 },
|
||||
{ PMC_EV_MIPS74K_NO_INSN_CYCLES, MIPS_CTR_0, 53 },
|
||||
{ PMC_EV_MIPS74K_LOAD_MISS_INSNS, MIPS_CTR_1, 53 },
|
||||
{ PMC_EV_MIPS74K_ONE_INSN_CYCLES, MIPS_CTR_0, 54 },
|
||||
{ PMC_EV_MIPS74K_TWO_INSNS_CYCLES, MIPS_CTR_1, 54 },
|
||||
{ PMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLES, MIPS_CTR_0, 55 },
|
||||
{ PMC_EV_MIPS74K_CP1_CP2_STORE_INSNS, MIPS_CTR_1, 55 },
|
||||
{ PMC_EV_MIPS74K_MISPREDICTION_STALLS, MIPS_CTR_0, 56 },
|
||||
{ PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLES, MIPS_CTR_0, 57 },
|
||||
{ PMC_EV_MIPS74K_EXCEPTIONS_TAKEN, MIPS_CTR_0, 58 },
|
||||
{ PMC_EV_MIPS74K_GRADUATION_REPLAYS, MIPS_CTR_1, 58 },
|
||||
{ PMC_EV_MIPS74K_COREEXTEND_EVENTS, MIPS_CTR_0, 59 },
|
||||
{ PMC_EV_MIPS74K_ISPRAM_EVENTS, MIPS_CTR_0, 62 },
|
||||
{ PMC_EV_MIPS74K_DSPRAM_EVENTS, MIPS_CTR_1, 62 },
|
||||
{ PMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORS, MIPS_CTR_0, 63 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_0, MIPS_CTR_0, 64 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_1, MIPS_CTR_1, 64 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_2, MIPS_CTR_0, 65 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_3, MIPS_CTR_1, 65 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_4, MIPS_CTR_0, 66 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_5, MIPS_CTR_1, 66 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_6, MIPS_CTR_0, 67 },
|
||||
{ PMC_EV_MIPS74K_SYSTEM_EVENT_7, MIPS_CTR_1, 67 },
|
||||
{ PMC_EV_MIPS74K_OCP_ALL_REQUESTS, MIPS_CTR_0, 68 },
|
||||
{ PMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTS, MIPS_CTR_1, 68 },
|
||||
{ PMC_EV_MIPS74K_OCP_READ_REQUESTS, MIPS_CTR_0, 69 },
|
||||
{ PMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTS, MIPS_CTR_1, 69 },
|
||||
{ PMC_EV_MIPS74K_OCP_WRITE_REQUESTS, MIPS_CTR_0, 70 },
|
||||
{ PMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTS, MIPS_CTR_1, 70 },
|
||||
{ PMC_EV_MIPS74K_FSB_LESS_25_FULL, MIPS_CTR_0, 74 },
|
||||
{ PMC_EV_MIPS74K_FSB_25_50_FULL, MIPS_CTR_1, 74 },
|
||||
{ PMC_EV_MIPS74K_LDQ_LESS_25_FULL, MIPS_CTR_0, 75 },
|
||||
{ PMC_EV_MIPS74K_LDQ_25_50_FULL, MIPS_CTR_1, 75 },
|
||||
{ PMC_EV_MIPS74K_WBB_LESS_25_FULL, MIPS_CTR_0, 76 },
|
||||
{ PMC_EV_MIPS74K_WBB_25_50_FULL, MIPS_CTR_1, 76 },
|
||||
};
|
||||
|
||||
const int mips_event_codes_size = nitems(mips_event_codes);
|
||||
|
||||
struct mips_pmc_spec mips_pmc_spec = {
|
||||
.ps_cpuclass = PMC_CLASS_MIPS74K,
|
||||
.ps_cputype = PMC_CPU_MIPS_74K,
|
||||
.ps_capabilities = MIPS74K_PMC_CAPS,
|
||||
.ps_counter_width = 32
|
||||
};
|
||||
|
||||
/*
|
||||
* Performance Count Register N
|
||||
*/
|
||||
uint64_t
|
||||
mips_pmcn_read(unsigned int pmc)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips74k,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
/* The counter value is the next value after the control register. */
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
reg = mips_rd_perfcnt1();
|
||||
break;
|
||||
case 1:
|
||||
reg = mips_rd_perfcnt3();
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint64_t
|
||||
mips_pmcn_write(unsigned int pmc, uint64_t reg)
|
||||
{
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips74k,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
mips_wr_perfcnt1(reg);
|
||||
break;
|
||||
case 1:
|
||||
mips_wr_perfcnt3(reg);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
|
||||
{
|
||||
uint32_t config;
|
||||
|
||||
config = event;
|
||||
|
||||
config <<= MIPS74K_PMC_SELECT;
|
||||
|
||||
if (caps & PMC_CAP_SYSTEM)
|
||||
config |= (MIPS74K_PMC_SUPER_ENABLE |
|
||||
MIPS74K_PMC_KERNEL_ENABLE);
|
||||
if (caps & PMC_CAP_USER)
|
||||
config |= MIPS74K_PMC_USER_ENABLE;
|
||||
if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
|
||||
config |= MIPS74K_PMC_ENABLE;
|
||||
if (caps & PMC_CAP_INTERRUPT)
|
||||
config |= MIPS74K_PMC_INTERRUPT_ENABLE;
|
||||
|
||||
PMCDBG2(MDP,ALL,2,"mips74k-get_perfctl ri=%d -> config=0x%x", ri, config);
|
||||
|
||||
return (config);
|
||||
}
|
||||
@ -1,197 +0,0 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/pmc.h>
|
||||
#include <sys/pmckern.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/pmc_mdep.h>
|
||||
|
||||
#include <contrib/octeon-sdk/cvmx.h>
|
||||
#include <contrib/octeon-sdk/cvmx-core.h>
|
||||
|
||||
#define OCTEON_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
|
||||
PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
|
||||
PMC_CAP_THRESHOLD | PMC_CAP_READ | \
|
||||
PMC_CAP_WRITE | PMC_CAP_INVERT | \
|
||||
PMC_CAP_QUALIFIER)
|
||||
|
||||
const struct mips_event_code_map mips_event_codes[] =
|
||||
{
|
||||
{ PMC_EV_OCTEON_CLK, MIPS_CTR_ALL, CVMX_CORE_PERF_CLK },
|
||||
{ PMC_EV_OCTEON_ISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_ISSUE },
|
||||
{ PMC_EV_OCTEON_RET, MIPS_CTR_ALL, CVMX_CORE_PERF_RET },
|
||||
{ PMC_EV_OCTEON_NISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_NISSUE },
|
||||
{ PMC_EV_OCTEON_SISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_SISSUE },
|
||||
{ PMC_EV_OCTEON_DISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_DISSUE },
|
||||
{ PMC_EV_OCTEON_IFI, MIPS_CTR_ALL, CVMX_CORE_PERF_IFI },
|
||||
{ PMC_EV_OCTEON_BR, MIPS_CTR_ALL, CVMX_CORE_PERF_BR },
|
||||
{ PMC_EV_OCTEON_BRMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_BRMIS },
|
||||
{ PMC_EV_OCTEON_J, MIPS_CTR_ALL, CVMX_CORE_PERF_J },
|
||||
{ PMC_EV_OCTEON_JMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_JMIS },
|
||||
{ PMC_EV_OCTEON_REPLAY, MIPS_CTR_ALL, CVMX_CORE_PERF_REPLAY },
|
||||
{ PMC_EV_OCTEON_IUNA, MIPS_CTR_ALL, CVMX_CORE_PERF_IUNA },
|
||||
{ PMC_EV_OCTEON_TRAP, MIPS_CTR_ALL, CVMX_CORE_PERF_TRAP },
|
||||
{ PMC_EV_OCTEON_UULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_UULOAD },
|
||||
{ PMC_EV_OCTEON_UUSTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_UUSTORE },
|
||||
{ PMC_EV_OCTEON_ULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_ULOAD },
|
||||
{ PMC_EV_OCTEON_USTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_USTORE },
|
||||
{ PMC_EV_OCTEON_EC, MIPS_CTR_ALL, CVMX_CORE_PERF_EC },
|
||||
{ PMC_EV_OCTEON_MC, MIPS_CTR_ALL, CVMX_CORE_PERF_MC },
|
||||
{ PMC_EV_OCTEON_CC, MIPS_CTR_ALL, CVMX_CORE_PERF_CC },
|
||||
{ PMC_EV_OCTEON_CSRC, MIPS_CTR_ALL, CVMX_CORE_PERF_CSRC },
|
||||
{ PMC_EV_OCTEON_CFETCH, MIPS_CTR_ALL, CVMX_CORE_PERF_CFETCH },
|
||||
{ PMC_EV_OCTEON_CPREF, MIPS_CTR_ALL, CVMX_CORE_PERF_CPREF },
|
||||
{ PMC_EV_OCTEON_ICA, MIPS_CTR_ALL, CVMX_CORE_PERF_ICA },
|
||||
{ PMC_EV_OCTEON_II, MIPS_CTR_ALL, CVMX_CORE_PERF_II },
|
||||
{ PMC_EV_OCTEON_IP, MIPS_CTR_ALL, CVMX_CORE_PERF_IP },
|
||||
{ PMC_EV_OCTEON_CIMISS, MIPS_CTR_ALL, CVMX_CORE_PERF_CIMISS },
|
||||
{ PMC_EV_OCTEON_WBUF, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUF },
|
||||
{ PMC_EV_OCTEON_WDAT, MIPS_CTR_ALL, CVMX_CORE_PERF_WDAT },
|
||||
{ PMC_EV_OCTEON_WBUFLD, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFLD },
|
||||
{ PMC_EV_OCTEON_WBUFFL, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFFL },
|
||||
{ PMC_EV_OCTEON_WBUFTR, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFTR },
|
||||
{ PMC_EV_OCTEON_BADD, MIPS_CTR_ALL, CVMX_CORE_PERF_BADD },
|
||||
{ PMC_EV_OCTEON_BADDL2, MIPS_CTR_ALL, CVMX_CORE_PERF_BADDL2 },
|
||||
{ PMC_EV_OCTEON_BFILL, MIPS_CTR_ALL, CVMX_CORE_PERF_BFILL },
|
||||
{ PMC_EV_OCTEON_DDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DDIDS },
|
||||
{ PMC_EV_OCTEON_IDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IDIDS },
|
||||
{ PMC_EV_OCTEON_DIDNA, MIPS_CTR_ALL, CVMX_CORE_PERF_DIDNA },
|
||||
{ PMC_EV_OCTEON_LDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LDS },
|
||||
{ PMC_EV_OCTEON_LMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMLDS },
|
||||
{ PMC_EV_OCTEON_IOLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOLDS },
|
||||
{ PMC_EV_OCTEON_DMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DMLDS },
|
||||
{ PMC_EV_OCTEON_STS, MIPS_CTR_ALL, CVMX_CORE_PERF_STS },
|
||||
{ PMC_EV_OCTEON_LMSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMSTS },
|
||||
{ PMC_EV_OCTEON_IOSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOSTS },
|
||||
{ PMC_EV_OCTEON_IOBDMA, MIPS_CTR_ALL, CVMX_CORE_PERF_IOBDMA },
|
||||
{ PMC_EV_OCTEON_DTLB, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLB },
|
||||
{ PMC_EV_OCTEON_DTLBAD, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLBAD },
|
||||
{ PMC_EV_OCTEON_ITLB, MIPS_CTR_ALL, CVMX_CORE_PERF_ITLB },
|
||||
{ PMC_EV_OCTEON_SYNC, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNC },
|
||||
{ PMC_EV_OCTEON_SYNCIOB, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCIOB },
|
||||
{ PMC_EV_OCTEON_SYNCW, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCW },
|
||||
};
|
||||
|
||||
const int mips_event_codes_size = nitems(mips_event_codes);
|
||||
|
||||
struct mips_pmc_spec mips_pmc_spec = {
|
||||
.ps_cpuclass = PMC_CLASS_OCTEON,
|
||||
.ps_cputype = PMC_CPU_MIPS_OCTEON,
|
||||
.ps_capabilities = OCTEON_PMC_CAPS,
|
||||
.ps_counter_width = 64
|
||||
};
|
||||
|
||||
/*
|
||||
* Performance Count Register N
|
||||
*/
|
||||
uint64_t
|
||||
mips_pmcn_read(unsigned int pmc)
|
||||
{
|
||||
uint64_t reg = 0;
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
/* The counter value is the next value after the control register. */
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
CVMX_MF_COP0(reg, COP0_PERFVALUE0);
|
||||
break;
|
||||
case 1:
|
||||
CVMX_MF_COP0(reg, COP0_PERFVALUE1);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint64_t
|
||||
mips_pmcn_write(unsigned int pmc, uint64_t reg)
|
||||
{
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
CVMX_MT_COP0(reg, COP0_PERFVALUE0);
|
||||
break;
|
||||
case 1:
|
||||
CVMX_MT_COP0(reg, COP0_PERFVALUE1);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
|
||||
{
|
||||
cvmx_core_perf_control_t control;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[mips,%d] illegal CPU value %d", __LINE__, cpu));
|
||||
KASSERT(ri >= 0 && ri < mips_npmcs,
|
||||
("[mips,%d] illegal row index %d", __LINE__, ri));
|
||||
|
||||
control.s.event = event;
|
||||
|
||||
if (caps & PMC_CAP_SYSTEM) {
|
||||
control.s.k = 1;
|
||||
control.s.s = 1;
|
||||
control.s.ex = 1;
|
||||
}
|
||||
|
||||
if (caps & PMC_CAP_USER)
|
||||
control.s.u = 1;
|
||||
|
||||
if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) {
|
||||
control.s.k = 1;
|
||||
control.s.s = 1;
|
||||
control.s.u = 1;
|
||||
control.s.ex = 1;
|
||||
}
|
||||
|
||||
if (caps & PMC_CAP_INTERRUPT)
|
||||
control.s.ie = 1;
|
||||
|
||||
PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri,
|
||||
control.u32);
|
||||
|
||||
return (control.u32);
|
||||
}
|
||||
@ -138,8 +138,6 @@ SUBDIR= \
|
||||
${_hptnr} \
|
||||
${_hptrr} \
|
||||
hwpmc \
|
||||
${_hwpmc_mips24k} \
|
||||
${_hwpmc_mips74k} \
|
||||
${_hyperv} \
|
||||
i2c \
|
||||
${_iavf} \
|
||||
@ -591,11 +589,6 @@ SUBDIR+= tests
|
||||
SUBDIR+= zfs
|
||||
.endif
|
||||
|
||||
.if (${MACHINE_CPUARCH} == "mips" && ${MACHINE_ARCH:Mmips64} == "")
|
||||
_hwpmc_mips24k= hwpmc_mips24k
|
||||
_hwpmc_mips74k= hwpmc_mips74k
|
||||
.endif
|
||||
|
||||
.if ${MACHINE_CPUARCH} != "aarch64" && ${MACHINE_CPUARCH} != "arm" && \
|
||||
${MACHINE_CPUARCH} != "mips" && ${MACHINE_CPUARCH} != "powerpc" && \
|
||||
${MACHINE_CPUARCH} != "riscv"
|
||||
|
||||
@ -1,17 +0,0 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/hwpmc
|
||||
|
||||
KMOD= hwpmc_mips24k
|
||||
|
||||
SRCS= bus_if.h device_if.h vnode_if.h
|
||||
SRCS+= hwpmc_mod.c hwpmc_logging.c hwpmc_soft.c
|
||||
SRCS+= hwpmc_mips.c
|
||||
|
||||
SRCS+= hwpmc_mips24k.c
|
||||
|
||||
SRCS+= opt_hwpmc_hooks.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -1,17 +0,0 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/hwpmc
|
||||
|
||||
KMOD= hwpmc_mips74k
|
||||
|
||||
SRCS= bus_if.h device_if.h vnode_if.h
|
||||
SRCS+= hwpmc_mod.c hwpmc_logging.c hwpmc_soft.c
|
||||
SRCS+= hwpmc_mips.c
|
||||
|
||||
SRCS+= hwpmc_mips74k.c
|
||||
|
||||
SRCS+= opt_hwpmc_hooks.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
x
Reference in New Issue
Block a user