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ixl(4): Fix 2.5 and 5G speeds reporting and update shared code

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Fix 2.5 and 5G speeds reporting and update shared code with recent
changes:
- Update expected FW API versions for X710 and X722 adapters
- Define pointers related to Preservation Rules Module
- Add definitions for Shadow RAM pointers to new modules: 5th and 6th
  FPA, and Preservation Rules Module.
- Add I40E_RX_PTYPE_PARSER_ABORTED definition, so the driver will know
  opcode for parser aborted packets.
- Add the new filter types needed for custom cloud filters.
- Add support for Minimum Rollback Revision
- Fix RX_ONLY mode for unicast promiscuous on VLAN
- Add EEE LPI status check for X722 adapters
- Fix PHY type identifiers for 2.5G and 5G adapters
- Fix update link data for X722
- Increase the timeout value for PF reset to give PF more time to finish
  reset if it is loaded with filters.
- Added support for Min Rollback Revision for 4 more X722 modules
- Fix reporting of Active Optical Cable media type
- Add flags and fields for double VLAN processing
- Fix potentially uninitialized variables in NVM code

Reviewed by:	kbowling@, mike.jakubik@gmail.com
Tested by:	gowtham.kumar.ks@intel.com
Sponsored by:	Intel Corporation
Differential Revision:	https://reviews.freebsd.org/D31565
This commit is contained in:
Krzysztof Galazka 2021-09-13 13:39:59 -07:00 committed by Eric Joyner
parent f28c1d0c5c
commit abf774528d
No known key found for this signature in database
GPG Key ID: 96F0C6FD61E05DE3
10 changed files with 234 additions and 108 deletions
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6
sys/dev/ixl/i40e_adminq.c
View File

@ -646,8 +646,10 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
{
struct i40e_adminq_info *aq = &hw->aq;
enum i40e_status_code ret_code;
u16 cfg_ptr, oem_hi, oem_lo;
u16 eetrack_lo, eetrack_hi;
u16 oem_hi = 0, oem_lo = 0;
u16 eetrack_hi = 0;
u16 eetrack_lo = 0;
u16 cfg_ptr = 0;
int retry = 0;
/* verify input for valid configuration */

71
sys/dev/ixl/i40e_adminq_cmd.h
View File

@ -43,8 +43,8 @@
#define I40E_FW_API_VERSION_MAJOR 0x0001
#define I40E_FW_API_VERSION_MINOR_X722 0x000A
#define I40E_FW_API_VERSION_MINOR_X710 0x000A
#define I40E_FW_API_VERSION_MINOR_X722 0x000C
#define I40E_FW_API_VERSION_MINOR_X710 0x000E
#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
I40E_FW_API_VERSION_MINOR_X710 : \
@ -267,7 +267,8 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_nvm_update = 0x0703,
i40e_aqc_opc_nvm_config_read = 0x0704,
i40e_aqc_opc_nvm_config_write = 0x0705,
i40e_aqc_opc_nvm_progress = 0x0706,
i40e_aqc_opc_nvm_update_in_process = 0x0706,
i40e_aqc_opc_rollback_revision_update = 0x0707,
i40e_aqc_opc_oem_post_update = 0x0720,
i40e_aqc_opc_thermal_sensor = 0x0721,
@ -467,6 +468,7 @@ struct i40e_aqc_list_capabilities_element_resp {
#define I40E_AQ_CAP_ID_SDP 0x0062
#define I40E_AQ_CAP_ID_MDIO 0x0063
#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
#define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067
#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
#define I40E_AQ_CAP_ID_FLEX10 0x00F1
#define I40E_AQ_CAP_ID_CEM 0x00F2
@ -793,6 +795,7 @@ struct i40e_aqc_set_switch_config {
#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
#define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008
__le16 valid_flags;
/* The ethertype in switch_tag is dropped on ingress and used
* internally by the switch. Set this to zero for the default
@ -929,7 +932,7 @@ struct i40e_aqc_vsi_properties_data {
u8 sec_reserved;
/* VLAN section */
__le16 pvid; /* VLANS include priority bits */
__le16 fcoe_pvid;
__le16 outer_vlan;
u8 port_vlan_flags;
#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
@ -945,7 +948,24 @@ struct i40e_aqc_vsi_properties_data {
#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
u8 pvlan_reserved[3];
u8 outer_vlan_flags;
#define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00
#define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \
I40E_AQ_VSI_OVLAN_MODE_SHIFT)
#define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01
#define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02
#define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03
#define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04
#define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03
#define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\
I40E_AQ_VSI_OVLAN_EMOD_SHIFT)
#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00
#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01
#define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02
#define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03
#define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04
u8 pvlan_reserved[2];
/* ingress egress up sections */
__le32 ingress_table; /* bitmap, 3 bits per up */
#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
@ -1247,7 +1267,7 @@ struct i40e_aqc_set_vsi_promiscuous_modes {
#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
#define I40E_AQC_SET_VSI_DEFAULT 0x08
#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
#define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
__le16 seid;
#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
__le16 vlan_tag;
@ -1433,6 +1453,8 @@ struct i40e_aqc_cloud_filters_element_data {
#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
#define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010
#define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012
/* 0x000D reserved */
/* 0x000E reserved */
/* 0x000F reserved */
@ -1940,8 +1962,10 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_25GBASE_LR = 0x22,
I40E_PHY_TYPE_25GBASE_AOC = 0x23,
I40E_PHY_TYPE_25GBASE_ACC = 0x24,
I40E_PHY_TYPE_2_5GBASE_T = 0x30,
I40E_PHY_TYPE_5GBASE_T = 0x31,
I40E_PHY_TYPE_2_5GBASE_T = 0x26,
I40E_PHY_TYPE_5GBASE_T = 0x27,
I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30,
I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
I40E_PHY_TYPE_MAX,
I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
I40E_PHY_TYPE_EMPTY = 0xFE,
@ -2411,6 +2435,16 @@ struct i40e_aqc_nvm_config_data_feature {
I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
/* NVM Update in Process (direct 0x0706) */
struct i40e_aqc_nvm_update_in_process {
u8 command;
#define I40E_AQ_UPDATE_FLOW_END 0x0
#define I40E_AQ_UPDATE_FLOW_START 0x1
u8 reserved[15];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update_in_process);
struct i40e_aqc_nvm_config_data_immediate_field {
__le32 field_id;
__le32 field_value;
@ -2420,6 +2454,27 @@ struct i40e_aqc_nvm_config_data_immediate_field {
I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
/* Minimal Rollback Revision Update (direct 0x0707) */
struct i40e_aqc_rollback_revision_update {
u8 optin_mode; /* bool */
#define I40E_AQ_RREV_OPTIN_MODE 0x01
u8 module_selected;
#define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0
#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1
#define I40E_AQ_RREV_MODULE_OPTION_ROM 2
#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3
#define I40E_AQ_RREV_MODULE_PE_IMAGE 4
#define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5
#define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6
#define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7
#define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8
u8 reserved1[2];
u32 min_rrev;
u8 reserved2[8];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_rollback_revision_update);
/* OEM Post Update (indirect 0x0720)
* no command data struct used
*/

206
sys/dev/ixl/i40e_common.c
View File

@ -1251,12 +1251,15 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
case I40E_PHY_TYPE_40GBASE_LR4:
case I40E_PHY_TYPE_25GBASE_LR:
case I40E_PHY_TYPE_25GBASE_SR:
case I40E_PHY_TYPE_10GBASE_AOC:
case I40E_PHY_TYPE_25GBASE_AOC:
case I40E_PHY_TYPE_40GBASE_AOC:
media = I40E_MEDIA_TYPE_FIBER;
break;
case I40E_PHY_TYPE_100BASE_TX:
case I40E_PHY_TYPE_1000BASE_T:
case I40E_PHY_TYPE_2_5GBASE_T:
case I40E_PHY_TYPE_5GBASE_T:
case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
case I40E_PHY_TYPE_10GBASE_T:
media = I40E_MEDIA_TYPE_BASET;
break;
@ -1265,10 +1268,7 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
case I40E_PHY_TYPE_10GBASE_CR1:
case I40E_PHY_TYPE_40GBASE_CR4:
case I40E_PHY_TYPE_10GBASE_SFPP_CU:
case I40E_PHY_TYPE_40GBASE_AOC:
case I40E_PHY_TYPE_10GBASE_AOC:
case I40E_PHY_TYPE_25GBASE_CR:
case I40E_PHY_TYPE_25GBASE_AOC:
case I40E_PHY_TYPE_25GBASE_ACC:
media = I40E_MEDIA_TYPE_DA;
break;
@ -1316,7 +1316,7 @@ static enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
return I40E_ERR_RESET_FAILED;
}
#define I40E_PF_RESET_WAIT_COUNT 200
#define I40E_PF_RESET_WAIT_COUNT 1000
/**
* i40e_pf_reset - Reset the PF
* @hw: pointer to the hardware structure
@ -1563,7 +1563,6 @@ static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
**/
u32 i40e_led_get(struct i40e_hw *hw)
{
u32 current_mode = 0;
u32 mode = 0;
int i;
@ -1576,20 +1575,6 @@ u32 i40e_led_get(struct i40e_hw *hw)
if (!gpio_val)
continue;
/* ignore gpio LED src mode entries related to the activity
* LEDs
*/
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
switch (current_mode) {
case I40E_COMBINED_ACTIVITY:
case I40E_FILTER_ACTIVITY:
case I40E_MAC_ACTIVITY:
case I40E_LINK_ACTIVITY:
continue;
default:
break;
}
mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
@ -1610,7 +1595,6 @@ u32 i40e_led_get(struct i40e_hw *hw)
**/
void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
{
u32 current_mode = 0;
int i;
if (mode & ~I40E_LED_MODE_VALID) {
@ -1627,20 +1611,6 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
if (!gpio_val)
continue;
/* ignore gpio LED src mode entries related to the activity
* LEDs
*/
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
switch (current_mode) {
case I40E_COMBINED_ACTIVITY:
case I40E_FILTER_ACTIVITY:
case I40E_MAC_ACTIVITY:
case I40E_LINK_ACTIVITY:
continue;
default:
break;
}
if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
u32 pin_func = 0;
@ -2053,6 +2023,9 @@ enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
/* 'Get Link Status' response data structure from X722 FW has
* different format and does not contain this information
*/
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
hw->mac.type != I40E_MAC_X722) {
__le32 tmp;
@ -2251,6 +2224,22 @@ enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
return status;
}
/**
* i40e_hw_ver_ge
* @hw: pointer to the hw struct
* @maj: api major value
* @min: api minor value
*
* Assert whether current HW api version is greater/equal than provided.
**/
static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min)
{
if (hw->aq.api_maj_ver > maj ||
(hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min))
return TRUE;
return FALSE;
}
/**
* i40e_aq_add_vsi
* @hw: pointer to the hw struct
@ -2376,18 +2365,16 @@ enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
if (set) {
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
if (rx_only_promisc &&
(((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
(hw->aq.api_maj_ver > 1)))
flags |= I40E_AQC_SET_VSI_PROMISC_TX;
if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5))
flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
}
cmd->promiscuous_flags = CPU_TO_LE16(flags);
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
(hw->aq.api_maj_ver > 1))
cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
if (i40e_hw_ver_ge(hw, 1, 5))
cmd->valid_flags |=
CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
cmd->seid = CPU_TO_LE16(seid);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
@ -2519,11 +2506,17 @@ enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_vsi_promiscuous_modes);
if (enable)
if (enable) {
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
if (i40e_hw_ver_ge(hw, 1, 5))
flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
}
cmd->promiscuous_flags = CPU_TO_LE16(flags);
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
if (i40e_hw_ver_ge(hw, 1, 5))
cmd->valid_flags |=
CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
cmd->seid = CPU_TO_LE16(seid);
cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
@ -2633,7 +2626,7 @@ enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
}
/**
* i40e_get_vsi_params - get VSI configuration info
* i40e_aq_get_vsi_params - get VSI configuration info
* @hw: pointer to the hw struct
* @vsi_ctx: pointer to a vsi context struct
* @cmd_details: pointer to command details structure or NULL
@ -2893,7 +2886,7 @@ enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
}
/**
* i40e_updatelink_status - update status of the HW network link
* i40e_update_link_info - update status of the HW network link
* @hw: pointer to the hw struct
**/
enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
@ -2906,10 +2899,13 @@ enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
return status;
/* extra checking needed to ensure link info to user is timely */
if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
if (((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) ||
hw->mac.type == I40E_MAC_X722) {
status = i40e_aq_get_phy_capabilities(hw, FALSE,
hw->mac.type ==
I40E_MAC_X722,
&abilities, NULL);
if (status)
return status;
@ -3666,6 +3662,64 @@ enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
return status;
}
/**
* i40e_aq_nvm_update_in_process
* @hw: pointer to the hw struct
* @update_flow_state: True indicates that update flow starts, FALSE that ends
* @cmd_details: pointer to command details structure or NULL
*
* Indicate NVM update in process.
**/
enum i40e_status_code i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
bool update_flow_state,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_nvm_update_in_process *cmd =
(struct i40e_aqc_nvm_update_in_process *)&desc.params.raw;
enum i40e_status_code status;
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_nvm_update_in_process);
cmd->command = I40E_AQ_UPDATE_FLOW_END;
if (update_flow_state)
cmd->command |= I40E_AQ_UPDATE_FLOW_START;
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
}
/**
* i40e_aq_min_rollback_rev_update - triggers an ow after update
* @hw: pointer to the hw struct
* @mode: opt-in mode, 1b for single module update, 0b for bulk update
* @module: module to be updated. Ignored if mode is 0b
* @min_rrev: value of the new minimal version. Ignored if mode is 0b
* @cmd_details: pointer to command details structure or NULL
**/
enum i40e_status_code
i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module,
u32 min_rrev,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_rollback_revision_update *cmd =
(struct i40e_aqc_rollback_revision_update *)&desc.params.raw;
enum i40e_status_code status;
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rollback_revision_update);
cmd->optin_mode = mode;
cmd->module_selected = module;
cmd->min_rrev = min_rrev;
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
}
/**
* i40e_aq_oem_post_update - triggers an OEM specific flow after update
* @hw: pointer to the hw struct
@ -3998,7 +4052,13 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
p->wr_csr_prot |= (u64)logical_id << 32;
i40e_debug(hw, I40E_DEBUG_INIT,
"HW Capability: wr_csr_prot = 0x%llX\n\n",
(p->wr_csr_prot & 0xffff));
(unsigned long long)(p->wr_csr_prot & 0xffff));
break;
case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
p->dis_unused_ports = (bool)number;
i40e_debug(hw, I40E_DEBUG_INIT,
"HW Capability: dis_unused_ports = %d\n\n",
p->dis_unused_ports);
break;
case I40E_AQ_CAP_ID_NVM_MGMT:
if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
@ -4193,28 +4253,6 @@ i40e_aq_update_nvm_exit:
return status;
}
/**
* i40e_aq_nvm_progress
* @hw: pointer to the hw struct
* @progress: pointer to progress returned from AQ
* @cmd_details: pointer to command details structure or NULL
*
* Gets progress of flash rearrangement process
**/
enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
struct i40e_asq_cmd_details *cmd_details)
{
enum i40e_status_code status;
struct i40e_aq_desc desc;
DEBUGFUNC("i40e_aq_nvm_progress");
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
*progress = desc.params.raw[0];
return status;
}
/**
* i40e_aq_get_lldp_mib
* @hw: pointer to the hw struct
@ -4593,7 +4631,7 @@ enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
}
/**
* i40e_aq_get_switch_resource_alloc (0x0204)
* i40e_aq_get_switch_resource_alloc - command (0x0204) to get allocations
* @hw: pointer to the hw struct
* @num_entries: pointer to u8 to store the number of resource entries returned
* @buf: pointer to a user supplied buffer. This buffer must be large enough
@ -6705,7 +6743,7 @@ u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
}
/**
* i40e_blink_phy_led
* i40e_blink_phy_link_led
* @hw: pointer to the HW structure
* @time: time how long led will blinks in secs
* @interval: gap between LED on and off in msecs
@ -6942,15 +6980,23 @@ enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
struct i40e_hw_port_stats *stat)
{
enum i40e_status_code ret = I40E_SUCCESS;
bool eee_mrvl_phy;
bool eee_bcm_phy;
u32 val;
stat->rx_lpi_status = 0;
stat->tx_lpi_status = 0;
if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
(hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
eee_bcm_phy =
(hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
(hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB);
eee_mrvl_phy =
hw->device_id == I40E_DEV_ID_1G_BASE_T_X722;
if (eee_bcm_phy || eee_mrvl_phy) {
// read Clause 45 PCS Status 1 register
ret = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
I40E_BCM_PHY_PCS_STATUS1_PAGE,
@ -7542,7 +7588,7 @@ enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
}
/**
* i40e_aq_opc_set_ns_proxy_table_entry
* i40e_aq_set_ns_proxy_table_entry
* @hw: pointer to the HW structure
* @ns_proxy_table_entry: pointer to NS table entry command struct
* @cmd_details: pointer to command details

10
sys/dev/ixl/i40e_dcb.c
View File

@ -265,7 +265,7 @@ static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv,
}
/**
* i40e_parse_ieee_etsrec_tlv
* i40e_parse_ieee_tlv
* @tlv: IEEE 802.1Qaz TLV
* @dcbcfg: Local store to update ETS REC data
*
@ -345,9 +345,15 @@ static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,
* |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
* ---------------------------------
*/
for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
etscfg->tcbwtable[i] = buf[offset++];
if (etscfg->prioritytable[i] == I40E_CEE_PGID_STRICT)
dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;
else
dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
}
/* Number of TCs supported (1 octet) */
etscfg->maxtcs = buf[offset];
}

2
sys/dev/ixl/i40e_lan_hmc.c
View File

@ -546,7 +546,7 @@ configure_lan_hmc_out:
}
/**
* i40e_delete_hmc_object - remove hmc objects
* i40e_delete_lan_hmc_object - remove hmc objects
* @hw: pointer to the HW structure
* @info: pointer to i40e_hmc_delete_obj_info struct
*

13
sys/dev/ixl/i40e_nvm.c
View File

@ -35,7 +35,7 @@
#include "i40e_prototype.h"
/**
* i40e_init_nvm_ops - Initialize NVM function pointers
* i40e_init_nvm - Initialize NVM function pointers
* @hw: pointer to the HW structure
*
* Setup the function pointers and the NVM info structure. Should be called
@ -108,7 +108,8 @@ enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
if (ret_code)
i40e_debug(hw, I40E_DEBUG_NVM,
"NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
access, time_left, ret_code, hw->aq.asq_last_status);
access, (unsigned long long)time_left, ret_code,
hw->aq.asq_last_status);
if (ret_code && time_left) {
/* Poll until the current NVM owner timeouts */
@ -130,7 +131,8 @@ enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
hw->nvm.hw_semaphore_timeout = 0;
i40e_debug(hw, I40E_DEBUG_NVM,
"NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
time_left, ret_code, hw->aq.asq_last_status);
(unsigned long long)time_left, ret_code,
hw->aq.asq_last_status);
}
}
@ -782,10 +784,11 @@ enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
DEBUGFUNC("i40e_update_nvm_checksum");
ret_code = i40e_calc_nvm_checksum(hw, &checksum);
le_sum = CPU_TO_LE16(checksum);
if (ret_code == I40E_SUCCESS)
if (ret_code == I40E_SUCCESS) {
le_sum = CPU_TO_LE16(checksum);
ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
1, &le_sum, TRUE);
}
return ret_code;
}

10
sys/dev/ixl/i40e_prototype.h
View File

@ -268,6 +268,10 @@ enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
u8 cmd_flags, void *data, u16 buf_size,
u16 element_count,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code
i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module,
u32 min_rrev,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
void *buff, u16 buff_size,
struct i40e_asq_cmd_details *cmd_details);
@ -279,7 +283,11 @@ enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
u32 offset, u16 length, void *data,
bool last_command, u8 preservation_flags,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
u8 rearrange_nvm,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
bool update_flow_state,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
u8 mib_type, void *buff, u16 buff_size,

3
sys/dev/ixl/i40e_register.h
View File

@ -232,6 +232,9 @@
#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
#define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */
#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0
#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT)
#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */
#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)

17
sys/dev/ixl/i40e_type.h
View File

@ -347,12 +347,8 @@ struct i40e_phy_info {
I40E_PHY_TYPE_OFFSET)
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
I40E_PHY_TYPE_OFFSET)
/* Offset for 2.5G/5G PHY Types value to bit number conversion */
#define I40E_PHY_TYPE_OFFSET2 (-10)
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
I40E_PHY_TYPE_OFFSET2)
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
I40E_PHY_TYPE_OFFSET2)
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
#define I40E_HW_CAP_MAX_GPIO 30
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
@ -443,6 +439,7 @@ struct i40e_hw_capabilities {
u32 enabled_tcmap;
u32 maxtc;
u64 wr_csr_prot;
bool dis_unused_ports;
bool apm_wol_support;
enum i40e_acpi_programming_method acpi_prog_method;
bool proxy_support;
@ -975,7 +972,8 @@ enum i40e_rx_l2_ptype {
I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153,
I40E_RX_PTYPE_PARSER_ABORTED = 255
};
struct i40e_rx_ptype_decoded {
@ -1551,6 +1549,9 @@ struct i40e_hw_port_stats {
#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
#define I40E_SR_5TH_FREE_PROVISION_AREA_PTR 0x50
#define I40E_SR_PRESERVATION_RULES_PTR 0x70
#define I40E_FPK_SR_5TH_FREE_PROVISION_AREA_PTR 0x71
#define I40E_SR_6TH_FREE_PROVISION_AREA_PTR 0x71
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
@ -1720,6 +1721,8 @@ struct i40e_lldp_variables {
#define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
#define I40E_VERIFY_TAG_SHIFT 31
#define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
#define I40E_VLAN_SRC_SHIFT 55
#define I40E_VLAN_SRC_MASK (0x1ULL << I40E_VLAN_SRC_SHIFT)
#define I40E_FLEX_50_SHIFT 13
#define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)

4
sys/dev/ixl/if_ixl.c
View File

@ -1514,11 +1514,11 @@ ixl_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
ifmr->ifm_active |= IFM_1000_T;
break;
/* 2.5 G */
case I40E_PHY_TYPE_2_5GBASE_T:
case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
ifmr->ifm_active |= IFM_2500_T;
break;
/* 5 G */
case I40E_PHY_TYPE_5GBASE_T:
case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
ifmr->ifm_active |= IFM_5000_T;
break;
/* 10 G */