Next version, many bugs fixed
This commit is contained in:
Andrey A. Chernov
parent
017b6c4995
commit
ae39e7ee16
@ -86,48 +86,47 @@
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#define RCSR_OE 0x01 /* Overrun Error */
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#define RCSR_FE 0x02 /* Frame Error */
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#define RCSR_PE 0x04 /* Parity Error */
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#define RCSR_BREAK 0x08 /* Break detected */
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#define RCSR_TOUT 0x80 /* Rx Timeout */
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#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
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#define RCSR_Break 0x08 /* Break detected */
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#define RCSR_Timeout 0x80 /* Rx Timeout */
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#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */
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#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */
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#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */
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#define RCSR_SC3 0x30 /* Special Char 3 */
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#define RCSR_SC4 0x40 /* Special Char 4 */
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/* Channel Command Register */
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#define CCR_RESETCHAN 0x80 /* Reset Channel */
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#define CCR_ResetChan 0x80 /* Reset Channel */
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#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */
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#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
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#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
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#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
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#define CCR_SSPC1 0x21 /* Send Special Character 1 */
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#define CCR_SSPC2 0x22 /* Send Special Character 2 */
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#define CCR_SSPC3 0x23 /* Send Special Character 3 */
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#define CCR_SSPC4 0x24 /* Send Special Character 4 */
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#define CCR_CHANCTL 0x10 /* Channel Control Command */
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#define CCR_RXDIS 0x11 /* Receiver Disable */
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#define CCR_RXEN 0x12 /* Receiver Enable */
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#define CCR_TXDIS 0x14 /* Transmitter Disable */
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#define CCR_TXEN 0x18 /* Transmitter Enable */
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#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */
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#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */
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#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */
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#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */
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#define CCR_RCVRDIS 0x11 /* Receiver Disable */
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#define CCR_RCVREN 0x12 /* Receiver Enable */
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#define CCR_XMTRDIS 0x14 /* Transmitter Disable */
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#define CCR_XMTREN 0x18 /* Transmitter Enable */
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/* Interrupt Enable Register */
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#define IER_DSR 0x80 /* Enable interrupt on DSR change */
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#define IER_CD 0x40 /* Enable interrupt on CD change */
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#define IER_CTS 0x20 /* Enable interrupt on CTS change */
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#define IER_RXD 0x10 /* Enable interrupt on Receive Data */
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#define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
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#define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
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#define IER_TXMPTY 0x02 /* Enable interrupt on TX completely empty*/
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#define IER_RxData 0x10 /* Enable interrupt on Receive Data */
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#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */
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#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */
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#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/
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#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */
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/* Channel Option Register 1 */
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#define COR1_ODDP 0x80 /* Odd Parity */
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#define COR1_PARMASK 0x60 /* Parity Mode mask */
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#define COR1_ParMMASK 0x60 /* Parity Mode mask */
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#define COR1_NOPAR 0x02 /* No Parity */
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#define COR1_FORCEPAR 0x20 /* Force Parity */
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#define COR1_NORMPAR 0x40 /* Normal Parity */
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#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
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#define COR1_STOPMASK 0x0C /* Stop Bits mode mask */
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#define COR1_Ignore 0x10 /* Ignore Parity on RX */
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#define COR1_StopMASK 0x0C /* Stop Bits mode mask */
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#define COR1_1SB 0x00 /* 1 Stop Bit */
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#define COR1_15SB 0x04 /* 1.5 Stop Bits */
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#define COR1_2SB 0x08 /* 2 Stop Bits */
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@ -139,44 +138,44 @@
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/* Channel Option Register 2 */
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#define COR2_IXM 0x80 /* Implied XON mode */
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#define COR2_TXIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
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#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
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#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
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#define COR2_LLM 0x10 /* Local Loopback Mode */
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#define COR2_RLM 0x08 /* Remote Loopback Mode */
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#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
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#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
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#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
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#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */
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#define COR2_CtsAE 0x02 /* CTS Automatic Enable */
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#define COR2_DsrAE 0x01 /* DSR Automatic Enable */
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/* Channel Option Register 3 */
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#define COR3_XONCH 0x80 /* XON is a double seq (1 & 3) */
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#define COR3_XOFFCH 0x40 /* XOFF is a double seq (1 & 3) */
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#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */
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#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */
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#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
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#define COR3_SCDE 0x10 /* Special Character Detection Enable */
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#define COR3_RXTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
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#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
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/* Channel Control Status Register */
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#define CCSR_RXEN 0x80 /* Revceiver Enabled */
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#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF sent) */
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#define CCSR_RXFLON 0x20 /* Receive Flow On (XON sent) */
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#define CCSR_TXEN 0x08 /* Transmitter Enabled */
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#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
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#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
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#define CCSR_RxEn 0x80 /* Revceiver Enabled */
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#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */
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#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */
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#define CCSR_TxEn 0x08 /* Transmitter Enabled */
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#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */
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#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */
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/* Modem Change Option Register 1 */
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#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
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#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
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#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
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#define MCOR1_DTRTH 0x0F /* Automatic DTR FC Threshold (1-8) */
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#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */
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#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */
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#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */
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#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */
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/* Modem Change Option Register 2 */
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#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
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#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
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#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
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#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */
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#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */
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#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */
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/* Modem Change Register */
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#define MCR_DSRCHG 0x80 /* DSR Changed */
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#define MCR_CDCHG 0x40 /* CD Changed */
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#define MCR_CTSCHG 0x20 /* CTS Changed */
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#define MCR_DSRchg 0x80 /* DSR Changed */
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#define MCR_CDchg 0x40 /* CD Changed */
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#define MCR_CTSchg 0x20 /* CTS Changed */
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/* Modem Signal Value Register */
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#define MSVR_DSR 0x80 /* Current state of DSR input */
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835
sys/dev/rc/rc.c
835
sys/dev/rc/rc.c
File diff suppressed because it is too large
Load Diff
@ -42,7 +42,7 @@
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#define RC_VALIDIRQ(i) ((i) < 16 && \
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"\0\0\0\1\1\1\0\1\0\0\1\1\1\0\0\1"[(i) & 0xF])
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/* Riscom/8 board I/O mapping */
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/* Riscom/8 board ISA I/O mapping */
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#define RC_IOMAP(r) ((((r) & 07) << 1) | (((r) & ~07) << 7))
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/* I/O commands */
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@ -50,8 +50,8 @@
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#define RC_IN(p,i) inb (RC_IOMAP(i) + (p))
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/* Riscom on-board registers (mapping assumed) */
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#define RC_RI 0x100 /* Ring Indicator Register (read-only) */
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#define RC_DTR 0x100 /* DTR Register (write-only) */
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#define RC_RIREG 0x100 /* Ring Indicator Register (read-only) */
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#define RC_DTREG 0x100 /* DTR Register (write-only) */
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#define RC_BSR 0x101 /* Board Status Register (read-only) */
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#define RC_CTOUT 0x101 /* Clear Timeout (write-only) */
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@ -63,10 +63,10 @@
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/* Interrupt groups */
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#define RC_MODEMGRP 0x01 /* Modem interrupt group */
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#define RC_TXGRP 0x02 /* Transmitter interrupt group */
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#define RC_RXGRP 0x04 /* Receiver interrupt group */
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#define RC_RXGRP 0x02 /* Receiver interrupt group */
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#define RC_TXGRP 0x04 /* Transmitter interrupt group */
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/* Priority Interrupt Level definitions */
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#define RC_PILR_MODEM (0x80 | RC_MODEMGRP)
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#define RC_PILR_TX (0x80 | RC_TXGRP )
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#define RC_PILR_RX (0x80 | RC_RXGRP )
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#define RC_PILR_TX (0x80 | RC_TXGRP )
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@ -86,48 +86,47 @@
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#define RCSR_OE 0x01 /* Overrun Error */
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#define RCSR_FE 0x02 /* Frame Error */
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#define RCSR_PE 0x04 /* Parity Error */
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#define RCSR_BREAK 0x08 /* Break detected */
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#define RCSR_TOUT 0x80 /* Rx Timeout */
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#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
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#define RCSR_Break 0x08 /* Break detected */
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#define RCSR_Timeout 0x80 /* Rx Timeout */
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#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */
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#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */
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#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */
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#define RCSR_SC3 0x30 /* Special Char 3 */
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#define RCSR_SC4 0x40 /* Special Char 4 */
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/* Channel Command Register */
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#define CCR_RESETCHAN 0x80 /* Reset Channel */
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#define CCR_ResetChan 0x80 /* Reset Channel */
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#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */
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#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
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#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
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#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
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#define CCR_SSPC1 0x21 /* Send Special Character 1 */
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#define CCR_SSPC2 0x22 /* Send Special Character 2 */
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#define CCR_SSPC3 0x23 /* Send Special Character 3 */
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#define CCR_SSPC4 0x24 /* Send Special Character 4 */
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#define CCR_CHANCTL 0x10 /* Channel Control Command */
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#define CCR_RXDIS 0x11 /* Receiver Disable */
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#define CCR_RXEN 0x12 /* Receiver Enable */
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#define CCR_TXDIS 0x14 /* Transmitter Disable */
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#define CCR_TXEN 0x18 /* Transmitter Enable */
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#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */
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#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */
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#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */
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#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */
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#define CCR_RCVRDIS 0x11 /* Receiver Disable */
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#define CCR_RCVREN 0x12 /* Receiver Enable */
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#define CCR_XMTRDIS 0x14 /* Transmitter Disable */
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#define CCR_XMTREN 0x18 /* Transmitter Enable */
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/* Interrupt Enable Register */
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#define IER_DSR 0x80 /* Enable interrupt on DSR change */
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#define IER_CD 0x40 /* Enable interrupt on CD change */
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#define IER_CTS 0x20 /* Enable interrupt on CTS change */
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#define IER_RXD 0x10 /* Enable interrupt on Receive Data */
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#define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
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#define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
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#define IER_TXMPTY 0x02 /* Enable interrupt on TX completely empty*/
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#define IER_RxData 0x10 /* Enable interrupt on Receive Data */
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#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */
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#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */
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#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/
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#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */
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/* Channel Option Register 1 */
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#define COR1_ODDP 0x80 /* Odd Parity */
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#define COR1_PARMASK 0x60 /* Parity Mode mask */
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#define COR1_ParMMASK 0x60 /* Parity Mode mask */
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#define COR1_NOPAR 0x02 /* No Parity */
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#define COR1_FORCEPAR 0x20 /* Force Parity */
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#define COR1_NORMPAR 0x40 /* Normal Parity */
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#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
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#define COR1_STOPMASK 0x0C /* Stop Bits mode mask */
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#define COR1_Ignore 0x10 /* Ignore Parity on RX */
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#define COR1_StopMASK 0x0C /* Stop Bits mode mask */
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#define COR1_1SB 0x00 /* 1 Stop Bit */
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#define COR1_15SB 0x04 /* 1.5 Stop Bits */
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#define COR1_2SB 0x08 /* 2 Stop Bits */
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@ -139,44 +138,44 @@
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/* Channel Option Register 2 */
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#define COR2_IXM 0x80 /* Implied XON mode */
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#define COR2_TXIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
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#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
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#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
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#define COR2_LLM 0x10 /* Local Loopback Mode */
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#define COR2_RLM 0x08 /* Remote Loopback Mode */
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#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
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#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
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#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
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#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */
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#define COR2_CtsAE 0x02 /* CTS Automatic Enable */
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#define COR2_DsrAE 0x01 /* DSR Automatic Enable */
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/* Channel Option Register 3 */
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#define COR3_XONCH 0x80 /* XON is a double seq (1 & 3) */
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#define COR3_XOFFCH 0x40 /* XOFF is a double seq (1 & 3) */
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#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */
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#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */
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#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
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#define COR3_SCDE 0x10 /* Special Character Detection Enable */
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#define COR3_RXTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
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#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
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/* Channel Control Status Register */
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#define CCSR_RXEN 0x80 /* Revceiver Enabled */
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#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF sent) */
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#define CCSR_RXFLON 0x20 /* Receive Flow On (XON sent) */
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#define CCSR_TXEN 0x08 /* Transmitter Enabled */
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#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
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#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
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#define CCSR_RxEn 0x80 /* Revceiver Enabled */
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#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */
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#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */
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#define CCSR_TxEn 0x08 /* Transmitter Enabled */
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#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */
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#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */
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/* Modem Change Option Register 1 */
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#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
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#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
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#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
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#define MCOR1_DTRTH 0x0F /* Automatic DTR FC Threshold (1-8) */
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#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */
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#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */
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#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */
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#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */
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/* Modem Change Option Register 2 */
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#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
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#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
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#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
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#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */
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#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */
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#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */
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/* Modem Change Register */
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#define MCR_DSRCHG 0x80 /* DSR Changed */
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#define MCR_CDCHG 0x40 /* CD Changed */
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#define MCR_CTSCHG 0x20 /* CTS Changed */
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#define MCR_DSRchg 0x80 /* DSR Changed */
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#define MCR_CDchg 0x40 /* CD Changed */
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#define MCR_CTSchg 0x20 /* CTS Changed */
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/* Modem Signal Value Register */
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#define MSVR_DSR 0x80 /* Current state of DSR input */
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File diff suppressed because it is too large
Load Diff
@ -42,7 +42,7 @@
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#define RC_VALIDIRQ(i) ((i) < 16 && \
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"\0\0\0\1\1\1\0\1\0\0\1\1\1\0\0\1"[(i) & 0xF])
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/* Riscom/8 board I/O mapping */
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/* Riscom/8 board ISA I/O mapping */
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#define RC_IOMAP(r) ((((r) & 07) << 1) | (((r) & ~07) << 7))
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/* I/O commands */
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@ -50,8 +50,8 @@
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#define RC_IN(p,i) inb (RC_IOMAP(i) + (p))
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/* Riscom on-board registers (mapping assumed) */
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#define RC_RI 0x100 /* Ring Indicator Register (read-only) */
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#define RC_DTR 0x100 /* DTR Register (write-only) */
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#define RC_RIREG 0x100 /* Ring Indicator Register (read-only) */
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#define RC_DTREG 0x100 /* DTR Register (write-only) */
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#define RC_BSR 0x101 /* Board Status Register (read-only) */
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#define RC_CTOUT 0x101 /* Clear Timeout (write-only) */
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@ -63,10 +63,10 @@
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/* Interrupt groups */
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#define RC_MODEMGRP 0x01 /* Modem interrupt group */
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#define RC_TXGRP 0x02 /* Transmitter interrupt group */
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||||
#define RC_RXGRP 0x04 /* Receiver interrupt group */
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#define RC_RXGRP 0x02 /* Receiver interrupt group */
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||||
#define RC_TXGRP 0x04 /* Transmitter interrupt group */
|
||||
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||||
/* Priority Interrupt Level definitions */
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#define RC_PILR_MODEM (0x80 | RC_MODEMGRP)
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#define RC_PILR_TX (0x80 | RC_TXGRP )
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#define RC_PILR_RX (0x80 | RC_RXGRP )
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||||
#define RC_PILR_TX (0x80 | RC_TXGRP )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user