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We don't need to generate DMA complete interrupt for every

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transmitted frames. So request interrupt for every 16th frames. Due
to the limitation of hardware we can't suppress the interrupt as
driver should have to check TX status register. The TX status
register can store up to 31 TX status so driver can't send more
than 31 frames without reading TX status register.
With this change controller would not generate TX completion
interrupt for every frame, so reclaim transmitted frames in
ste_tick().
This commit is contained in:
Pyun YongHyeon 2009-12-23 19:38:22 +00:00
parent 95a3c23b51
commit ae49e7a695
2 changed files with 18 additions and 1 deletions
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13
sys/dev/ste/if_ste.c
View File

@ -877,6 +877,13 @@ ste_tick(void *arg)
*/
if ((sc->ste_flags & STE_FLAG_LINK) == 0)
ste_miibus_statchg(sc->ste_dev);
/*
* Because we are not generating Tx completion
* interrupt for every frame, reclaim transmitted
* buffers here.
*/
ste_txeof(sc);
ste_txeoc(sc);
ste_stats_update(sc);
ste_watchdog(sc);
callout_reset(&sc->ste_callout, hz, ste_tick, sc);
@ -1953,7 +1960,11 @@ ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
* Tx descriptors here. Otherwise we race with controller.
*/
desc->ste_next = 0;
desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR);
if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
STE_TXCTL_DMAINTR);
else
desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
txc->ste_mbuf = *m_head;
STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
sc->ste_cdata.ste_tx_cnt++;

6
sys/dev/ste/if_stereg.h
View File

@ -494,6 +494,12 @@ struct ste_desc_onefrag {
#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32)
/*
* Since Tx status can hold up to 31 status bytes we should
* check Tx status before controller fills it up. Otherwise
* Tx MAC stalls.
*/
#define STE_TX_INTR_FRAMES 16
#define STE_TX_TIMEOUT 5
#define STE_TIMEOUT 1000
#define STE_MIN_FRAMELEN 60