arm64: rk3399: add SPI driver and include it in GENERIC config
SPI driver for Rockchip's RK3399 SoC. Implements PIO mode, CS selection, SPI mode and frequency configuration. Reviewed by: manu MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D22148
This commit is contained in:
Oleksandr Tymoshenko
parent
a3a63d8ac2
commit
aea1c841f4
@ -286,6 +286,7 @@ device mv_thermal # Marvell Thermal Sensor Controller
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# SPI
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device spibus
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device bcm2835_spi # Broadcom BCM283x SPI bus
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device rk_spi # RockChip SPI controller
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# PWM
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device pwm
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483
sys/arm64/rockchip/rk_spi.c
Normal file
483
sys/arm64/rockchip/rk_spi.c
Normal file
@ -0,0 +1,483 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/resource.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "spibus_if.h"
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#define RK_SPI_CTRLR0 0x0000
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#define CTRLR0_OPM_MASTER (0 << 20)
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#define CTRLR0_XFM_TR (0 << 18)
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#define CTRLR0_FRF_MOTO (0 << 16)
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#define CTRLR0_BHT_8BIT (1 << 13)
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#define CTRLR0_EM_BIG (1 << 11)
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#define CTRLR0_SSD_ONE (1 << 10)
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#define CTRLR0_SCPOL (1 << 7)
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#define CTRLR0_SCPH (1 << 6)
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#define CTRLR0_DFS_8BIT (1 << 0)
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#define RK_SPI_CTRLR1 0x0004
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#define RK_SPI_ENR 0x0008
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#define RK_SPI_SER 0x000c
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#define RK_SPI_BAUDR 0x0010
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#define RK_SPI_TXFTLR 0x0014
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#define RK_SPI_RXFTLR 0x0018
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#define RK_SPI_TXFLR 0x001c
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#define RK_SPI_RXFLR 0x0020
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#define RK_SPI_SR 0x0024
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#define SR_BUSY (1 << 0)
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#define RK_SPI_IPR 0x0028
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#define RK_SPI_IMR 0x002c
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#define IMR_RFFIM (1 << 4)
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#define IMR_TFEIM (1 << 0)
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#define RK_SPI_ISR 0x0030
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#define ISR_RFFIS (1 << 4)
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#define ISR_TFEIS (1 << 0)
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#define RK_SPI_RISR 0x0034
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#define RK_SPI_ICR 0x0038
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#define RK_SPI_DMACR 0x003c
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#define RK_SPI_DMATDLR 0x0040
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#define RK_SPI_DMARDLR 0x0044
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#define RK_SPI_TXDR 0x0400
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#define RK_SPI_RXDR 0x0800
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#define CS_MAX 1
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static struct ofw_compat_data compat_data[] = {
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{ "rockchip,rk3399-spi", 1 },
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{ NULL, 0 }
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};
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static struct resource_spec rk_spi_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
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{ -1, 0 }
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};
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struct rk_spi_softc {
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device_t dev;
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device_t spibus;
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struct resource *res[2];
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struct mtx mtx;
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clk_t clk_apb;
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clk_t clk_spi;
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void * intrhand;
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int transfer;
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uint32_t fifo_size;
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uint64_t max_freq;
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uint32_t intreg;
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uint8_t *rxbuf;
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uint32_t rxidx;
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uint8_t *txbuf;
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uint32_t txidx;
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uint32_t txlen;
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uint32_t rxlen;
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};
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#define RK_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define RK_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define RK_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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static int rk_spi_probe(device_t dev);
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static int rk_spi_attach(device_t dev);
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static int rk_spi_detach(device_t dev);
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static void rk_spi_intr(void *arg);
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static void
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rk_spi_enable_chip(struct rk_spi_softc *sc, int enable)
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{
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RK_SPI_WRITE_4(sc, RK_SPI_ENR, enable ? 1 : 0);
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}
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static int
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rk_spi_set_cs(struct rk_spi_softc *sc, uint32_t cs, bool active)
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{
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uint32_t reg;
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if (cs & SPIBUS_CS_HIGH) {
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device_printf(sc->dev, "SPIBUS_CS_HIGH is not supported\n");
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return (EINVAL);
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}
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if (cs > CS_MAX)
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return (EINVAL);
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reg = RK_SPI_READ_4(sc, RK_SPI_SER);
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if (active)
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reg |= (1 << cs);
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else
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reg &= ~(1 << cs);
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RK_SPI_WRITE_4(sc, RK_SPI_SER, reg);
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return (0);
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}
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static void
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rk_spi_hw_setup(struct rk_spi_softc *sc, uint32_t mode, uint32_t freq)
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{
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uint32_t cr0;
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uint32_t div;
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cr0 = CTRLR0_OPM_MASTER | CTRLR0_XFM_TR | CTRLR0_FRF_MOTO |
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CTRLR0_BHT_8BIT | CTRLR0_EM_BIG | CTRLR0_SSD_ONE |
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CTRLR0_DFS_8BIT;
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if (mode & SPIBUS_MODE_CPHA)
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cr0 |= CTRLR0_SCPH;
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if (mode & SPIBUS_MODE_CPOL)
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cr0 |= CTRLR0_SCPOL;
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/* minimum divider is 2 */
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if (sc->max_freq < freq*2) {
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clk_set_freq(sc->clk_spi, 2 * freq, CLK_SET_ROUND_DOWN);
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clk_get_freq(sc->clk_spi, &sc->max_freq);
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}
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div = ((sc->max_freq + freq - 1) / freq);
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div = (div + 1) & 0xfffe;
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RK_SPI_WRITE_4(sc, RK_SPI_BAUDR, div);
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RK_SPI_WRITE_4(sc, RK_SPI_CTRLR0, cr0);
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}
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static uint32_t
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rk_spi_fifo_size(struct rk_spi_softc *sc)
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{
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uint32_t txftlr, reg;
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for (txftlr = 2; txftlr < 32; txftlr++) {
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RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, txftlr);
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reg = RK_SPI_READ_4(sc, RK_SPI_TXFTLR);
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if (reg != txftlr)
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break;
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}
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RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, 0);
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if (txftlr == 31)
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return 0;
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return txftlr;
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}
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static void
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rk_spi_empty_rxfifo(struct rk_spi_softc *sc)
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{
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uint32_t rxlevel;
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rxlevel = RK_SPI_READ_4(sc, RK_SPI_RXFLR);
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while (sc->rxidx < sc->rxlen &&
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(rxlevel-- > 0)) {
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sc->rxbuf[sc->rxidx++] = (uint8_t)RK_SPI_READ_4(sc, RK_SPI_RXDR);
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}
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}
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static void
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rk_spi_fill_txfifo(struct rk_spi_softc *sc)
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{
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uint32_t txlevel;
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txlevel = RK_SPI_READ_4(sc, RK_SPI_TXFLR);
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int cnt = 0;
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while (sc->txidx < sc->txlen && txlevel < sc->fifo_size) {
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RK_SPI_WRITE_4(sc, RK_SPI_TXDR, sc->txbuf[sc->txidx++]);
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txlevel++;
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cnt++;
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}
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if (sc->txidx != sc->txlen)
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sc->intreg |= (IMR_TFEIM | IMR_RFFIM);
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}
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static int
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rk_spi_xfer_buf(struct rk_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len)
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{
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int err;
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if (len == 0)
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return (0);
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sc->rxbuf = rxbuf;
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sc->rxlen = len;
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sc->rxidx = 0;
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sc->txbuf = txbuf;
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sc->txlen = len;
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sc->txidx = 0;
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sc->intreg = 0;
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rk_spi_fill_txfifo(sc);
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RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
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err = 0;
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while (err == 0 && sc->intreg != 0)
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err = msleep(sc, &sc->mtx, 0, "rk_spi", 10 * hz);
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while (err == 0 && sc->rxidx != sc->txidx) {
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/* read residual data from RX fifo */
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rk_spi_empty_rxfifo(sc);
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}
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if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen)
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err = EIO;
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return (err);
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}
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static int
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rk_spi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Rockchip SPI");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk_spi_attach(device_t dev)
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{
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struct rk_spi_softc *sc;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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if (bus_alloc_resources(dev, rk_spi_spec, sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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error = ENXIO;
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goto fail;
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}
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if (bus_setup_intr(dev, sc->res[1],
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INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_spi_intr, sc,
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&sc->intrhand)) {
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bus_release_resources(dev, rk_spi_spec, sc->res);
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device_printf(dev, "cannot setup interrupt handler\n");
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return (ENXIO);
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}
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/* Activate the module clock. */
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error = clk_get_by_ofw_name(dev, 0, "apb_pclk", &sc->clk_apb);
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if (error != 0) {
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device_printf(dev, "cannot get apb_pclk clock\n");
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goto fail;
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}
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error = clk_get_by_ofw_name(dev, 0, "spiclk", &sc->clk_spi);
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if (error != 0) {
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device_printf(dev, "cannot get spiclk clock\n");
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goto fail;
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}
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error = clk_enable(sc->clk_apb);
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if (error != 0) {
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device_printf(dev, "cannot enable ahb clock\n");
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goto fail;
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}
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error = clk_enable(sc->clk_spi);
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if (error != 0) {
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device_printf(dev, "cannot enable spiclk clock\n");
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goto fail;
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}
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clk_get_freq(sc->clk_spi, &sc->max_freq);
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sc->fifo_size = rk_spi_fifo_size(sc);
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if (sc->fifo_size == 0) {
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device_printf(dev, "failed to get fifo size\n");
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goto fail;
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}
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sc->spibus = device_add_child(dev, "spibus", -1);
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RK_SPI_WRITE_4(sc, RK_SPI_IMR, 0);
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RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, sc->fifo_size/2 - 1);
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RK_SPI_WRITE_4(sc, RK_SPI_RXFTLR, sc->fifo_size/2 - 1);
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return (bus_generic_attach(dev));
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fail:
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rk_spi_detach(dev);
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return (error);
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}
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static int
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rk_spi_detach(device_t dev)
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{
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struct rk_spi_softc *sc;
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sc = device_get_softc(dev);
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bus_generic_detach(sc->dev);
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if (sc->spibus != NULL)
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device_delete_child(dev, sc->spibus);
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if (sc->clk_spi != NULL)
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clk_release(sc->clk_spi);
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if (sc->clk_apb)
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clk_release(sc->clk_apb);
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if (sc->intrhand != NULL)
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bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
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bus_release_resources(dev, rk_spi_spec, sc->res);
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mtx_destroy(&sc->mtx);
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return (0);
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}
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static void
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rk_spi_intr(void *arg)
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{
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struct rk_spi_softc *sc;
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uint32_t intreg, isr;
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sc = arg;
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RK_SPI_LOCK(sc);
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intreg = RK_SPI_READ_4(sc, RK_SPI_IMR);
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isr = RK_SPI_READ_4(sc, RK_SPI_ISR);
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RK_SPI_WRITE_4(sc, RK_SPI_ICR, isr);
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if (isr & ISR_RFFIS)
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rk_spi_empty_rxfifo(sc);
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if (isr & ISR_TFEIS)
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rk_spi_fill_txfifo(sc);
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/* no bytes left, disable interrupt */
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if (sc->txidx == sc->txlen) {
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sc->intreg = 0;
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wakeup(sc);
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}
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if (sc->intreg != intreg) {
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(void)RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
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(void)RK_SPI_READ_4(sc, RK_SPI_IMR);
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}
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RK_SPI_UNLOCK(sc);
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}
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static phandle_t
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rk_spi_get_node(device_t bus, device_t dev)
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{
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return ofw_bus_get_node(bus);
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}
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static int
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rk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct rk_spi_softc *sc;
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uint32_t cs, mode, clock;
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int err = 0;
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sc = device_get_softc(dev);
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spibus_get_cs(child, &cs);
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spibus_get_clock(child, &clock);
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spibus_get_mode(child, &mode);
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RK_SPI_LOCK(sc);
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rk_spi_hw_setup(sc, mode, clock);
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rk_spi_enable_chip(sc, 1);
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err = rk_spi_set_cs(sc, cs, true);
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if (err != 0) {
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rk_spi_enable_chip(sc, 0);
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RK_SPI_UNLOCK(sc);
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return (err);
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}
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/* Transfer command then data bytes. */
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err = 0;
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if (cmd->tx_cmd_sz > 0)
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err = rk_spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
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cmd->tx_cmd_sz);
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if (cmd->tx_data_sz > 0 && err == 0)
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err = rk_spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
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||||
cmd->tx_data_sz);
|
||||
|
||||
rk_spi_set_cs(sc, cs, false);
|
||||
rk_spi_enable_chip(sc, 0);
|
||||
RK_SPI_UNLOCK(sc);
|
||||
|
||||
return (err);
|
||||
}
|
||||
|
||||
static device_method_t rk_spi_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, rk_spi_probe),
|
||||
DEVMETHOD(device_attach, rk_spi_attach),
|
||||
DEVMETHOD(device_detach, rk_spi_detach),
|
||||
|
||||
/* spibus_if */
|
||||
DEVMETHOD(spibus_transfer, rk_spi_transfer),
|
||||
|
||||
/* ofw_bus_if */
|
||||
DEVMETHOD(ofw_bus_get_node, rk_spi_get_node),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t rk_spi_driver = {
|
||||
"spi",
|
||||
rk_spi_methods,
|
||||
sizeof(struct rk_spi_softc),
|
||||
};
|
||||
|
||||
static devclass_t rk_spi_devclass;
|
||||
|
||||
DRIVER_MODULE(rk_spi, simplebus, rk_spi_driver, rk_spi_devclass, 0, 0);
|
||||
DRIVER_MODULE(ofw_spibus, rk_spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0);
|
||||
MODULE_DEPEND(rk_spi, ofw_spibus, 1, 1, 1);
|
||||
SIMPLEBUS_PNP_INFO(compat_data);
|
||||
@ -298,6 +298,7 @@ arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_
|
||||
arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
|
||||
arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399
|
||||
arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399
|
||||
arm64/rockchip/rk_spi.c optional fdt rk_spi
|
||||
arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399
|
||||
arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399
|
||||
arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user