Add the latest r300 code from r300.sf.net. This is based on the patch supplied
by Vladimir Dergachev for inclusion in DRM CVS, with minor modifications for FreeBSD CVS and the appropriate license from Nicolai Haehnle on r300_reg.h. Fixes hangs when using r300.sf.net userland, tested on a Radeon 9600 on amd64.
This commit is contained in:
Eric Anholt
parent
9727df0c09
commit
af088425f7
@ -210,7 +210,7 @@ device drm # DRM core module required by DRM drivers
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device mach64drm # ATI Rage Pro, Rage Mobility P/M, Rage XL
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device mgadrm # AGP Matrox G200, G400, G450, G550
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device r128drm # ATI Rage 128
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device radeondrm # ATI Radeon up to 9200
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device radeondrm # ATI Radeon
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device sisdrm # SiS 300/305, 540, 630
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device tdfxdrm # 3dfx Voodoo 3/4/5 and Banshee
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options DRM_DEBUG # Include debug printfs (slow)
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@ -511,6 +511,7 @@ dev/drm/r128_drv.c optional r128drm
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dev/drm/r128_irq.c optional r128drm
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dev/drm/r128_state.c optional r128drm \
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compile-with "${NORMAL_C} -finline-limit=13500"
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dev/drm/r300_cmdbuf.c optional radeondrm
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dev/drm/radeon_cp.c optional radeondrm
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dev/drm/radeon_drv.c optional radeondrm
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dev/drm/radeon_irq.c optional radeondrm
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@ -46,7 +46,7 @@
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# define ATI_PCIGART_PAGE_SIZE 4096 /* PCI GART page size */
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int drm_ati_pcigart_init(drm_device_t *dev, unsigned long *addr,
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dma_addr_t *bus_addr)
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dma_addr_t *bus_addr, int is_pcie)
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{
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drm_sg_mem_t *entry = dev->sg;
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unsigned long address = 0;
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@ -81,7 +81,14 @@ int drm_ati_pcigart_init(drm_device_t *dev, unsigned long *addr,
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page_base = (u32) entry->busaddr[i];
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for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
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*pci_gart++ = cpu_to_le32( page_base );
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if (is_pcie) {
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*pci_gart = (cpu_to_le32(page_base)>>8) | 0xc;
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DRM_DEBUG("PCIE: %d %08X %08X to %p\n", i,
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page_base, (cpu_to_le32(page_base)>>8)|0xc,
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pci_gart);
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} else
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*pci_gart = cpu_to_le32(page_base);
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pci_gart++;
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page_base += ATI_PCIGART_PAGE_SIZE;
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}
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}
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@ -252,6 +252,15 @@ typedef drm_device_t *device_t;
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extern struct cfdriver drm_cd;
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#endif /* !__FreeBSD__ */
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/* Capabilities taken from src/sys/dev/pci/pcireg.h. */
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#ifndef PCIY_AGP
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#define PCIY_AGP 0x02
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#endif
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#ifndef PCIY_EXPRESS
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#define PCIY_EXPRESS 0x10
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#endif
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typedef unsigned long dma_addr_t;
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typedef u_int32_t u32;
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typedef u_int16_t u16;
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@ -821,8 +830,9 @@ void drm_driver_irq_uninstall(drm_device_t *dev);
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int drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq);
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void drm_vbl_send_signals(drm_device_t *dev);
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/* AGP/GART support (drm_agpsupport.c) */
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/* AGP/PCI Express/GART support (drm_agpsupport.c) */
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int drm_device_is_agp(drm_device_t *dev);
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int drm_device_is_pcie(drm_device_t *dev);
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drm_agp_head_t *drm_agp_init(void);
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void drm_agp_uninit(void);
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void drm_agp_do_release(void);
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@ -842,7 +852,7 @@ extern int drm_sysctl_cleanup(drm_device_t *dev);
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/* ATI PCIGART support (ati_pcigart.c) */
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int drm_ati_pcigart_init(drm_device_t *dev, unsigned long *addr,
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dma_addr_t *bus_addr);
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dma_addr_t *bus_addr, int is_pcie);
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int drm_ati_pcigart_cleanup(drm_device_t *dev, unsigned long addr,
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dma_addr_t bus_addr);
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@ -39,8 +39,8 @@
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#include <dev/pci/pcireg.h>
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#endif
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int
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drm_device_is_agp(drm_device_t *dev)
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static int
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drm_device_find_capability(drm_device_t *dev, int cap)
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{
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#ifdef __FreeBSD__
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/* Code taken from agp.c. IWBNI that was a public interface. */
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@ -64,9 +64,9 @@ drm_device_is_agp(drm_device_t *dev)
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next = AGP_CAPID_GET_NEXT_PTR(capid);
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/*
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* If this capability entry ID is 2, then we are done.
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* If this capability entry ID is cap, then we are done.
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*/
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if (AGP_CAPID_GET_CAP_ID(capid) == 2)
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if (AGP_CAPID_GET_CAP_ID(capid) == cap)
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return 1;
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}
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@ -77,6 +77,18 @@ drm_device_is_agp(drm_device_t *dev)
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#endif
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}
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int
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drm_device_is_agp(drm_device_t *dev)
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{
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return (drm_device_find_capability(dev, PCIY_AGP));
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}
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int
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drm_device_is_pcie(drm_device_t *dev)
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{
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return (drm_device_find_capability(dev, PCIY_EXPRESS));
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}
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int drm_agp_info(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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@ -29,6 +29,8 @@
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{0x1002, 0x4965, CHIP_R250, "ATI Radeon Ie R250 9000"}, \
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{0x1002, 0x4966, CHIP_R250, "ATI Radeon If R250 9000"}, \
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{0x1002, 0x4967, CHIP_R250, "ATI Radeon Ig R250 9000"}, \
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{0x1002, 0x4A49, CHIP_R420, "ATI Radeon JI R420 X800PRO"}, \
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{0x1002, 0x4A4B, CHIP_R420, "ATI Radeon JK R420 X800 XT"}, \
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{0x1002, 0x4C57, CHIP_RV200|CHIP_IS_MOBILITY, "ATI Radeon LW RV200 Mobility 7500 M7"}, \
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{0x1002, 0x4C58, CHIP_RV200|CHIP_IS_MOBILITY, "ATI Radeon LX RV200 Mobility FireGL 7800 M7"}, \
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{0x1002, 0x4C59, CHIP_RV100|CHIP_IS_MOBILITY, "ATI Radeon LY RV100 Mobility M6"}, \
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@ -37,7 +39,17 @@
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{0x1002, 0x4C65, CHIP_R250|CHIP_IS_MOBILITY, "ATI Radeon Le R250 Mobility 9000 M9"}, \
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{0x1002, 0x4C66, CHIP_R250|CHIP_IS_MOBILITY, "ATI Radeon Lf R250 Mobility 9000 M9"}, \
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{0x1002, 0x4C67, CHIP_R250|CHIP_IS_MOBILITY, "ATI Radeon Lg R250 Mobility 9000 M9"}, \
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{0x1002, 0x4E44, CHIP_R300, "ATI Radeon ND R300 9700 Pro"}, \
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{0x1002, 0x4E45, CHIP_R300, "ATI Radeon NE R300 9500 Pro"}, \
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{0x1002, 0x4E46, CHIP_RV350, "ATI Radeon NF RV350 9600"}, \
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{0x1002, 0x4E47, CHIP_R300, "ATI Radeon NG R300 FireGL X1"}, \
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{0x1002, 0x4E48, CHIP_R350, "ATI Radeon NH R350 9800 Pro"}, \
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{0x1002, 0x4E49, CHIP_R350, "ATI Radeon NI R350 9800"}, \
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{0x1002, 0x4E4A, CHIP_RV350, "ATI Radeon NJ RV350 9800 XT"}, \
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{0x1002, 0x4E4B, CHIP_R350, "ATI Radeon NK R350 FireGL X2"}, \
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{0x1002, 0x4E50, CHIP_RV350|CHIP_IS_MOBILITY, "ATI Radeon RV300 Mobility 9600 M10"}, \
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{0x1002, 0x4E51, CHIP_RV350|CHIP_IS_MOBILITY, "ATI Radeon RV350 Mobility 9600 M10 NQ"}, \
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{0x1002, 0x4E54, CHIP_RV350|CHIP_IS_MOBILITY, "ATI Radeon FireGL T2 128"}, \
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{0x1002, 0x5144, CHIP_R100|CHIP_SINGLE_CRTC, "ATI Radeon QD R100"}, \
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{0x1002, 0x5145, CHIP_R100|CHIP_SINGLE_CRTC, "ATI Radeon QE R100"}, \
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{0x1002, 0x5146, CHIP_R100|CHIP_SINGLE_CRTC, "ATI Radeon QF R100"}, \
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@ -59,6 +71,7 @@
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{0x1002, 0x516A, CHIP_R200, "ATI Radeon Qj R200"}, \
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{0x1002, 0x516B, CHIP_R200, "ATI Radeon Qk R200"}, \
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{0x1002, 0x516C, CHIP_R200, "ATI Radeon Ql R200"}, \
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{0x1002, 0x5460, CHIP_RV350, "ATI Radeon X300"}, \
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{0x1002, 0x5834, CHIP_RS300|CHIP_IS_IGP, "ATI Radeon RS300 IGP"}, \
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{0x1002, 0x5835, CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY, "ATI Radeon RS300 Mobility IGP"}, \
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{0x1002, 0x5836, CHIP_RS300|CHIP_IS_IGP, "ATI Radeon RS300 IGP"}, \
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@ -559,7 +559,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
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if (dev_priv->is_pci) {
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#endif
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if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
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&dev_priv->bus_pci_gart)) {
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&dev_priv->bus_pci_gart, 0)) {
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DRM_ERROR("failed to init PCI GART!\n");
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dev->dev_private = (void *)dev_priv;
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r128_do_cleanup_cce(dev);
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805
sys/dev/drm/r300_cmdbuf.c
Normal file
805
sys/dev/drm/r300_cmdbuf.c
Normal file
@ -0,0 +1,805 @@
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/* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
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*
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* Copyright (C) The Weather Channel, Inc. 2002.
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* Copyright (C) 2004 Nicolai Haehnle.
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* All Rights Reserved.
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*
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* The Weather Channel (TM) funded Tungsten Graphics to develop the
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* initial release of the Radeon 8500 driver under the XFree86 license.
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* This notice must be preserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Nicolai Haehnle <prefect_@gmx.net>
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*
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* $FreeBSD$
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*/
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#include "dev/drm/drmP.h"
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#include "dev/drm/drm.h"
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#include "dev/drm/radeon_drm.h"
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#include "dev/drm/radeon_drv.h"
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#include "dev/drm/r300_reg.h"
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#define R300_SIMULTANEOUS_CLIPRECTS 4
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/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
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*/
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static const int r300_cliprect_cntl[4] = {
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0xAAAA,
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0xEEEE,
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0xFEFE,
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0xFFFE
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};
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/**
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* Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
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* buffer, starting with index n.
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*/
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static int r300_emit_cliprects(drm_radeon_private_t* dev_priv,
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drm_radeon_cmd_buffer_t* cmdbuf,
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int n)
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{
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drm_clip_rect_t box;
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int nr;
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int i;
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RING_LOCALS;
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nr = cmdbuf->nbox - n;
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if (nr > R300_SIMULTANEOUS_CLIPRECTS)
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nr = R300_SIMULTANEOUS_CLIPRECTS;
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DRM_DEBUG("%i cliprects\n", nr);
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if (nr) {
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BEGIN_RING(6 + nr*2);
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OUT_RING( CP_PACKET0( R300_RE_CLIPRECT_TL_0, nr*2 - 1 ) );
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for(i = 0; i < nr; ++i) {
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if (DRM_COPY_FROM_USER_UNCHECKED(&box, &cmdbuf->boxes[n+i], sizeof(box))) {
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DRM_ERROR("copy cliprect faulted\n");
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return DRM_ERR(EFAULT);
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}
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box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
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OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
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(box.y1 << R300_CLIPRECT_Y_SHIFT));
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OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
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(box.y2 << R300_CLIPRECT_Y_SHIFT));
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}
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OUT_RING_REG( R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr-1] );
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/* TODO/SECURITY: Force scissors to a safe value, otherwise the
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* client might be able to trample over memory.
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* The impact should be very limited, but I'd rather be safe than
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* sorry.
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*/
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OUT_RING( CP_PACKET0( R300_RE_SCISSORS_TL, 1 ) );
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OUT_RING( 0 );
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OUT_RING( R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK );
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ADVANCE_RING();
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} else {
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/* Why we allow zero cliprect rendering:
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* There are some commands in a command buffer that must be submitted
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* even when there are no cliprects, e.g. DMA buffer discard
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* or state setting (though state setting could be avoided by
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* simulating a loss of context).
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*
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* Now since the cmdbuf interface is so chaotic right now (and is
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* bound to remain that way for a bit until things settle down),
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* it is basically impossible to filter out the commands that are
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* necessary and those that aren't.
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*
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* So I choose the safe way and don't do any filtering at all;
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* instead, I simply set up the engine so that all rendering
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* can't produce any fragments.
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*/
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BEGIN_RING(2);
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OUT_RING_REG( R300_RE_CLIPRECT_CNTL, 0 );
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ADVANCE_RING();
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}
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return 0;
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}
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u8 r300_reg_flags[0x10000>>2];
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void r300_init_reg_flags(void)
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{
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int i;
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memset(r300_reg_flags, 0, 0x10000>>2);
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#define ADD_RANGE_MARK(reg, count,mark) \
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for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
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r300_reg_flags[i]|=(mark);
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#define MARK_SAFE 1
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#define MARK_CHECK_OFFSET 2
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#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
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/* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
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ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
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ADD_RANGE(0x2080, 1);
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ADD_RANGE(R300_SE_VTE_CNTL, 2);
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ADD_RANGE(0x2134, 2);
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ADD_RANGE(0x2140, 1);
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ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
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ADD_RANGE(0x21DC, 1);
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ADD_RANGE(0x221C, 1);
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ADD_RANGE(0x2220, 4);
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ADD_RANGE(0x2288, 1);
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ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
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ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
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ADD_RANGE(R300_GB_ENABLE, 1);
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ADD_RANGE(R300_GB_MSPOS0, 5);
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ADD_RANGE(R300_TX_ENABLE, 1);
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ADD_RANGE(0x4200, 4);
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ADD_RANGE(0x4214, 1);
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ADD_RANGE(R300_RE_POINTSIZE, 1);
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ADD_RANGE(0x4230, 3);
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ADD_RANGE(R300_RE_LINE_CNT, 1);
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ADD_RANGE(0x4238, 1);
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ADD_RANGE(0x4260, 3);
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ADD_RANGE(0x4274, 4);
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ADD_RANGE(0x4288, 5);
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ADD_RANGE(0x42A0, 1);
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ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
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ADD_RANGE(0x42B4, 1);
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ADD_RANGE(R300_RE_CULL_CNTL, 1);
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ADD_RANGE(0x42C0, 2);
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ADD_RANGE(R300_RS_CNTL_0, 2);
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ADD_RANGE(R300_RS_INTERP_0, 8);
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ADD_RANGE(R300_RS_ROUTE_0, 8);
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ADD_RANGE(0x43A4, 2);
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ADD_RANGE(0x43E8, 1);
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ADD_RANGE(R300_PFS_CNTL_0, 3);
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ADD_RANGE(R300_PFS_NODE_0, 4);
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ADD_RANGE(R300_PFS_TEXI_0, 64);
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ADD_RANGE(0x46A4, 5);
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ADD_RANGE(R300_PFS_INSTR0_0, 64);
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ADD_RANGE(R300_PFS_INSTR1_0, 64);
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ADD_RANGE(R300_PFS_INSTR2_0, 64);
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ADD_RANGE(R300_PFS_INSTR3_0, 64);
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ADD_RANGE(0x4BC0, 1);
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ADD_RANGE(0x4BC8, 3);
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ADD_RANGE(R300_PP_ALPHA_TEST, 2);
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ADD_RANGE(0x4BD8, 1);
|
||||
ADD_RANGE(R300_PFS_PARAM_0_X, 64);
|
||||
ADD_RANGE(0x4E00, 1);
|
||||
ADD_RANGE(R300_RB3D_CBLEND, 2);
|
||||
ADD_RANGE(R300_RB3D_COLORMASK, 1);
|
||||
ADD_RANGE(0x4E10, 3);
|
||||
ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
|
||||
ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
|
||||
ADD_RANGE(0x4E50, 9);
|
||||
ADD_RANGE(0x4E88, 1);
|
||||
ADD_RANGE(0x4EA0, 2);
|
||||
ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
|
||||
ADD_RANGE(0x4F10, 4);
|
||||
ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
|
||||
ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
|
||||
ADD_RANGE(0x4F28, 1);
|
||||
ADD_RANGE(0x4F30, 2);
|
||||
ADD_RANGE(0x4F44, 1);
|
||||
ADD_RANGE(0x4F54, 1);
|
||||
|
||||
ADD_RANGE(R300_TX_FILTER_0, 16);
|
||||
ADD_RANGE(R300_TX_UNK1_0, 16);
|
||||
ADD_RANGE(R300_TX_SIZE_0, 16);
|
||||
ADD_RANGE(R300_TX_FORMAT_0, 16);
|
||||
/* Texture offset is dangerous and needs more checking */
|
||||
ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
|
||||
ADD_RANGE(R300_TX_UNK4_0, 16);
|
||||
ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
|
||||
|
||||
/* Sporadic registers used as primitives are emitted */
|
||||
ADD_RANGE(0x4f18, 1);
|
||||
ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
|
||||
ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
|
||||
ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
|
||||
|
||||
}
|
||||
|
||||
static __inline__ int r300_check_range(unsigned reg, int count)
|
||||
{
|
||||
int i;
|
||||
if(reg & ~0xffff)return -1;
|
||||
for(i=(reg>>2);i<(reg>>2)+count;i++)
|
||||
if(r300_reg_flags[i]!=MARK_SAFE)return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* we expect offsets passed to the framebuffer to be either within video memory or
|
||||
within AGP space */
|
||||
static __inline__ int r300_check_offset(drm_radeon_private_t* dev_priv, u32 offset)
|
||||
{
|
||||
/* we realy want to check against end of video aperture
|
||||
but this value is not being kept.
|
||||
This code is correct for now (does the same thing as the
|
||||
code that sets MC_FB_LOCATION) in radeon_cp.c */
|
||||
if((offset>=dev_priv->fb_location) &&
|
||||
(offset<dev_priv->gart_vm_start))return 0;
|
||||
if((offset>=dev_priv->gart_vm_start) &&
|
||||
(offset<dev_priv->gart_vm_start+dev_priv->gart_size))return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf,
|
||||
drm_r300_cmd_header_t header)
|
||||
{
|
||||
int reg;
|
||||
int sz;
|
||||
int i;
|
||||
int values[64];
|
||||
RING_LOCALS;
|
||||
|
||||
sz = header.packet0.count;
|
||||
reg = (header.packet0.reghi << 8) | header.packet0.reglo;
|
||||
|
||||
if((sz>64)||(sz<0)){
|
||||
DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", reg, sz);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
for(i=0;i<sz;i++){
|
||||
values[i]=((int __user*)cmdbuf->buf)[i];
|
||||
switch(r300_reg_flags[(reg>>2)+i]){
|
||||
case MARK_SAFE:
|
||||
break;
|
||||
case MARK_CHECK_OFFSET:
|
||||
if(r300_check_offset(dev_priv, (u32)values[i])){
|
||||
DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n", reg, sz);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Register %04x failed check as flag=%02x\n", reg+i*4, r300_reg_flags[(reg>>2)+i]);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
BEGIN_RING(1+sz);
|
||||
OUT_RING( CP_PACKET0( reg, sz-1 ) );
|
||||
OUT_RING_TABLE( values, sz );
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += sz*4;
|
||||
cmdbuf->bufsz -= sz*4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Emits a packet0 setting arbitrary registers.
|
||||
* Called by r300_do_cp_cmdbuf.
|
||||
*
|
||||
* Note that checks are performed on contents and addresses of the registers
|
||||
*/
|
||||
static __inline__ int r300_emit_packet0(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf,
|
||||
drm_r300_cmd_header_t header)
|
||||
{
|
||||
int reg;
|
||||
int sz;
|
||||
RING_LOCALS;
|
||||
|
||||
sz = header.packet0.count;
|
||||
reg = (header.packet0.reghi << 8) | header.packet0.reglo;
|
||||
|
||||
if (!sz)
|
||||
return 0;
|
||||
|
||||
if (sz*4 > cmdbuf->bufsz)
|
||||
return DRM_ERR(EINVAL);
|
||||
|
||||
if (reg+sz*4 >= 0x10000){
|
||||
DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, sz);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if(r300_check_range(reg, sz)){
|
||||
/* go and check everything */
|
||||
return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, header);
|
||||
}
|
||||
/* the rest of the data is safe to emit, whatever the values the user passed */
|
||||
|
||||
BEGIN_RING(1+sz);
|
||||
OUT_RING( CP_PACKET0( reg, sz-1 ) );
|
||||
OUT_RING_TABLE( (int __user*)cmdbuf->buf, sz );
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += sz*4;
|
||||
cmdbuf->bufsz -= sz*4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Uploads user-supplied vertex program instructions or parameters onto
|
||||
* the graphics card.
|
||||
* Called by r300_do_cp_cmdbuf.
|
||||
*/
|
||||
static __inline__ int r300_emit_vpu(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf,
|
||||
drm_r300_cmd_header_t header)
|
||||
{
|
||||
int sz;
|
||||
int addr;
|
||||
RING_LOCALS;
|
||||
|
||||
sz = header.vpu.count;
|
||||
addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
|
||||
|
||||
if (!sz)
|
||||
return 0;
|
||||
if (sz*16 > cmdbuf->bufsz)
|
||||
return DRM_ERR(EINVAL);
|
||||
|
||||
BEGIN_RING(5+sz*4);
|
||||
/* Wait for VAP to come to senses.. */
|
||||
/* there is no need to emit it multiple times, (only once before VAP is programmed,
|
||||
but this optimization is for later */
|
||||
OUT_RING_REG( R300_VAP_PVS_WAITIDLE, 0 );
|
||||
OUT_RING_REG( R300_VAP_PVS_UPLOAD_ADDRESS, addr );
|
||||
OUT_RING( CP_PACKET0_TABLE( R300_VAP_PVS_UPLOAD_DATA, sz*4 - 1 ) );
|
||||
OUT_RING_TABLE( (int __user*)cmdbuf->buf, sz*4 );
|
||||
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += sz*16;
|
||||
cmdbuf->bufsz -= sz*16;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Emit a clear packet from userspace.
|
||||
* Called by r300_emit_packet3.
|
||||
*/
|
||||
static __inline__ int r300_emit_clear(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf)
|
||||
{
|
||||
RING_LOCALS;
|
||||
|
||||
if (8*4 > cmdbuf->bufsz)
|
||||
return DRM_ERR(EINVAL);
|
||||
|
||||
BEGIN_RING(10);
|
||||
OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 8 ) );
|
||||
OUT_RING( R300_PRIM_TYPE_POINT|R300_PRIM_WALK_RING|
|
||||
(1<<R300_PRIM_NUM_VERTICES_SHIFT) );
|
||||
OUT_RING_TABLE( (int __user*)cmdbuf->buf, 8 );
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += 8*4;
|
||||
cmdbuf->bufsz -= 8*4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf,
|
||||
u32 header)
|
||||
{
|
||||
int count, i,k;
|
||||
#define MAX_ARRAY_PACKET 64
|
||||
u32 payload[MAX_ARRAY_PACKET];
|
||||
u32 narrays;
|
||||
RING_LOCALS;
|
||||
|
||||
count=(header>>16) & 0x3fff;
|
||||
|
||||
if((count+1)>MAX_ARRAY_PACKET){
|
||||
DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
memset(payload, 0, MAX_ARRAY_PACKET*4);
|
||||
memcpy(payload, cmdbuf->buf+4, (count+1)*4);
|
||||
|
||||
/* carefully check packet contents */
|
||||
|
||||
narrays=payload[0];
|
||||
k=0;
|
||||
i=1;
|
||||
while((k<narrays) && (i<(count+1))){
|
||||
i++; /* skip attribute field */
|
||||
if(r300_check_offset(dev_priv, payload[i])){
|
||||
DRM_ERROR("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
k++;
|
||||
i++;
|
||||
if(k==narrays)break;
|
||||
/* have one more to process, they come in pairs */
|
||||
if(r300_check_offset(dev_priv, payload[i])){
|
||||
DRM_ERROR("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
k++;
|
||||
i++;
|
||||
}
|
||||
/* do the counts match what we expect ? */
|
||||
if((k!=narrays) || (i!=(count+1))){
|
||||
DRM_ERROR("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", k, i, narrays, count+1);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* all clear, output packet */
|
||||
|
||||
BEGIN_RING(count+2);
|
||||
OUT_RING(header);
|
||||
OUT_RING_TABLE(payload, count+1);
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += (count+2)*4;
|
||||
cmdbuf->bufsz -= (count+2)*4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf)
|
||||
{
|
||||
u32 header;
|
||||
int count;
|
||||
RING_LOCALS;
|
||||
|
||||
if (4 > cmdbuf->bufsz)
|
||||
return DRM_ERR(EINVAL);
|
||||
|
||||
/* Fixme !! This simply emits a packet without much checking.
|
||||
We need to be smarter. */
|
||||
|
||||
/* obtain first word - actual packet3 header */
|
||||
header = *(u32 __user*)cmdbuf->buf;
|
||||
|
||||
/* Is it packet 3 ? */
|
||||
if( (header>>30)!=0x3 ) {
|
||||
DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
count=(header>>16) & 0x3fff;
|
||||
|
||||
/* Check again now that we know how much data to expect */
|
||||
if ((count+2)*4 > cmdbuf->bufsz){
|
||||
DRM_ERROR("Expected packet3 of length %d but have only %d bytes left\n",
|
||||
(count+2)*4, cmdbuf->bufsz);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* Is it a packet type we know about ? */
|
||||
switch(header & 0xff00){
|
||||
case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
|
||||
return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
|
||||
|
||||
case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
|
||||
case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
|
||||
case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
|
||||
case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
|
||||
case RADEON_WAIT_FOR_IDLE:
|
||||
case RADEON_CP_NOP:
|
||||
/* these packets are safe */
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
|
||||
BEGIN_RING(count+2);
|
||||
OUT_RING(header);
|
||||
OUT_RING_TABLE( (int __user*)(cmdbuf->buf+4), count+1);
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += (count+2)*4;
|
||||
cmdbuf->bufsz -= (count+2)*4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Emit a rendering packet3 from userspace.
|
||||
* Called by r300_do_cp_cmdbuf.
|
||||
*/
|
||||
static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf,
|
||||
drm_r300_cmd_header_t header)
|
||||
{
|
||||
int n;
|
||||
int ret;
|
||||
char __user* orig_buf = cmdbuf->buf;
|
||||
int orig_bufsz = cmdbuf->bufsz;
|
||||
|
||||
/* This is a do-while-loop so that we run the interior at least once,
|
||||
* even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
|
||||
*/
|
||||
n = 0;
|
||||
do {
|
||||
if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
|
||||
ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cmdbuf->buf = orig_buf;
|
||||
cmdbuf->bufsz = orig_bufsz;
|
||||
}
|
||||
|
||||
switch(header.packet3.packet) {
|
||||
case R300_CMD_PACKET3_CLEAR:
|
||||
DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
|
||||
ret = r300_emit_clear(dev_priv, cmdbuf);
|
||||
if (ret) {
|
||||
DRM_ERROR("r300_emit_clear failed\n");
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
|
||||
case R300_CMD_PACKET3_RAW:
|
||||
DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
|
||||
ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
|
||||
if (ret) {
|
||||
DRM_ERROR("r300_emit_raw_packet3 failed\n");
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
DRM_ERROR("bad packet3 type %i at %p\n",
|
||||
header.packet3.packet,
|
||||
cmdbuf->buf - sizeof(header));
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
n += R300_SIMULTANEOUS_CLIPRECTS;
|
||||
} while(n < cmdbuf->nbox);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Some of the R300 chips seem to be extremely touchy about the two registers
|
||||
* that are configured in r300_pacify.
|
||||
* Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
|
||||
* sends a command buffer that contains only state setting commands and a
|
||||
* vertex program/parameter upload sequence, this will eventually lead to a
|
||||
* lockup, unless the sequence is bracketed by calls to r300_pacify.
|
||||
* So we should take great care to *always* call r300_pacify before
|
||||
* *anything* 3D related, and again afterwards. This is what the
|
||||
* call bracket in r300_do_cp_cmdbuf is for.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Emit the sequence to pacify R300.
|
||||
*/
|
||||
static __inline__ void r300_pacify(drm_radeon_private_t* dev_priv)
|
||||
{
|
||||
RING_LOCALS;
|
||||
|
||||
BEGIN_RING(6);
|
||||
OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) );
|
||||
OUT_RING( 0xa );
|
||||
OUT_RING( CP_PACKET0( 0x4f18, 0 ) );
|
||||
OUT_RING( 0x3 );
|
||||
OUT_RING( CP_PACKET3( RADEON_CP_NOP, 0 ) );
|
||||
OUT_RING( 0x0 );
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
|
||||
* The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
|
||||
* be careful about how this function is called.
|
||||
*/
|
||||
static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
|
||||
|
||||
buf_priv->age = dev_priv->sarea_priv->last_dispatch+1;
|
||||
buf->pending = 1;
|
||||
buf->used = 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Parses and validates a user-supplied command buffer and emits appropriate
|
||||
* commands on the DMA ring buffer.
|
||||
* Called by the ioctl handler function radeon_cp_cmdbuf.
|
||||
*/
|
||||
int r300_do_cp_cmdbuf(drm_device_t* dev,
|
||||
DRMFILE filp,
|
||||
drm_file_t* filp_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_buf_t *buf = NULL;
|
||||
int emit_dispatch_age = 0;
|
||||
int ret = 0;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
|
||||
/* See the comment above r300_emit_begin3d for why this call must be here,
|
||||
* and what the cleanup gotos are for. */
|
||||
r300_pacify(dev_priv);
|
||||
|
||||
if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
|
||||
ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
|
||||
if (ret)
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
while(cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
|
||||
int idx;
|
||||
drm_r300_cmd_header_t header;
|
||||
|
||||
header.u = *(unsigned int *)cmdbuf->buf;
|
||||
|
||||
cmdbuf->buf += sizeof(header);
|
||||
cmdbuf->bufsz -= sizeof(header);
|
||||
|
||||
switch(header.header.cmd_type) {
|
||||
case R300_CMD_PACKET0:
|
||||
DRM_DEBUG("R300_CMD_PACKET0\n");
|
||||
ret = r300_emit_packet0(dev_priv, cmdbuf, header);
|
||||
if (ret) {
|
||||
DRM_ERROR("r300_emit_packet0 failed\n");
|
||||
goto cleanup;
|
||||
}
|
||||
break;
|
||||
|
||||
case R300_CMD_VPU:
|
||||
DRM_DEBUG("R300_CMD_VPU\n");
|
||||
ret = r300_emit_vpu(dev_priv, cmdbuf, header);
|
||||
if (ret) {
|
||||
DRM_ERROR("r300_emit_vpu failed\n");
|
||||
goto cleanup;
|
||||
}
|
||||
break;
|
||||
|
||||
case R300_CMD_PACKET3:
|
||||
DRM_DEBUG("R300_CMD_PACKET3\n");
|
||||
ret = r300_emit_packet3(dev_priv, cmdbuf, header);
|
||||
if (ret) {
|
||||
DRM_ERROR("r300_emit_packet3 failed\n");
|
||||
goto cleanup;
|
||||
}
|
||||
break;
|
||||
|
||||
case R300_CMD_END3D:
|
||||
DRM_DEBUG("R300_CMD_END3D\n");
|
||||
/* TODO:
|
||||
Ideally userspace driver should not need to issue this call,
|
||||
i.e. the drm driver should issue it automatically and prevent
|
||||
lockups.
|
||||
|
||||
In practice, we do not understand why this call is needed and what
|
||||
it does (except for some vague guesses that it has to do with cache
|
||||
coherence) and so the user space driver does it.
|
||||
|
||||
Once we are sure which uses prevent lockups the code could be moved
|
||||
into the kernel and the userspace driver will not
|
||||
need to use this command.
|
||||
|
||||
Note that issuing this command does not hurt anything
|
||||
except, possibly, performance */
|
||||
r300_pacify(dev_priv);
|
||||
break;
|
||||
|
||||
case R300_CMD_CP_DELAY:
|
||||
/* simple enough, we can do it here */
|
||||
DRM_DEBUG("R300_CMD_CP_DELAY\n");
|
||||
{
|
||||
int i;
|
||||
RING_LOCALS;
|
||||
|
||||
BEGIN_RING(header.delay.count);
|
||||
for(i=0;i<header.delay.count;i++)
|
||||
OUT_RING(RADEON_CP_PACKET2);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
break;
|
||||
|
||||
case R300_CMD_DMA_DISCARD:
|
||||
DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
|
||||
idx = header.dma.buf_idx;
|
||||
if (idx < 0 || idx >= dma->buf_count) {
|
||||
DRM_ERROR("buffer index %d (of %d max)\n",
|
||||
idx, dma->buf_count - 1);
|
||||
ret = DRM_ERR(EINVAL);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
buf = dma->buflist[idx];
|
||||
if (buf->filp != filp || buf->pending) {
|
||||
DRM_ERROR("bad buffer %p %p %d\n",
|
||||
buf->filp, filp, buf->pending);
|
||||
ret = DRM_ERR(EINVAL);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
emit_dispatch_age = 1;
|
||||
r300_discard_buffer(dev, buf);
|
||||
break;
|
||||
|
||||
case R300_CMD_WAIT:
|
||||
/* simple enough, we can do it here */
|
||||
DRM_DEBUG("R300_CMD_WAIT\n");
|
||||
if(header.wait.flags==0)break; /* nothing to do */
|
||||
|
||||
{
|
||||
RING_LOCALS;
|
||||
|
||||
BEGIN_RING(2);
|
||||
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );
|
||||
OUT_RING( (header.wait.flags & 0xf)<<14 );
|
||||
ADVANCE_RING();
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
DRM_ERROR("bad cmd_type %i at %p\n",
|
||||
header.header.cmd_type,
|
||||
cmdbuf->buf - sizeof(header));
|
||||
ret = DRM_ERR(EINVAL);
|
||||
goto cleanup;
|
||||
}
|
||||
}
|
||||
|
||||
DRM_DEBUG("END\n");
|
||||
|
||||
cleanup:
|
||||
r300_pacify(dev_priv);
|
||||
|
||||
/* We emit the vertex buffer age here, outside the pacifier "brackets"
|
||||
* for two reasons:
|
||||
* (1) This may coalesce multiple age emissions into a single one and
|
||||
* (2) more importantly, some chips lock up hard when scratch registers
|
||||
* are written inside the pacifier bracket.
|
||||
*/
|
||||
if (emit_dispatch_age) {
|
||||
RING_LOCALS;
|
||||
|
||||
dev_priv->sarea_priv->last_dispatch++;
|
||||
|
||||
/* Emit the vertex buffer age */
|
||||
BEGIN_RING(2);
|
||||
RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
COMMIT_RING();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
1416
sys/dev/drm/r300_reg.h
Normal file
1416
sys/dev/drm/r300_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -34,6 +34,7 @@
|
||||
#include "dev/drm/drm.h"
|
||||
#include "dev/drm/radeon_drm.h"
|
||||
#include "dev/drm/radeon_drv.h"
|
||||
#include "dev/drm/r300_reg.h"
|
||||
|
||||
#define RADEON_FIFO_DEBUG 0
|
||||
|
||||
@ -825,6 +826,12 @@ static int RADEON_READ_PLL(drm_device_t * dev, int addr)
|
||||
return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
|
||||
}
|
||||
|
||||
static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
|
||||
{
|
||||
RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
|
||||
return RADEON_READ(RADEON_PCIE_DATA);
|
||||
}
|
||||
|
||||
#if RADEON_FIFO_DEBUG
|
||||
static void radeon_status(drm_radeon_private_t * dev_priv)
|
||||
{
|
||||
@ -1133,6 +1140,7 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
|
||||
ring_start = (dev_priv->cp_ring->offset
|
||||
- dev->sg->handle + dev_priv->gart_vm_start);
|
||||
|
||||
|
||||
RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
|
||||
|
||||
/* Set the write pointer delay */
|
||||
@ -1233,11 +1241,38 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
|
||||
RADEON_ISYNC_CPSCRATCH_IDLEGUI));
|
||||
}
|
||||
|
||||
/* Enable or disable PCI-E GART on the chip */
|
||||
static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
|
||||
{
|
||||
u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
|
||||
if (on) {
|
||||
|
||||
DRM_DEBUG("programming pcie %08X %08lX %08X\n", dev_priv->gart_vm_start, dev_priv->bus_pci_gart,dev_priv->gart_size);
|
||||
RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start);
|
||||
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->bus_pci_gart);
|
||||
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start);
|
||||
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start
|
||||
+ dev_priv->gart_size - 1);
|
||||
|
||||
RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
|
||||
|
||||
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN | RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD | RADEON_PCIE_TX_GART_CHK_RW_VALID_EN);
|
||||
} else {
|
||||
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable or disable PCI GART on the chip */
|
||||
static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
|
||||
{
|
||||
u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
|
||||
|
||||
if (dev_priv->flags & CHIP_IS_PCIE)
|
||||
{
|
||||
radeon_set_pciegart(dev_priv, on);
|
||||
return;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
RADEON_WRITE(RADEON_AIC_CNTL,
|
||||
tmp | RADEON_PCIGART_TRANSLATE_EN);
|
||||
@ -1499,7 +1534,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
|
||||
#endif
|
||||
{
|
||||
if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
|
||||
&dev_priv->bus_pci_gart)) {
|
||||
&dev_priv->bus_pci_gart, (dev_priv->flags & CHIP_IS_PCIE))) {
|
||||
DRM_ERROR("failed to init PCI GART!\n");
|
||||
radeon_do_cleanup_cp(dev);
|
||||
return DRM_ERR(ENOMEM);
|
||||
@ -1608,6 +1643,9 @@ int radeon_cp_init(DRM_IOCTL_ARGS)
|
||||
DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
|
||||
sizeof(init));
|
||||
|
||||
if(init.func == RADEON_INIT_R300_CP)
|
||||
r300_init_reg_flags();
|
||||
|
||||
switch (init.func) {
|
||||
case RADEON_INIT_CP:
|
||||
case RADEON_INIT_R200_CP:
|
||||
@ -2024,6 +2062,7 @@ int radeon_preinit(struct drm_device *dev, unsigned long flags)
|
||||
case CHIP_RV200:
|
||||
case CHIP_R200:
|
||||
case CHIP_R300:
|
||||
case CHIP_R420:
|
||||
dev_priv->flags |= CHIP_HAS_HIERZ;
|
||||
break;
|
||||
default:
|
||||
@ -2056,8 +2095,11 @@ int radeon_preinit(struct drm_device *dev, unsigned long flags)
|
||||
if (drm_device_is_agp(dev))
|
||||
dev_priv->flags |= CHIP_IS_AGP;
|
||||
|
||||
if (drm_device_is_pcie(dev))
|
||||
dev_priv->flags |= CHIP_IS_PCIE;
|
||||
|
||||
DRM_DEBUG("%s card detected\n",
|
||||
((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
|
||||
((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
|
||||
|
||||
#if defined(__linux__)
|
||||
/* Check if we need a reset */
|
||||
|
||||
@ -195,6 +195,53 @@ typedef union {
|
||||
#define RADEON_WAIT_2D 0x1
|
||||
#define RADEON_WAIT_3D 0x2
|
||||
|
||||
/* Allowed parameters for R300_CMD_PACKET3
|
||||
*/
|
||||
#define R300_CMD_PACKET3_CLEAR 0
|
||||
#define R300_CMD_PACKET3_RAW 1
|
||||
|
||||
/* Commands understood by cmd_buffer ioctl for R300.
|
||||
* The interface has not been stabilized, so some of these may be removed
|
||||
* and eventually reordered before stabilization.
|
||||
*/
|
||||
#define R300_CMD_PACKET0 1
|
||||
#define R300_CMD_VPU 2 /* emit vertex program upload */
|
||||
#define R300_CMD_PACKET3 3 /* emit a packet3 */
|
||||
#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
|
||||
#define R300_CMD_CP_DELAY 5
|
||||
#define R300_CMD_DMA_DISCARD 6
|
||||
#define R300_CMD_WAIT 7
|
||||
# define R300_WAIT_2D 0x1
|
||||
# define R300_WAIT_3D 0x2
|
||||
# define R300_WAIT_2D_CLEAN 0x3
|
||||
# define R300_WAIT_3D_CLEAN 0x4
|
||||
|
||||
typedef union {
|
||||
unsigned int u;
|
||||
struct {
|
||||
unsigned char cmd_type, pad0, pad1, pad2;
|
||||
} header;
|
||||
struct {
|
||||
unsigned char cmd_type, count, reglo, reghi;
|
||||
} packet0;
|
||||
struct {
|
||||
unsigned char cmd_type, count, adrlo, adrhi;
|
||||
} vpu;
|
||||
struct {
|
||||
unsigned char cmd_type, packet, pad0, pad1;
|
||||
} packet3;
|
||||
struct {
|
||||
unsigned char cmd_type, packet;
|
||||
unsigned short count; /* amount of packet2 to emit */
|
||||
} delay;
|
||||
struct {
|
||||
unsigned char cmd_type, buf_idx, pad0, pad1;
|
||||
} dma;
|
||||
struct {
|
||||
unsigned char cmd_type, flags, pad0, pad1;
|
||||
} wait;
|
||||
} drm_r300_cmd_header_t;
|
||||
|
||||
#define RADEON_FRONT 0x1
|
||||
#define RADEON_BACK 0x2
|
||||
#define RADEON_DEPTH 0x4
|
||||
|
||||
@ -107,7 +107,9 @@ enum radeon_family {
|
||||
CHIP_RV280,
|
||||
CHIP_R300,
|
||||
CHIP_RS300,
|
||||
CHIP_R350,
|
||||
CHIP_RV350,
|
||||
CHIP_R420,
|
||||
CHIP_LAST,
|
||||
};
|
||||
|
||||
@ -128,6 +130,7 @@ enum radeon_chip_flags {
|
||||
CHIP_SINGLE_CRTC = 0x00040000UL,
|
||||
CHIP_IS_AGP = 0x00080000UL,
|
||||
CHIP_HAS_HIERZ = 0x00100000UL,
|
||||
CHIP_IS_PCIE = 0x00200000UL,
|
||||
};
|
||||
|
||||
#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
|
||||
@ -321,6 +324,14 @@ extern int radeon_driver_open_helper(drm_device_t * dev,
|
||||
extern void radeon_driver_free_filp_priv(drm_device_t * dev,
|
||||
drm_file_t * filp_priv);
|
||||
|
||||
/* r300_cmdbuf.c */
|
||||
extern void r300_init_reg_flags(void);
|
||||
|
||||
extern int r300_do_cp_cmdbuf( drm_device_t* dev,
|
||||
DRMFILE filp,
|
||||
drm_file_t* filp_priv,
|
||||
drm_radeon_cmd_buffer_t* cmdbuf );
|
||||
|
||||
/* Flags for stats.boxes
|
||||
*/
|
||||
#define RADEON_BOX_DMA_IDLE 0x1
|
||||
@ -358,6 +369,25 @@ extern void radeon_driver_free_filp_priv(drm_device_t * dev,
|
||||
#define RADEON_CRTC2_OFFSET 0x0324
|
||||
#define RADEON_CRTC2_OFFSET_CNTL 0x0328
|
||||
|
||||
#define RADEON_PCIE_INDEX 0x0030
|
||||
#define RADEON_PCIE_DATA 0x0034
|
||||
#define RADEON_PCIE_TX_GART_CNTL 0x10
|
||||
# define RADEON_PCIE_TX_GART_EN (1 << 0)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
|
||||
# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
|
||||
# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
|
||||
# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
|
||||
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
|
||||
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
|
||||
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
|
||||
#define RADEON_PCIE_TX_GART_BASE 0x13
|
||||
#define RADEON_PCIE_TX_GART_START_LO 0x14
|
||||
#define RADEON_PCIE_TX_GART_START_HI 0x15
|
||||
#define RADEON_PCIE_TX_GART_END_LO 0x16
|
||||
#define RADEON_PCIE_TX_GART_END_HI 0x17
|
||||
|
||||
#define RADEON_MPP_TB_CONFIG 0x01c0
|
||||
#define RADEON_MEM_CNTL 0x0140
|
||||
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
|
||||
@ -603,6 +633,8 @@ extern void radeon_driver_free_filp_priv(drm_device_t * dev,
|
||||
|
||||
#define RADEON_WAIT_UNTIL 0x1720
|
||||
# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
|
||||
# define RADEON_WAIT_2D_IDLE (1 << 14)
|
||||
# define RADEON_WAIT_3D_IDLE (1 << 15)
|
||||
# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
|
||||
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
|
||||
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
|
||||
@ -655,16 +687,27 @@ extern void radeon_driver_free_filp_priv(drm_device_t * dev,
|
||||
#define RADEON_CP_PACKET1 0x40000000
|
||||
#define RADEON_CP_PACKET2 0x80000000
|
||||
#define RADEON_CP_PACKET3 0xC0000000
|
||||
# define RADEON_CP_NOP 0x00001000
|
||||
# define RADEON_CP_NEXT_CHAR 0x00001900
|
||||
# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
|
||||
# define RADEON_CP_SET_SCISSORS 0x00001E00
|
||||
/* GEN_INDX_PRIM is unsupported starting with R300 */
|
||||
# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
|
||||
# define RADEON_WAIT_FOR_IDLE 0x00002600
|
||||
# define RADEON_3D_DRAW_VBUF 0x00002800
|
||||
# define RADEON_3D_DRAW_IMMD 0x00002900
|
||||
# define RADEON_3D_DRAW_INDX 0x00002A00
|
||||
# define RADEON_CP_LOAD_PALETTE 0x00002C00
|
||||
# define RADEON_3D_LOAD_VBPNTR 0x00002F00
|
||||
# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
|
||||
# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
|
||||
# define RADEON_3D_CLEAR_ZMASK 0x00003200
|
||||
# define RADEON_CP_INDX_BUFFER 0x00003300
|
||||
# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
|
||||
# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
|
||||
# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
|
||||
# define RADEON_3D_CLEAR_HIZ 0x00003700
|
||||
# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
|
||||
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
|
||||
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
|
||||
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
|
||||
@ -859,6 +902,13 @@ do { \
|
||||
RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_PCIE( addr, val ) \
|
||||
do { \
|
||||
RADEON_WRITE8( RADEON_PCIE_INDEX, \
|
||||
((addr) & 0xff)); \
|
||||
RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
|
||||
} while (0)
|
||||
|
||||
extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
|
||||
extern int radeon_postcleanup(struct drm_device *dev);
|
||||
|
||||
|
||||
@ -1475,7 +1475,7 @@ static void radeon_cp_dispatch_indices(drm_device_t * dev,
|
||||
|
||||
}
|
||||
|
||||
#define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
|
||||
#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
|
||||
|
||||
static int radeon_cp_dispatch_texture(DRMFILE filp,
|
||||
drm_device_t * dev,
|
||||
@ -1488,10 +1488,11 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
|
||||
u32 format;
|
||||
u32 *buffer;
|
||||
const u8 __user *data;
|
||||
int size, dwords, tex_width, blit_width;
|
||||
int size, dwords, tex_width, blit_width, spitch;
|
||||
u32 height;
|
||||
int i;
|
||||
u32 texpitch, microtile;
|
||||
u32 offset;
|
||||
RING_LOCALS;
|
||||
|
||||
DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
|
||||
@ -1512,16 +1513,6 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
|
||||
RADEON_WAIT_UNTIL_IDLE();
|
||||
ADVANCE_RING();
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
/* The Mesa texture functions provide the data in little endian as the
|
||||
* chip wants it, but we need to compensate for the fact that the CP
|
||||
* ring gets byte-swapped
|
||||
*/
|
||||
BEGIN_RING(2);
|
||||
OUT_RING_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT);
|
||||
ADVANCE_RING();
|
||||
#endif
|
||||
|
||||
/* The compiler won't optimize away a division by a variable,
|
||||
* even if the only legal values are powers of two. Thus, we'll
|
||||
* use a shift instead.
|
||||
@ -1553,6 +1544,10 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
|
||||
DRM_ERROR("invalid texture format %d\n", tex->format);
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
spitch = blit_width >> 6;
|
||||
if (spitch == 0 && image->height > 1)
|
||||
return DRM_ERR(EINVAL);
|
||||
|
||||
texpitch = tex->pitch;
|
||||
if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
|
||||
microtile = 1;
|
||||
@ -1605,23 +1600,6 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
|
||||
buffer =
|
||||
(u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
|
||||
dwords = size / 4;
|
||||
buffer[0] = CP_PACKET3(RADEON_CNTL_HOSTDATA_BLT, dwords + 6);
|
||||
buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_BRUSH_NONE |
|
||||
(format << 8) |
|
||||
RADEON_GMC_SRC_DATATYPE_COLOR |
|
||||
RADEON_ROP3_S |
|
||||
RADEON_DP_SRC_SOURCE_HOST_DATA |
|
||||
RADEON_GMC_CLR_CMP_CNTL_DIS |
|
||||
RADEON_GMC_WR_MSK_DIS);
|
||||
|
||||
buffer[2] = (texpitch << 22) | (tex->offset >> 10);
|
||||
buffer[3] = 0xffffffff;
|
||||
buffer[4] = 0xffffffff;
|
||||
buffer[5] = (image->y << 16) | image->x;
|
||||
buffer[6] = (height << 16) | image->width;
|
||||
buffer[7] = dwords;
|
||||
buffer += 8;
|
||||
|
||||
if (microtile) {
|
||||
/* texture micro tiling in use, minimum texture width is thus 16 bytes.
|
||||
@ -1730,8 +1708,27 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
|
||||
}
|
||||
|
||||
buf->filp = filp;
|
||||
buf->used = (dwords + 8) * sizeof(u32);
|
||||
radeon_cp_dispatch_indirect(dev, buf, 0, buf->used);
|
||||
buf->used = size;
|
||||
offset = dev_priv->gart_buffers_offset + buf->offset;
|
||||
BEGIN_RING(9);
|
||||
OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
|
||||
OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_BRUSH_NONE |
|
||||
(format << 8) |
|
||||
RADEON_GMC_SRC_DATATYPE_COLOR |
|
||||
RADEON_ROP3_S |
|
||||
RADEON_DP_SRC_SOURCE_MEMORY |
|
||||
RADEON_GMC_CLR_CMP_CNTL_DIS |
|
||||
RADEON_GMC_WR_MSK_DIS );
|
||||
OUT_RING((spitch << 22) | (offset >> 10));
|
||||
OUT_RING((texpitch << 22) | (tex->offset >> 10));
|
||||
OUT_RING(0);
|
||||
OUT_RING((image->x << 16) | image->y);
|
||||
OUT_RING((image->width << 16) | height);
|
||||
RADEON_WAIT_UNTIL_2D_IDLE();
|
||||
ADVANCE_RING();
|
||||
|
||||
radeon_cp_discard_buffer(dev, buf);
|
||||
|
||||
/* Update the input parameters for next time */
|
||||
@ -2771,7 +2768,18 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
|
||||
}
|
||||
|
||||
orig_nbox = cmdbuf.nbox;
|
||||
|
||||
|
||||
if(dev_priv->microcode_version == UCODE_R300) {
|
||||
int temp;
|
||||
temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
|
||||
|
||||
if (orig_bufsz != 0)
|
||||
drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
/* microcode_version != r300 */
|
||||
while (cmdbuf.bufsz >= sizeof(header)) {
|
||||
header.i = *(int *)cmdbuf.buf;
|
||||
cmdbuf.buf += sizeof(header);
|
||||
@ -2866,6 +2874,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
|
||||
drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
|
||||
DRM_DEBUG("DONE\n");
|
||||
COMMIT_RING();
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
|
||||
@ -458,7 +458,7 @@ device drm # DRM core module required by DRM drivers
|
||||
device mach64drm # ATI Rage Pro, Rage Mobility P/M, Rage XL
|
||||
device mgadrm # AGP Matrox G200, G400, G450, G550
|
||||
device r128drm # ATI Rage 128
|
||||
device radeondrm # ATI Radeon up to 9200
|
||||
device radeondrm # ATI Radeon
|
||||
device sisdrm # SiS 300/305, 540, 630
|
||||
device tdfxdrm # 3dfx Voodoo 3/4/5 and Banshee
|
||||
options DRM_DEBUG # Include debug printfs (slow)
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
.PATH: ${.CURDIR}/../../../dev/drm
|
||||
KMOD = radeon
|
||||
SRCS = radeon_cp.c radeon_drv.c radeon_irq.c \
|
||||
SRCS = r300_cmdbuf.c radeon_cp.c radeon_drv.c radeon_irq.c \
|
||||
radeon_mem.c radeon_state.c
|
||||
SRCS +=device_if.h bus_if.h pci_if.h opt_drm.h
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user