More fully support 64-bit bars. Prior to this commit, we supported
only those bars that had addresses assigned by the BIOS and where the bridges were properly programmed. Now even unprogrammed ones work. This was needed for sun4v. We still only implement up to 2GB memory ranges, even for 64-bit bars. PCI standards at least through 2.2 say that this is the max (or 1GB is, I only know it is < 32bits). o Always define pci_addr_t as uint64_t. A pci address is always 64-bits, but some hosts can't address all of them. o Preserve the upper half of the 64-bit word during resource probing. o Test to make sure that 64-bit values can fit in a u_long (true on some platforms, but not others). Don't use those that can't. o minor pedantry about data sizes. o Better bridge resource reporting in bootverbose case. o Minor formatting changes to cope with different data types on different platforms. Submitted by: jmg, with many changes by me to fully support 64-bit addresses.
This commit is contained in:
Warner Losh
parent
a930f272de
commit
b0a2d4b8a9
@ -245,7 +245,7 @@ pci_find_device(uint16_t vendor, uint16_t device)
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/* return base address of memory or port map */
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static uint32_t
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pci_mapbase(unsigned mapreg)
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pci_mapbase(uint32_t mapreg)
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{
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int mask = 0x03;
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if ((mapreg & 0x01) == 0)
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@ -275,7 +275,7 @@ pci_maptype(unsigned mapreg)
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/* return log2 of map size decoded for memory or port map */
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static int
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pci_mapsize(unsigned testval)
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pci_mapsize(uint32_t testval)
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{
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int ln2size;
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@ -1211,8 +1211,8 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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int prefetch)
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{
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uint32_t map;
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uint64_t base;
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uint64_t start, end, count;
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pci_addr_t base;
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pci_addr_t start, end, count;
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uint8_t ln2size;
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uint8_t ln2range;
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uint32_t testval;
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@ -1252,11 +1252,9 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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if (ln2range == 64)
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/* Read the other half of a 64bit map register */
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base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
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if (bootverbose) {
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printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
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reg, pci_maptype(map), ln2range,
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(unsigned int) base, ln2size);
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printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d",
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reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
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printf(", port disabled\n");
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else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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@ -1278,7 +1276,11 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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*/
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if (!force && (base == 0 || map == testval))
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return (barlen);
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if ((u_long)base != base) {
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device_printf(bus,
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"pci%d:%d:%d bar %#x too many address bits", b, s, f, reg);
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return (barlen);
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}
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/*
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* This code theoretically does the right thing, but has
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* undesirable side effects in some cases where peripherals
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@ -1313,6 +1315,13 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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start = base;
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end = base + (1 << ln2size) - 1;
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}
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if ((u_long)start != start) {
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/* Wait a minute! this platform can't do this address. */
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device_printf(bus,
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"pci%d.%d.%x bar %#x start %#jx, too many bits.",
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b, s, f, reg, (uintmax_t)start);
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return (barlen);
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}
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resource_list_add(rl, type, reg, start, end, count);
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/*
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@ -1321,8 +1330,12 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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*/
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res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
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prefetch ? RF_PREFETCHABLE : 0);
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if (res != NULL)
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if (res != NULL) {
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pci_write_config(dev, reg, rman_get_start(res), 4);
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if (ln2range == 64)
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pci_write_config(dev, reg + 4,
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rman_get_start(res) >> 32, 4);
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}
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return (barlen);
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}
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@ -2139,7 +2152,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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struct resource_list *rl = &dinfo->resources;
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struct resource_list_entry *rle;
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struct resource *res;
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uint32_t map, testval;
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pci_addr_t map, testval;
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int mapsize;
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/*
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@ -2153,6 +2166,8 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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map = pci_read_config(child, *rid, 4);
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pci_write_config(child, *rid, 0xffffffff, 4);
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testval = pci_read_config(child, *rid, 4);
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if (pci_maprange(testval) == 64)
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map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
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if (pci_mapbase(testval) == 0)
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goto out;
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if (pci_maptype(testval) & PCI_MAPMEM) {
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@ -2182,7 +2197,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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* another driver, which won't work.
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*/
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mapsize = pci_mapsize(testval);
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count = 1 << mapsize;
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count = 1UL << mapsize;
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if (RF_ALIGNMENT(flags) < mapsize)
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flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
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@ -2213,6 +2228,8 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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map = rman_get_start(res);
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out:;
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pci_write_config(child, *rid, map, 4);
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if (pci_maprange(testval) == 64)
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pci_write_config(child, *rid + 4, map >> 32, 4);
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return (res);
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}
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@ -88,6 +88,33 @@ static devclass_t pcib_devclass;
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DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
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DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
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/*
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* Is the prefetch window open (eg, can we allocate memory in it?)
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*/
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static int
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pcib_is_prefetch_open(struct pcib_softc *sc)
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{
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return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
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}
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/*
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* Is the nonprefetch window open (eg, can we allocate memory in it?)
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*/
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static int
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pcib_is_nonprefetch_open(struct pcib_softc *sc)
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{
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return (sc->membase > 0 && sc->membase < sc->memlimit);
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}
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/*
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* Is the io window open (eg, can we allocate ports in it?)
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*/
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static int
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pcib_is_io_open(struct pcib_softc *sc)
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{
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return (sc->iobase > 0 && sc->iobase < sc->iolimit);
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}
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/*
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* Generic device interface
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*/
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@ -225,8 +252,14 @@ pcib_attach_common(device_t dev)
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device_printf(dev, " secondary bus %d\n", sc->secbus);
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device_printf(dev, " subordinate bus %d\n", sc->subbus);
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device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
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device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
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device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
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if (pcib_is_nonprefetch_open(sc))
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device_printf(dev, " memory decode 0x%jx-0x%jx\n",
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(uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
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if (pcib_is_prefetch_open(sc))
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device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
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(uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
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else
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device_printf(dev, " no prefetched decode\n");
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if (sc->flags & PCIB_SUBTRACTIVE)
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device_printf(dev, " Subtractively decoded bridge.\n");
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}
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@ -288,33 +321,6 @@ pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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return(ENOENT);
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}
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/*
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* Is the prefetch window open (eg, can we allocate memory in it?)
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*/
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static int
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pcib_is_prefetch_open(struct pcib_softc *sc)
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{
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return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
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}
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/*
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* Is the nonprefetch window open (eg, can we allocate memory in it?)
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*/
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static int
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pcib_is_nonprefetch_open(struct pcib_softc *sc)
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{
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return (sc->membase > 0 && sc->membase < sc->memlimit);
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}
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/*
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* Is the io window open (eg, can we allocate ports in it?)
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*/
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static int
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pcib_is_io_open(struct pcib_softc *sc)
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{
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return (sc->iobase > 0 && sc->iobase < sc->iolimit);
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}
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/*
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* We have to trap resource allocation requests and ensure that the bridge
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* is set up to, or capable of handling them.
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@ -444,11 +450,11 @@ pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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}
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if (!ok && bootverbose)
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device_printf(dev,
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"%s requested unsupported memory range "
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"0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
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"%s requested unsupported memory range %#lx-%#lx "
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"(decoding %#jx-%#jx, %#jx-%#jx)\n",
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device_get_nameunit(child), start, end,
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sc->membase, sc->memlimit, sc->pmembase,
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sc->pmemlimit);
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(uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
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(uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
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if (!ok)
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return (NULL);
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if (bootverbose)
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@ -43,13 +43,7 @@
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#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
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#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
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/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
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#ifdef PCI_A64
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typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */
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#else
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typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */
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#endif
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typedef uint64_t pci_addr_t;
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/* Interesting values for PCI power management */
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struct pcicfg_pp {
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@ -130,14 +124,8 @@ typedef struct pcicfg {
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/* additional type 1 device config header information (PCI to PCI bridge) */
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#ifdef PCI_A64
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#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
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#else
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#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
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#endif /* PCI_A64 */
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#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
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#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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