From b0cb115fb7f022d134fed110dd4d51e08f47d8fa Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Fri, 22 Aug 2003 03:11:53 +0000 Subject: [PATCH] Prefer the uintXX_t to the u_intXX_t names. --- sys/dev/pci/pci.c | 60 ++++++++-------- sys/dev/pci/pci_pci.c | 12 ++-- sys/dev/pci/pci_private.h | 4 +- sys/dev/pci/pcib_private.h | 24 +++---- sys/dev/pci/pcivar.h | 138 ++++++++++++++++++------------------- 5 files changed, 119 insertions(+), 119 deletions(-) diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c index 0c7486e11475..aab9339c615a 100644 --- a/sys/dev/pci/pci.c +++ b/sys/dev/pci/pci.c @@ -60,7 +60,7 @@ #include "pcib_if.h" #include "pci_if.h" -static u_int32_t pci_mapbase(unsigned mapreg); +static uint32_t pci_mapbase(unsigned mapreg); static int pci_maptype(unsigned mapreg); static int pci_mapsize(unsigned testval); static int pci_maprange(unsigned mapreg); @@ -140,7 +140,7 @@ static size_t pci_vendordata_size; struct pci_quirk { - u_int32_t devid; /* Vendor/device of the card */ + uint32_t devid; /* Vendor/device of the card */ int type; #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ int arg1; @@ -163,8 +163,8 @@ struct pci_quirk pci_quirks[] = { #define PCI_MAPPORT 0x04 /* port map */ struct devlist pci_devq; -u_int32_t pci_generation; -u_int32_t pci_numdevs = 0; +uint32_t pci_generation; +uint32_t pci_numdevs = 0; /* sysctl vars */ SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); @@ -180,7 +180,7 @@ are some peripherals that this causes problems with."); /* Find a device_t by bus/slot/function */ device_t -pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) +pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) { struct pci_devinfo *dinfo; @@ -198,7 +198,7 @@ pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) /* Find a device_t by vendor/device ID */ device_t -pci_find_device(u_int16_t vendor, u_int16_t device) +pci_find_device(uint16_t vendor, uint16_t device) { struct pci_devinfo *dinfo; @@ -214,7 +214,7 @@ pci_find_device(u_int16_t vendor, u_int16_t device) /* return base address of memory or port map */ -static u_int32_t +static uint32_t pci_mapbase(unsigned mapreg) { int mask = 0x03; @@ -228,7 +228,7 @@ pci_mapbase(unsigned mapreg) static int pci_maptype(unsigned mapreg) { - static u_int8_t maptype[0x10] = { + static uint8_t maptype[0x10] = { PCI_MAPMEM, PCI_MAPPORT, PCI_MAPMEM, 0, PCI_MAPMEM, PCI_MAPPORT, @@ -474,7 +474,7 @@ pci_set_powerstate_method(device_t dev, device_t child, int state) { struct pci_devinfo *dinfo = device_get_ivars(child); pcicfgregs *cfg = &dinfo->cfg; - u_int16_t status; + uint16_t status; int result; if (cfg->pp_cap != 0) { @@ -517,7 +517,7 @@ pci_get_powerstate_method(device_t dev, device_t child) { struct pci_devinfo *dinfo = device_get_ivars(child); pcicfgregs *cfg = &dinfo->cfg; - u_int16_t status; + uint16_t status; int result; if (cfg->pp_cap != 0) { @@ -551,9 +551,9 @@ pci_get_powerstate_method(device_t dev, device_t child) */ static __inline void -pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) +pci_set_command_bit(device_t dev, device_t child, uint16_t bit) { - u_int16_t command; + uint16_t command; command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); command |= bit; @@ -561,9 +561,9 @@ pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) } static __inline void -pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) +pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) { - u_int16_t command; + uint16_t command; command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); command &= ~bit; @@ -587,8 +587,8 @@ pci_disable_busmaster_method(device_t dev, device_t child) int pci_enable_io_method(device_t dev, device_t child, int space) { - u_int16_t command; - u_int16_t bit; + uint16_t command; + uint16_t bit; char *error; bit = 0; @@ -617,8 +617,8 @@ pci_enable_io_method(device_t dev, device_t child, int space) int pci_disable_io_method(device_t dev, device_t child, int space) { - u_int16_t command; - u_int16_t bit; + uint16_t command; + uint16_t bit; char *error; bit = 0; @@ -672,7 +672,7 @@ pci_print_verbose(struct pci_devinfo *dinfo) printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); if (cfg->pp_cap) { - u_int16_t status; + uint16_t status; status = pci_read_config(cfg->dev, cfg->pp_status, 2); printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", @@ -706,12 +706,12 @@ static int pci_add_map(device_t pcib, int b, int s, int f, int reg, struct resource_list *rl) { - u_int32_t map; - u_int64_t base; - u_int8_t ln2size; - u_int8_t ln2range; - u_int32_t testval; - u_int16_t cmd; + uint32_t map; + uint64_t base; + uint8_t ln2size; + uint8_t ln2range; + uint32_t testval; + uint16_t cmd; int type; map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); @@ -732,7 +732,7 @@ pci_add_map(device_t pcib, int b, int s, int f, int reg, ln2range = pci_maprange(testval); if (ln2range == 64) { /* Read the other half of a 64bit map register */ - base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; + base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; } if (bootverbose) { @@ -826,7 +826,7 @@ pci_add_children(device_t dev, int busno, size_t dinfo_size) struct pci_devinfo *dinfo; int maxslots; int s, f, pcifunchigh; - u_int8_t hdrtype; + uint8_t hdrtype; KASSERT(dinfo_size >= sizeof(struct pci_devinfo), ("dinfo_size too small")); @@ -1176,7 +1176,7 @@ pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) * The generic accessor doesn't deal with failure, so * we set the return value, then return an error. */ - *((u_int8_t **) result) = NULL; + *((uint8_t **) result) = NULL; return (EINVAL); case PCI_IVAR_SUBVENDOR: *result = cfg->subvendor; @@ -1406,7 +1406,7 @@ pci_get_resource_list (device_t dev, device_t child) return (rl); } -u_int32_t +uint32_t pci_read_config_method(device_t dev, device_t child, int reg, int width) { struct pci_devinfo *dinfo = device_get_ivars(child); @@ -1418,7 +1418,7 @@ pci_read_config_method(device_t dev, device_t child, int reg, int width) void pci_write_config_method(device_t dev, device_t child, int reg, - u_int32_t val, int width) + uint32_t val, int width) { struct pci_devinfo *dinfo = device_get_ivars(child); pcicfgregs *cfg = &dinfo->cfg; diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c index cc113ab2c48a..29dd9526a2b0 100644 --- a/sys/dev/pci/pci_pci.c +++ b/sys/dev/pci/pci_pci.c @@ -120,7 +120,7 @@ void pcib_attach_common(device_t dev) { struct pcib_softc *sc; - u_int8_t iolow; + uint8_t iolow; sc = device_get_softc(dev); sc->dev = dev; @@ -174,7 +174,7 @@ pcib_attach_common(device_t dev) switch (pci_get_devid(dev)) { case 0x12258086: /* Intel 82454KX/GX (Orion) */ { - u_int8_t supbus; + uint8_t supbus; supbus = pci_read_config(dev, 0x41, 1); if (supbus != 0xff) { @@ -462,14 +462,14 @@ pcib_maxslots(device_t dev) /* * Since we are a child of a PCI bus, its parent must support the pcib interface. */ -u_int32_t +uint32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) { return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); } void -pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) +pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) { PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); } @@ -516,9 +516,9 @@ pcib_route_interrupt(device_t pcib, device_t dev, int pin) */ int host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, - u_int8_t *busnum) + uint8_t *busnum) { - u_int32_t id; + uint32_t id; id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); if (id == 0xffffffff) diff --git a/sys/dev/pci/pci_private.h b/sys/dev/pci/pci_private.h index fb85e6011568..3123c61cdfc7 100644 --- a/sys/dev/pci/pci_private.h +++ b/sys/dev/pci/pci_private.h @@ -50,10 +50,10 @@ int pci_write_ivar(device_t dev, device_t child, int which, int pci_set_powerstate_method(device_t dev, device_t child, int state); int pci_get_powerstate_method(device_t dev, device_t child); -u_int32_t pci_read_config_method(device_t dev, device_t child, +uint32_t pci_read_config_method(device_t dev, device_t child, int reg, int width); void pci_write_config_method(device_t dev, device_t child, - int reg, u_int32_t val, int width); + int reg, uint32_t val, int width); int pci_enable_busmaster_method(device_t dev, device_t child); int pci_disable_busmaster_method(device_t dev, device_t child); int pci_enable_io_method(device_t dev, device_t child, int space); diff --git a/sys/dev/pci/pcib_private.h b/sys/dev/pci/pcib_private.h index e897e4bc8ab3..870b306a2c38 100644 --- a/sys/dev/pci/pcib_private.h +++ b/sys/dev/pci/pcib_private.h @@ -44,24 +44,24 @@ struct pcib_softc { device_t dev; - u_int16_t command; /* command register */ - u_int8_t secbus; /* secondary bus number */ - u_int8_t subbus; /* subordinate bus number */ + uint16_t command; /* command register */ + uint8_t secbus; /* secondary bus number */ + uint8_t subbus; /* subordinate bus number */ pci_addr_t pmembase; /* base address of prefetchable memory */ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ pci_addr_t membase; /* base address of memory window */ pci_addr_t memlimit; /* topmost address of memory window */ - u_int32_t iobase; /* base address of port window */ - u_int32_t iolimit; /* topmost address of port window */ - u_int16_t secstat; /* secondary bus status register */ - u_int16_t bridgectl; /* bridge control register */ - u_int8_t seclat; /* secondary bus latency timer */ + uint32_t iobase; /* base address of port window */ + uint32_t iolimit; /* topmost address of port window */ + uint16_t secstat; /* secondary bus status register */ + uint16_t bridgectl; /* bridge control register */ + uint8_t seclat; /* secondary bus latency timer */ }; -typedef u_int32_t pci_read_config_fn(int b, int s, int f, int reg, int width); +typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width); int host_pcib_get_busno(pci_read_config_fn read_config, int bus, - int slot, int func, u_int8_t *busnum); + int slot, int func, uint8_t *busnum); int pcib_attach(device_t dev); void pcib_attach_common(device_t dev); int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); @@ -69,8 +69,8 @@ int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags); int pcib_maxslots(device_t dev); -u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); -void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width); +uint32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); +void pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width); int pcib_route_interrupt(device_t pcib, device_t dev, int pin); extern devclass_t pcib_devclass; diff --git a/sys/dev/pci/pcivar.h b/sys/dev/pci/pcivar.h index 53ad3a0355f3..de084f614d2f 100644 --- a/sys/dev/pci/pcivar.h +++ b/sys/dev/pci/pcivar.h @@ -46,9 +46,9 @@ /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ #ifdef PCI_A64 -typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ +typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */ #else -typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ +typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */ #endif /* config header information common to all header types */ @@ -56,39 +56,39 @@ typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ typedef struct pcicfg { struct device *dev; /* device which owns this */ - u_int16_t subvendor; /* card vendor ID */ - u_int16_t subdevice; /* card device ID, assigned by card vendor */ - u_int16_t vendor; /* chip vendor ID */ - u_int16_t device; /* chip device ID, assigned by chip vendor */ + uint16_t subvendor; /* card vendor ID */ + uint16_t subdevice; /* card device ID, assigned by card vendor */ + uint16_t vendor; /* chip vendor ID */ + uint16_t device; /* chip device ID, assigned by chip vendor */ - u_int16_t cmdreg; /* disable/enable chip and PCI options */ - u_int16_t statreg; /* supported PCI features and error state */ + uint16_t cmdreg; /* disable/enable chip and PCI options */ + uint16_t statreg; /* supported PCI features and error state */ - u_int8_t baseclass; /* chip PCI class */ - u_int8_t subclass; /* chip PCI subclass */ - u_int8_t progif; /* chip PCI programming interface */ - u_int8_t revid; /* chip revision ID */ + uint8_t baseclass; /* chip PCI class */ + uint8_t subclass; /* chip PCI subclass */ + uint8_t progif; /* chip PCI programming interface */ + uint8_t revid; /* chip revision ID */ - u_int8_t hdrtype; /* chip config header type */ - u_int8_t cachelnsz; /* cache line size in 4byte units */ - u_int8_t intpin; /* PCI interrupt pin */ - u_int8_t intline; /* interrupt line (IRQ for PC arch) */ + uint8_t hdrtype; /* chip config header type */ + uint8_t cachelnsz; /* cache line size in 4byte units */ + uint8_t intpin; /* PCI interrupt pin */ + uint8_t intline; /* interrupt line (IRQ for PC arch) */ - u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ - u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ - u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ + uint8_t mingnt; /* min. useful bus grant time in 250ns units */ + uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ + uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ - u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ - u_int8_t nummaps; /* actual number of PCI maps used */ + uint8_t mfdev; /* multi-function device (from hdrtype reg) */ + uint8_t nummaps; /* actual number of PCI maps used */ - u_int8_t bus; /* config space bus address */ - u_int8_t slot; /* config space slot address */ - u_int8_t func; /* config space function number */ + uint8_t bus; /* config space bus address */ + uint8_t slot; /* config space slot address */ + uint8_t func; /* config space function number */ - u_int16_t pp_cap; /* PCI power management capabilities */ - u_int8_t pp_status; /* config space address of PCI power status reg */ - u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ - u_int8_t pp_data; /* config space address of PCI power data reg */ + uint16_t pp_cap; /* PCI power management capabilities */ + uint8_t pp_status; /* config space address of PCI power status reg */ + uint8_t pp_pmcsr; /* config space address of PMCSR reg */ + uint8_t pp_data; /* config space address of PCI power data reg */ } pcicfgregs; @@ -108,33 +108,33 @@ typedef struct pcicfg { typedef struct { pci_addr_t pmembase; /* base address of prefetchable memory */ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ - u_int32_t membase; /* base address of memory window */ - u_int32_t memlimit; /* topmost address of memory window */ - u_int32_t iobase; /* base address of port window */ - u_int32_t iolimit; /* topmost address of port window */ - u_int16_t secstat; /* secondary bus status register */ - u_int16_t bridgectl; /* bridge control register */ - u_int8_t seclat; /* CardBus latency timer */ + uint32_t membase; /* base address of memory window */ + uint32_t memlimit; /* topmost address of memory window */ + uint32_t iobase; /* base address of port window */ + uint32_t iolimit; /* topmost address of port window */ + uint16_t secstat; /* secondary bus status register */ + uint16_t bridgectl; /* bridge control register */ + uint8_t seclat; /* CardBus latency timer */ } pcih1cfgregs; /* additional type 2 device config header information (CardBus bridge) */ typedef struct { - u_int32_t membase0; /* base address of memory window */ - u_int32_t memlimit0; /* topmost address of memory window */ - u_int32_t membase1; /* base address of memory window */ - u_int32_t memlimit1; /* topmost address of memory window */ - u_int32_t iobase0; /* base address of port window */ - u_int32_t iolimit0; /* topmost address of port window */ - u_int32_t iobase1; /* base address of port window */ - u_int32_t iolimit1; /* topmost address of port window */ - u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ - u_int16_t secstat; /* secondary bus status register */ - u_int16_t bridgectl; /* bridge control register */ - u_int8_t seclat; /* CardBus latency timer */ + uint32_t membase0; /* base address of memory window */ + uint32_t memlimit0; /* topmost address of memory window */ + uint32_t membase1; /* base address of memory window */ + uint32_t memlimit1; /* topmost address of memory window */ + uint32_t iobase0; /* base address of port window */ + uint32_t iolimit0; /* topmost address of port window */ + uint32_t iobase1; /* base address of port window */ + uint32_t iolimit1; /* topmost address of port window */ + uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ + uint16_t secstat; /* secondary bus status register */ + uint16_t bridgectl; /* bridge control register */ + uint8_t seclat; /* CardBus latency timer */ } pcih2cfgregs; -extern u_int32_t pci_numdevs; +extern uint32_t pci_numdevs; /* Only if the prerequisites are present */ #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) @@ -186,35 +186,35 @@ enum pci_device_ivars { #define PCI_ACCESSOR(var, ivar, type) \ __BUS_ACCESSOR(pci, var, PCI, ivar, type) -PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) -PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) -PCI_ACCESSOR(vendor, VENDOR, u_int16_t) -PCI_ACCESSOR(device, DEVICE, u_int16_t) -PCI_ACCESSOR(devid, DEVID, u_int32_t) -PCI_ACCESSOR(class, CLASS, u_int8_t) -PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) -PCI_ACCESSOR(progif, PROGIF, u_int8_t) -PCI_ACCESSOR(revid, REVID, u_int8_t) -PCI_ACCESSOR(intpin, INTPIN, u_int8_t) -PCI_ACCESSOR(irq, IRQ, u_int8_t) -PCI_ACCESSOR(bus, BUS, u_int8_t) -PCI_ACCESSOR(slot, SLOT, u_int8_t) -PCI_ACCESSOR(function, FUNCTION, u_int8_t) -PCI_ACCESSOR(ether, ETHADDR, u_int8_t *) +PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) +PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) +PCI_ACCESSOR(vendor, VENDOR, uint16_t) +PCI_ACCESSOR(device, DEVICE, uint16_t) +PCI_ACCESSOR(devid, DEVID, uint32_t) +PCI_ACCESSOR(class, CLASS, uint8_t) +PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) +PCI_ACCESSOR(progif, PROGIF, uint8_t) +PCI_ACCESSOR(revid, REVID, uint8_t) +PCI_ACCESSOR(intpin, INTPIN, uint8_t) +PCI_ACCESSOR(irq, IRQ, uint8_t) +PCI_ACCESSOR(bus, BUS, uint8_t) +PCI_ACCESSOR(slot, SLOT, uint8_t) +PCI_ACCESSOR(function, FUNCTION, uint8_t) +PCI_ACCESSOR(ether, ETHADDR, uint8_t *) #undef PCI_ACCESSOR /* * Operations on configuration space. */ -static __inline u_int32_t +static __inline uint32_t pci_read_config(device_t dev, int reg, int width) { return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); } static __inline void -pci_write_config(device_t dev, int reg, u_int32_t val, int width) +pci_write_config(device_t dev, int reg, uint32_t val, int width) { PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); } @@ -231,7 +231,7 @@ enum pcib_device_ivars { #define PCIB_ACCESSOR(var, ivar, type) \ __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) -PCIB_ACCESSOR(bus, BUS, u_int32_t) +PCIB_ACCESSOR(bus, BUS, uint32_t) #undef PCIB_ACCESSOR @@ -306,8 +306,8 @@ pci_get_powerstate(device_t dev) return PCI_GET_POWERSTATE(device_get_parent(dev), dev); } -device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); -device_t pci_find_device(u_int16_t, u_int16_t); +device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); +device_t pci_find_device(uint16_t, uint16_t); #endif /* _SYS_BUS_H_ */ /* @@ -321,6 +321,6 @@ extern struct cdevsw pcicdev; STAILQ_HEAD(devlist, pci_devinfo); extern struct devlist pci_devq; -extern u_int32_t pci_generation; +extern uint32_t pci_generation; #endif /* _PCIVAR_H_ */