bus_dmamap_sync() overhaul:
- Remove NetBSD-style or-ed together BUS_DMASYNC operations, in some cases relaxing the (intended) syncing operation a bit. - Stop pretending that that we can sync part of a dmamap: replace the GEM_CDTXSYNC and GEM_CDRXSYNC macros with GEM_CDSYNC to sync the complete control map, and combine syncs wherever possible to avoid the overhead. - Sync all maps before unloading them. - Remove a few syncs which should be unnecessary.
This commit is contained in:
Thomas Moestl
parent
d2ccea1588
commit
b2d59f4234
@ -371,6 +371,8 @@ gem_detach(sc)
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bus_dmamap_destroy(sc->sc_tdmatag,
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sc->sc_txsoft[i].txs_dmamap);
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}
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GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
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GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
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bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
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sc->sc_cddmamap);
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@ -570,6 +572,8 @@ gem_rxdrain(sc)
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for (i = 0; i < GEM_NRXDESC; i++) {
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rxs = &sc->sc_rxsoft[i];
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if (rxs->rxs_mbuf != NULL) {
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bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
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BUS_DMASYNC_POSTREAD);
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bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
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m_freem(rxs->rxs_mbuf);
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rxs->rxs_mbuf = NULL;
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@ -602,6 +606,8 @@ gem_stop(ifp, disable)
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while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
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STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
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if (txs->txs_ndescs != 0) {
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bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
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if (txs->txs_mbuf != NULL) {
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m_freem(txs->txs_mbuf);
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@ -750,8 +756,6 @@ gem_meminit(sc)
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sc->sc_txdescs[i].gd_flags = 0;
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sc->sc_txdescs[i].gd_addr = 0;
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}
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GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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sc->sc_txfree = GEM_MAXTXFREE;
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sc->sc_txnext = 0;
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sc->sc_txwin = 0;
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@ -778,6 +782,8 @@ gem_meminit(sc)
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GEM_INIT_RXDESC(sc, i);
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}
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sc->sc_rxptr = 0;
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GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
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GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
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return (0);
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}
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@ -978,10 +984,6 @@ gem_load_txmbuf(sc, m0)
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STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
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STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
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/* Sync the descriptors we're using. */
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GEM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndescs,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
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sc->sc_txfree -= txs->txs_ndescs;
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return (0);
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@ -1149,6 +1151,8 @@ gem_start(ifp)
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}
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if (ntx > 0) {
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GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
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CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
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device_get_name(sc->sc_dev), firsttx);
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@ -1197,10 +1201,8 @@ gem_tint(sc)
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* Go through our Tx list and free mbufs for those
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* frames that have been transmitted.
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*/
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GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
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while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
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GEM_CDTXSYNC(sc, txs->txs_lastdesc,
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txs->txs_ndescs,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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#ifdef GEM_DEBUG
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if (ifp->if_flags & IFF_DEBUG) {
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@ -1322,13 +1324,11 @@ gem_rint(sc)
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CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
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sc->sc_rxptr, rxcomp);
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GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
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for (i = sc->sc_rxptr; i != rxcomp;
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i = GEM_NEXTRX(i)) {
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rxs = &sc->sc_rxsoft[i];
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GEM_CDRXSYNC(sc, i,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
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if (rxstat & GEM_RD_OWN) {
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@ -1357,8 +1357,6 @@ gem_rint(sc)
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continue;
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}
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bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
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BUS_DMASYNC_POSTREAD);
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#ifdef GEM_DEBUG
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if (ifp->if_flags & IFF_DEBUG) {
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printf(" rxsoft %p descriptor %d: ", rxs, i);
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@ -1384,8 +1382,6 @@ gem_rint(sc)
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if (gem_add_rxbuf(sc, i) != 0) {
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ifp->if_ierrors++;
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GEM_INIT_RXDESC(sc, i);
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bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
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BUS_DMASYNC_PREREAD);
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continue;
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}
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m->m_data += 2; /* We're already off by two */
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@ -1398,6 +1394,7 @@ gem_rint(sc)
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}
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if (progress) {
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GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
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/* Update the receive pointer. */
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if (i == sc->sc_rxptr) {
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device_printf(sc->sc_dev, "rint: ring wrap\n");
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@ -1435,8 +1432,11 @@ gem_add_rxbuf(sc, idx)
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memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
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#endif
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if (rxs->rxs_mbuf != NULL)
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if (rxs->rxs_mbuf != NULL) {
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bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
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BUS_DMASYNC_POSTREAD);
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bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
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}
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rxs->rxs_mbuf = m;
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@ -193,12 +193,9 @@ struct gem_softc {
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#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
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#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
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#define GEM_CDTXSYNC(sc, x, n, ops) \
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#define GEM_CDSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); \
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#define GEM_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops))
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#define GEM_INIT_RXDESC(sc, x) \
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do { \
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struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
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@ -212,7 +209,6 @@ do { \
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GEM_DMA_WRITE((sc), \
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(((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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#ifdef _KERNEL
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