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Intel drives have an optimal alignment for I/O. While they honor I/Os

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that cross this boundary, they perform better when this isn't the
case. Intel uses the 3rd byte in the vendor specific area for
this. The DC P3500 was previously listed without any explanation. Add
the DC P3520 and DC P4500 to the list.

There won't be any others drives needing this quirk. Intel has
standardized a field in the namespace data in 1.3 (noiob).  A future
patch will use that if it exists, with fallback to this method.

Submitted by: Keith Busch
Reviewed by: jimharris@
This commit is contained in:
Warner Losh 2018-04-19 15:39:20 +00:00
parent 596e6ade92
commit b3e85e7a79
1 changed files with 17 additions and 3 deletions
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20
sys/dev/nvme/nvme_ns.c
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@ -505,9 +505,23 @@ nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
ns->id = id;
ns->stripesize = 0;
if (pci_get_devid(ctrlr->dev) == 0x09538086 && ctrlr->cdata.vs[3] != 0)
ns->stripesize =
(1 << ctrlr->cdata.vs[3]) * ctrlr->min_page_size;
/*
* Some Intel devices advertise an alignment that improves performance,
* but is in it's vendor specific space in the cdata. Use it for these
* drives, if present, to suggest a stripe size. Future versions of
* Intel hardware will use fields standardized in NVMe 1.3 for this.
*/
switch (pci_get_devid(ctrlr->dev)) {
case 0x09538086: /* Intel DC PC3500 */
case 0x0a538086: /* Intel DC PC3520 */
case 0x0a548086: /* Intel DC PC4500 */
if (ctrlr->cdata.vs[3] != 0)
ns->stripesize =
(1 << ctrlr->cdata.vs[3]) * ctrlr->min_page_size;
break;
default:
break;
}
/*
* Namespaces are reconstructed after a controller reset, so check