Make it possible to link together a sam and an rm kernel. The results
aren't very pretty yet, but this takes DELAY and cpu_reset and makes them pointers. # I worry that these are set too late in the boot, especially cpu_reset.
This commit is contained in:
Warner Losh
parent
7e7f083f94
commit
b44f8e5e1e
@ -201,11 +201,22 @@ const struct pmap_devmap at91_devmap[] = {
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{ 0, 0, 0, 0, 0, }
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};
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#ifdef LINUX_BOOT_ABI
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extern int membanks;
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extern int memstart[];
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extern int memsize[];
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#endif
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long
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at91_ramsize(void)
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{
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uint32_t cr, mr;
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int banks, rows, cols, bw;
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#ifdef LINUX_BOOT_ABI
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// If we found any ATAGs that were for memory, return the first bank.
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if (membanks > 0)
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return memsize[0];
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#endif
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if (at91_is_rm92()) {
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uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
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@ -593,3 +604,19 @@ cpu_initclocks(void)
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{
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}
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void
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DELAY(int n)
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{
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if (soc_data.delay)
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soc_data.delay(n);
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}
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void
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cpu_reset(void)
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{
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if (soc_data.reset)
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soc_data.reset();
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while (1)
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continue;
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}
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@ -48,6 +48,10 @@ __FBSDID("$FreeBSD$");
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91_pitreg.h>
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#ifndef PIT_PRESCALE
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#define PIT_PRESCALE (16)
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#endif
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static struct pit_softc {
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struct resource *mem_res; /* Memory resource */
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void *intrhand; /* Interrupt handle */
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@ -55,6 +59,8 @@ static struct pit_softc {
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} *sc;
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static uint32_t timecount = 0;
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static unsigned at91pit_get_timecount(struct timecounter *tc);
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static int pit_intr(void *arg);
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static inline uint32_t
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RD4(struct pit_softc *sc, bus_size_t off)
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@ -70,12 +76,28 @@ WR4(struct pit_softc *sc, bus_size_t off, uint32_t val)
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bus_write_4(sc->mem_res, off, val);
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}
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static unsigned at91pit_get_timecount(struct timecounter *tc);
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static int pit_intr(void *arg);
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static void
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at91pit_delay(int us)
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{
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int32_t cnt, last, piv;
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uint64_t pit_freq;
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const uint64_t mhz = 1E6;
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#ifndef PIT_PRESCALE
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#define PIT_PRESCALE (16)
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#endif
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last = PIT_PIV(RD4(sc, PIT_PIIR));
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/* Max delay ~= 260s. @ 133Mhz */
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pit_freq = at91_master_clock / PIT_PRESCALE;
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cnt = ((pit_freq * us) + (mhz -1)) / mhz;
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cnt = (cnt <= 0) ? 1 : cnt;
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while (cnt > 0) {
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piv = PIT_PIV(RD4(sc, PIT_PIIR));
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cnt -= piv - last ;
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if (piv < last)
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cnt -= PIT_PIV(~0u) - last;
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last = piv;
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}
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}
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static struct timecounter at91pit_timecounter = {
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at91pit_get_timecount, /* get_timecount */
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@ -90,11 +112,8 @@ static int
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at91pit_probe(device_t dev)
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{
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if (at91_is_sam9() || at91_is_sam9xe()) {
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device_set_desc(dev, "AT91SAM9 PIT");
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return (0);
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}
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return (ENXIO);
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device_set_desc(dev, "AT91SAM9 PIT");
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return (0);
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}
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static int
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@ -135,6 +154,7 @@ at91pit_attach(device_t dev)
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/* Enable the PIT here. */
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WR4(sc, PIT_MR, PIT_PIV(at91_master_clock / PIT_PRESCALE / hz) |
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PIT_EN | PIT_IEN);
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soc_data.delay = at91pit_delay;
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out:
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return (err);
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}
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@ -183,26 +203,3 @@ at91pit_get_timecount(struct timecounter *tc)
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icnt = piir >> 20; /* Overflows */
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return (timecount + PIT_PIV(piir) + PIT_PIV(RD4(sc, PIT_MR)) * icnt);
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}
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void
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DELAY(int us)
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{
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int32_t cnt, last, piv;
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uint64_t pit_freq;
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const uint64_t mhz = 1E6;
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last = PIT_PIV(RD4(sc, PIT_PIIR));
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/* Max delay ~= 260s. @ 133Mhz */
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pit_freq = at91_master_clock / PIT_PRESCALE;
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cnt = ((pit_freq * us) + (mhz -1)) / mhz;
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cnt = (cnt <= 0) ? 1 : cnt;
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while (cnt > 0) {
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piv = PIT_PIV(RD4(sc, PIT_PIIR));
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cnt -= piv - last ;
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if (piv < last)
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cnt -= PIT_PIV(~0u) - last;
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last = piv;
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}
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}
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@ -42,50 +42,70 @@ __FBSDID("$FreeBSD$");
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#define RST_TIMEOUT (5) /* Seconds to hold NRST for hard reset */
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#define RST_TICK (20) /* sample NRST at hz/RST_TICK intervals */
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static int rst_intr(void *arg);
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static int at91rst_intr(void *arg);
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static struct rst_softc {
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static struct at91rst_softc {
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struct resource *mem_res; /* Memory resource */
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struct resource *irq_res; /* IRQ resource */
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void *intrhand; /* Interrupt handle */
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struct callout tick_ch; /* Tick callout */
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device_t sc_dev;
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u_int shutdown; /* Shutdown in progress */
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} *rst_sc;
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} *at91rst_sc;
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static inline uint32_t
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RD4(struct rst_softc *sc, bus_size_t off)
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RD4(struct at91rst_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off));
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}
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static inline void
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WR4(struct rst_softc *sc, bus_size_t off, uint32_t val)
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WR4(struct at91rst_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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static int
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at91_rst_probe(device_t dev)
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void cpu_reset_sam9g20(void) __attribute__((weak));
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void cpu_reset_sam9g20(void) {}
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static void
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at91rst_cpu_reset(void)
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{
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if (at91_is_sam9() || at91_is_sam9xe()) {
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device_set_desc(dev, "AT91SAM9 Reset Controller");
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return (0);
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if (at91rst_sc) {
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cpu_reset_sam9g20(); /* May be null */
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WR4(at91rst_sc, RST_MR,
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RST_MR_ERSTL(0xd) | RST_MR_URSTEN | RST_MR_KEY);
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WR4(at91rst_sc, RST_CR,
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RST_CR_PROCRST |
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RST_CR_PERRST |
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RST_CR_EXTRST |
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RST_CR_KEY);
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}
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return (ENXIO);
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while(1)
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continue;
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}
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static int
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at91_rst_attach(device_t dev)
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at91rst_probe(device_t dev)
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{
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struct rst_softc *sc;
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device_set_desc(dev, "AT91SAM9 Reset Controller");
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return (0);
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}
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static int
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at91rst_attach(device_t dev)
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{
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struct at91rst_softc *sc;
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const char *cause;
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int rid, err;
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rst_sc = sc = device_get_softc(dev);
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at91rst_sc = sc = device_get_softc(dev);
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sc->sc_dev = dev;
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callout_init(&sc->tick_ch, 0);
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@ -109,11 +129,11 @@ at91_rst_attach(device_t dev)
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/* Activate the interrupt. */
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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rst_intr, NULL, sc, &sc->intrhand);
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at91rst_intr, NULL, sc, &sc->intrhand);
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if (err)
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device_printf(dev, "could not establish interrupt handler.\n");
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WR4(rst_sc, RST_MR, RST_MR_ERSTL(0xd) | RST_MR_URSIEN | RST_MR_KEY);
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WR4(at91rst_sc, RST_MR, RST_MR_ERSTL(0xd) | RST_MR_URSIEN | RST_MR_KEY);
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switch (RD4(sc, RST_SR) & RST_SR_RST_MASK) {
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case RST_SR_RST_POW:
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@ -137,16 +157,15 @@ at91_rst_attach(device_t dev)
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}
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device_printf(dev, "Reset cause: %s.\n", cause);
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/* cpu_reset_addr = cpu_reset; */
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soc_data.reset = at91rst_cpu_reset;
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out:
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return (err);
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}
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static void
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rst_tick(void *argp)
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at91rst_tick(void *argp)
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{
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struct rst_softc *sc = argp;
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struct at91rst_softc *sc = argp;
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if (sc->shutdown++ >= RST_TIMEOUT * RST_TICK) {
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/* User released the button in morre than RST_TIMEOUT */
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@ -157,60 +176,36 @@ rst_tick(void *argp)
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device_printf(sc->sc_dev, "shutting down...\n");
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shutdown_nice(0);
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} else {
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callout_reset(&sc->tick_ch, hz/RST_TICK, rst_tick, sc);
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callout_reset(&sc->tick_ch, hz/RST_TICK, at91rst_tick, sc);
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}
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}
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static int
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rst_intr(void *argp)
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at91rst_intr(void *argp)
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{
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struct rst_softc *sc = argp;
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struct at91rst_softc *sc = argp;
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if (RD4(sc, RST_SR) & RST_SR_URSTS) {
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if (sc->shutdown == 0)
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callout_reset(&sc->tick_ch, hz/RST_TICK, rst_tick, sc);
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callout_reset(&sc->tick_ch, hz/RST_TICK, at91rst_tick, sc);
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return (FILTER_HANDLED);
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}
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return (FILTER_STRAY);
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}
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static device_method_t at91_rst_methods[] = {
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DEVMETHOD(device_probe, at91_rst_probe),
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DEVMETHOD(device_attach, at91_rst_attach),
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static device_method_t at91rst_methods[] = {
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DEVMETHOD(device_probe, at91rst_probe),
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DEVMETHOD(device_attach, at91rst_attach),
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DEVMETHOD_END
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};
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static driver_t at91_rst_driver = {
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static driver_t at91rst_driver = {
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"at91_rst",
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at91_rst_methods,
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sizeof(struct rst_softc),
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at91rst_methods,
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sizeof(struct at91rst_softc),
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};
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static devclass_t at91_rst_devclass;
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static devclass_t at91rst_devclass;
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DRIVER_MODULE(at91_rst, atmelarm, at91_rst_driver, at91_rst_devclass, NULL,
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DRIVER_MODULE(at91_rst, atmelarm, at91rst_driver, at91rst_devclass, NULL,
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NULL);
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void cpu_reset_sam9g20(void) __attribute__((weak));
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void cpu_reset_sam9g20(void) {}
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void
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cpu_reset(void)
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{
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if (rst_sc) {
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cpu_reset_sam9g20(); /* May be null */
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WR4(rst_sc, RST_MR,
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RST_MR_ERSTL(0xd) | RST_MR_URSTEN | RST_MR_KEY);
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WR4(rst_sc, RST_CR,
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RST_CR_PROCRST |
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RST_CR_PERRST |
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RST_CR_EXTRST |
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RST_CR_KEY);
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}
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for(;;)
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;
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}
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@ -84,6 +84,40 @@ static struct timecounter at91st_timecounter = {
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1000 /* quality */
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};
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static void
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at91st_delay(int n)
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{
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uint32_t start, end, cur;
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start = st_crtr();
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n = (n * 1000) / 32768;
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if (n <= 0)
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n = 1;
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end = (start + n) & ST_CRTR_MASK;
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cur = start;
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if (start > end) {
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while (cur >= start || cur < end)
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cur = st_crtr();
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} else {
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while (cur < end)
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cur = st_crtr();
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}
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}
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static void
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at91st_cpu_reset(void)
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{
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/*
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* Reset the CPU by programmig the watchdog timer to reset the
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* CPU after 128 'slow' clocks, or about ~4ms. Loop until
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* the reset happens for safety.
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*/
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WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
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WR4(ST_CR, ST_CR_WDRST);
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while (1)
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continue;
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}
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static int
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at91st_probe(device_t dev)
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{
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@ -112,6 +146,8 @@ at91st_attach(device_t dev)
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WR4(ST_IDR, 0xffffffff);
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/* disable watchdog timer */
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WR4(ST_WDMR, 0);
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soc_data.delay = at91st_delay;
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soc_data.reset = at91st_cpu_reset; // XXX kinda late to be setting this...
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timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
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at91st_watchdog, dev, 0);
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@ -221,37 +257,3 @@ at91st_initclocks(struct at91st_softc *sc)
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WR4(ST_IER, ST_SR_PITS);
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tc_init(&at91st_timecounter);
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}
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void
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DELAY(int n)
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{
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uint32_t start, end, cur;
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start = st_crtr();
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n = (n * 1000) / 32768;
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if (n <= 0)
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n = 1;
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end = (start + n) & ST_CRTR_MASK;
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cur = start;
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if (start > end) {
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while (cur >= start || cur < end)
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cur = st_crtr();
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} else {
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while (cur < end)
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cur = st_crtr();
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}
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}
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void
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cpu_reset(void)
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{
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/*
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* Reset the CPU by programmig the watchdog timer to reset the
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* CPU after 128 'slow' clocks, or about ~4ms. Loop until
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* the reset happens for safety.
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*/
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WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
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WR4(ST_CR, ST_CR_WDRST);
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while (1)
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continue;
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}
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@ -102,6 +102,9 @@ enum at91_soc_family {
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#define AT91_SOC_NAME_MAX 50
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typedef void (*DELAY_t)(int);
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typedef void (*cpu_reset_t)(void);
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struct at91_soc_info {
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enum at91_soc_type type;
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enum at91_soc_subtype subtype;
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@ -109,6 +112,8 @@ struct at91_soc_info {
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uint32_t cidr;
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uint32_t exid;
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char name[AT91_SOC_NAME_MAX];
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DELAY_t delay;
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cpu_reset_t reset;
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};
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extern struct at91_soc_info soc_data;
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