First of several commits for driver support for the Chelsio T3B 10 Gigabit
Ethernet adapter. Reviewed by: scottl, sam For those interested in the preliminary performance work see below. Plots of mxge vs. cxgb running netpipe: blocksize vs. bandwidth: http://www.fsmware.com/chelsio.random/bsvsbw.gif blocksize vs. RTT: First of several commits for driver support for the Chelsio T3B 10 Gigabit Ethernet adapter. Reviewed by: scottl, sam For those interested in the preliminary performance work see below. Plots of mxge vs. cxgb running netpipe: blocksize vs. bandwidth: http://www.fsmware.com/chelsio.random/bsvsbw.gif blocksize vs. RTT: http://www.fsmware.com/chelsio.random/bsvstime.gif blocksize vs. RTT for block sizes <= 10kb: http://www.fsmware.com/chelsio.random/bsvstime_10kb.gif http://www.fsmware.com/chelsio.random/bsvstime_10kb3.gif
This commit is contained in:
Kip Macy
parent
dc0a8e318e
commit
b6d90eb779
328
sys/dev/cxgb/common/cxgb_ael1002.c
Normal file
328
sys/dev/cxgb/common/cxgb_ael1002.c
Normal file
@ -0,0 +1,328 @@
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/**************************************************************************
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Copyright (c) 2007, Chelsio Inc.
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All rights reserved.
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|
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Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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||||
POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <dev/cxgb/common/cxgb_common.h>
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#include <dev/cxgb/common/cxgb_regs.h>
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enum {
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AEL100X_TX_DISABLE = 9,
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AEL100X_TX_CONFIG1 = 0xc002,
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AEL1002_PWR_DOWN_HI = 0xc011,
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AEL1002_PWR_DOWN_LO = 0xc012,
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AEL1002_XFI_EQL = 0xc015,
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AEL1002_LB_EN = 0xc017,
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LASI_CTRL = 0x9002,
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LASI_STAT = 0x9005
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};
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static void ael100x_txon(struct cphy *phy)
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{
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int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
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t3_os_sleep(100);
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t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
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t3_os_sleep(30);
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}
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static int ael1002_power_down(struct cphy *phy, int enable)
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{
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int err;
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err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
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if (!err)
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err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_PDOWN, enable ? BMCR_PDOWN : 0);
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return err;
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}
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static int ael1002_reset(struct cphy *phy, int wait)
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{
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int err;
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if ((err = ael1002_power_down(phy, 0)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) ||
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(err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN,
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0, 1 << 5)))
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return err;
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return 0;
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}
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static int ael1002_intr_noop(struct cphy *phy)
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{
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return 0;
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}
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static int ael100x_get_link_status(struct cphy *phy, int *link_ok,
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int *speed, int *duplex, int *fc)
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{
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if (link_ok) {
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unsigned int status;
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int err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &status);
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/*
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* BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
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* once more to get the current link state.
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*/
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if (!err && !(status & BMSR_LSTATUS))
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR,
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&status);
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if (err)
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return err;
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*link_ok = !!(status & BMSR_LSTATUS);
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}
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if (speed)
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*speed = SPEED_10000;
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if (duplex)
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*duplex = DUPLEX_FULL;
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return 0;
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}
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#ifdef C99_NOT_SUPPORTED
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static struct cphy_ops ael1002_ops = {
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NULL,
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ael1002_reset,
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ael1002_intr_noop,
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ael1002_intr_noop,
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ael1002_intr_noop,
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ael1002_intr_noop,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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ael100x_get_link_status,
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ael1002_power_down,
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};
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#else
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static struct cphy_ops ael1002_ops = {
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.reset = ael1002_reset,
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.intr_enable = ael1002_intr_noop,
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.intr_disable = ael1002_intr_noop,
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.intr_clear = ael1002_intr_noop,
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.intr_handler = ael1002_intr_noop,
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.get_link_status = ael100x_get_link_status,
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.power_down = ael1002_power_down,
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};
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#endif
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void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops);
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ael100x_txon(phy);
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}
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static int ael1006_reset(struct cphy *phy, int wait)
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{
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return t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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}
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static int ael1006_intr_enable(struct cphy *phy)
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{
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return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1);
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}
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static int ael1006_intr_disable(struct cphy *phy)
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{
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return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0);
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}
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static int ael1006_intr_clear(struct cphy *phy)
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{
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u32 val;
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return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val);
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}
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static int ael1006_intr_handler(struct cphy *phy)
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{
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unsigned int status;
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int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status);
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if (err)
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return err;
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return (status & 1) ? cphy_cause_link_change : 0;
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}
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static int ael1006_power_down(struct cphy *phy, int enable)
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{
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return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_PDOWN, enable ? BMCR_PDOWN : 0);
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}
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#ifdef C99_NOT_SUPPORTED
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static struct cphy_ops ael1006_ops = {
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NULL,
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ael1006_reset,
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ael1006_intr_enable,
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ael1006_intr_disable,
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ael1006_intr_clear,
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ael1006_intr_handler,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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ael100x_get_link_status,
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ael1006_power_down,
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};
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#else
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static struct cphy_ops ael1006_ops = {
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.reset = ael1006_reset,
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.intr_enable = ael1006_intr_enable,
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.intr_disable = ael1006_intr_disable,
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.intr_clear = ael1006_intr_clear,
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.intr_handler = ael1006_intr_handler,
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.get_link_status = ael100x_get_link_status,
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.power_down = ael1006_power_down,
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};
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#endif
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void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops);
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ael100x_txon(phy);
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}
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#ifdef C99_NOT_SUPPORTED
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static struct cphy_ops qt2045_ops = {
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NULL,
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ael1006_reset,
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ael1006_intr_enable,
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ael1006_intr_disable,
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ael1006_intr_clear,
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ael1006_intr_handler,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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ael100x_get_link_status,
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ael1006_power_down,
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};
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#else
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static struct cphy_ops qt2045_ops = {
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.reset = ael1006_reset,
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.intr_enable = ael1006_intr_enable,
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.intr_disable = ael1006_intr_disable,
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.intr_clear = ael1006_intr_clear,
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.intr_handler = ael1006_intr_handler,
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.get_link_status = ael100x_get_link_status,
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.power_down = ael1006_power_down,
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};
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#endif
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void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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unsigned int stat;
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cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops);
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/*
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* Some cards where the PHY is supposed to be at address 0 actually
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* have it at 1.
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*/
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if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) &&
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stat == 0xffff)
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phy->addr = 1;
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}
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static int xaui_direct_reset(struct cphy *phy, int wait)
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{
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return 0;
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}
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static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
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int *speed, int *duplex, int *fc)
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{
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if (link_ok) {
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unsigned int status;
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status = t3_read_reg(phy->adapter,
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XGM_REG(A_XGM_SERDES_STAT0, phy->addr));
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*link_ok = !(status & F_LOWSIG0);
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}
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if (speed)
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*speed = SPEED_10000;
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if (duplex)
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*duplex = DUPLEX_FULL;
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return 0;
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}
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static int xaui_direct_power_down(struct cphy *phy, int enable)
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{
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return 0;
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}
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#ifdef C99_NOT_SUPPORTED
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static struct cphy_ops xaui_direct_ops = {
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NULL,
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xaui_direct_reset,
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ael1002_intr_noop,
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ael1002_intr_noop,
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ael1002_intr_noop,
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ael1002_intr_noop,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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xaui_direct_get_link_status,
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xaui_direct_power_down,
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};
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#else
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static struct cphy_ops xaui_direct_ops = {
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.reset = xaui_direct_reset,
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.intr_enable = ael1002_intr_noop,
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.intr_disable = ael1002_intr_noop,
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.intr_clear = ael1002_intr_noop,
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.intr_handler = ael1002_intr_noop,
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.get_link_status = xaui_direct_get_link_status,
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.power_down = xaui_direct_power_down,
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};
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#endif
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|
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void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, 1, &xaui_direct_ops, mdio_ops);
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}
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687
sys/dev/cxgb/common/cxgb_common.h
Normal file
687
sys/dev/cxgb/common/cxgb_common.h
Normal file
@ -0,0 +1,687 @@
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/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
#ifndef __CHELSIO_COMMON_H
|
||||
#define __CHELSIO_COMMON_H
|
||||
|
||||
#include <dev/cxgb/cxgb_osdep.h>
|
||||
|
||||
enum {
|
||||
MAX_NPORTS = 2, /* max # of ports */
|
||||
MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
|
||||
EEPROMSIZE = 8192, /* Serial EEPROM size */
|
||||
RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
|
||||
TCB_SIZE = 128, /* TCB size */
|
||||
NMTUS = 16, /* size of MTU table */
|
||||
NCCTRL_WIN = 32, /* # of congestion control windows */
|
||||
};
|
||||
|
||||
#define MAX_RX_COALESCING_LEN 16224U
|
||||
|
||||
enum {
|
||||
PAUSE_RX = 1 << 0,
|
||||
PAUSE_TX = 1 << 1,
|
||||
PAUSE_AUTONEG = 1 << 2
|
||||
};
|
||||
|
||||
enum {
|
||||
SUPPORTED_OFFLOAD = 1 << 24,
|
||||
SUPPORTED_IRQ = 1 << 25
|
||||
};
|
||||
|
||||
enum { /* adapter interrupt-maintained statistics */
|
||||
STAT_ULP_CH0_PBL_OOB,
|
||||
STAT_ULP_CH1_PBL_OOB,
|
||||
STAT_PCI_CORR_ECC,
|
||||
|
||||
IRQ_NUM_STATS /* keep last */
|
||||
};
|
||||
|
||||
enum {
|
||||
SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
|
||||
SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
|
||||
SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
|
||||
};
|
||||
|
||||
enum sge_context_type { /* SGE egress context types */
|
||||
SGE_CNTXT_RDMA = 0,
|
||||
SGE_CNTXT_ETH = 2,
|
||||
SGE_CNTXT_OFLD = 4,
|
||||
SGE_CNTXT_CTRL = 5
|
||||
};
|
||||
|
||||
enum {
|
||||
AN_PKT_SIZE = 32, /* async notification packet size */
|
||||
IMMED_PKT_SIZE = 48 /* packet size for immediate data */
|
||||
};
|
||||
|
||||
struct sg_ent { /* SGE scatter/gather entry */
|
||||
u32 len[2];
|
||||
u64 addr[2];
|
||||
};
|
||||
|
||||
#ifndef SGE_NUM_GENBITS
|
||||
/* Must be 1 or 2 */
|
||||
# define SGE_NUM_GENBITS 2
|
||||
#endif
|
||||
|
||||
#define TX_DESC_FLITS 16U
|
||||
#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
|
||||
|
||||
struct cphy;
|
||||
|
||||
struct mdio_ops {
|
||||
int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *val);
|
||||
int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val);
|
||||
};
|
||||
|
||||
struct adapter_info {
|
||||
unsigned char nports; /* # of ports */
|
||||
unsigned char phy_base_addr; /* MDIO PHY base address */
|
||||
unsigned char mdien;
|
||||
unsigned char mdiinv;
|
||||
unsigned int gpio_out; /* GPIO output settings */
|
||||
unsigned int gpio_intr; /* GPIO IRQ enable mask */
|
||||
unsigned long caps; /* adapter capabilities */
|
||||
const struct mdio_ops *mdio_ops; /* MDIO operations */
|
||||
const char *desc; /* product description */
|
||||
};
|
||||
|
||||
struct port_type_info {
|
||||
void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *ops);
|
||||
unsigned int caps;
|
||||
const char *desc;
|
||||
};
|
||||
|
||||
struct mc5_stats {
|
||||
unsigned long parity_err;
|
||||
unsigned long active_rgn_full;
|
||||
unsigned long nfa_srch_err;
|
||||
unsigned long unknown_cmd;
|
||||
unsigned long reqq_parity_err;
|
||||
unsigned long dispq_parity_err;
|
||||
unsigned long del_act_empty;
|
||||
};
|
||||
|
||||
struct mc7_stats {
|
||||
unsigned long corr_err;
|
||||
unsigned long uncorr_err;
|
||||
unsigned long parity_err;
|
||||
unsigned long addr_err;
|
||||
};
|
||||
|
||||
struct mac_stats {
|
||||
u64 tx_octets; /* total # of octets in good frames */
|
||||
u64 tx_octets_bad; /* total # of octets in error frames */
|
||||
u64 tx_frames; /* all good frames */
|
||||
u64 tx_mcast_frames; /* good multicast frames */
|
||||
u64 tx_bcast_frames; /* good broadcast frames */
|
||||
u64 tx_pause; /* # of transmitted pause frames */
|
||||
u64 tx_deferred; /* frames with deferred transmissions */
|
||||
u64 tx_late_collisions; /* # of late collisions */
|
||||
u64 tx_total_collisions; /* # of total collisions */
|
||||
u64 tx_excess_collisions; /* frame errors from excessive collissions */
|
||||
u64 tx_underrun; /* # of Tx FIFO underruns */
|
||||
u64 tx_len_errs; /* # of Tx length errors */
|
||||
u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
|
||||
u64 tx_excess_deferral; /* # of frames with excessive deferral */
|
||||
u64 tx_fcs_errs; /* # of frames with bad FCS */
|
||||
|
||||
u64 tx_frames_64; /* # of Tx frames in a particular range */
|
||||
u64 tx_frames_65_127;
|
||||
u64 tx_frames_128_255;
|
||||
u64 tx_frames_256_511;
|
||||
u64 tx_frames_512_1023;
|
||||
u64 tx_frames_1024_1518;
|
||||
u64 tx_frames_1519_max;
|
||||
|
||||
u64 rx_octets; /* total # of octets in good frames */
|
||||
u64 rx_octets_bad; /* total # of octets in error frames */
|
||||
u64 rx_frames; /* all good frames */
|
||||
u64 rx_mcast_frames; /* good multicast frames */
|
||||
u64 rx_bcast_frames; /* good broadcast frames */
|
||||
u64 rx_pause; /* # of received pause frames */
|
||||
u64 rx_fcs_errs; /* # of received frames with bad FCS */
|
||||
u64 rx_align_errs; /* alignment errors */
|
||||
u64 rx_symbol_errs; /* symbol errors */
|
||||
u64 rx_data_errs; /* data errors */
|
||||
u64 rx_sequence_errs; /* sequence errors */
|
||||
u64 rx_runt; /* # of runt frames */
|
||||
u64 rx_jabber; /* # of jabber frames */
|
||||
u64 rx_short; /* # of short frames */
|
||||
u64 rx_too_long; /* # of oversized frames */
|
||||
u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
|
||||
|
||||
u64 rx_frames_64; /* # of Rx frames in a particular range */
|
||||
u64 rx_frames_65_127;
|
||||
u64 rx_frames_128_255;
|
||||
u64 rx_frames_256_511;
|
||||
u64 rx_frames_512_1023;
|
||||
u64 rx_frames_1024_1518;
|
||||
u64 rx_frames_1519_max;
|
||||
|
||||
u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
|
||||
|
||||
unsigned long tx_fifo_parity_err;
|
||||
unsigned long rx_fifo_parity_err;
|
||||
unsigned long tx_fifo_urun;
|
||||
unsigned long rx_fifo_ovfl;
|
||||
unsigned long serdes_signal_loss;
|
||||
unsigned long xaui_pcs_ctc_err;
|
||||
unsigned long xaui_pcs_align_change;
|
||||
};
|
||||
|
||||
struct tp_mib_stats {
|
||||
u32 ipInReceive_hi;
|
||||
u32 ipInReceive_lo;
|
||||
u32 ipInHdrErrors_hi;
|
||||
u32 ipInHdrErrors_lo;
|
||||
u32 ipInAddrErrors_hi;
|
||||
u32 ipInAddrErrors_lo;
|
||||
u32 ipInUnknownProtos_hi;
|
||||
u32 ipInUnknownProtos_lo;
|
||||
u32 ipInDiscards_hi;
|
||||
u32 ipInDiscards_lo;
|
||||
u32 ipInDelivers_hi;
|
||||
u32 ipInDelivers_lo;
|
||||
u32 ipOutRequests_hi;
|
||||
u32 ipOutRequests_lo;
|
||||
u32 ipOutDiscards_hi;
|
||||
u32 ipOutDiscards_lo;
|
||||
u32 ipOutNoRoutes_hi;
|
||||
u32 ipOutNoRoutes_lo;
|
||||
u32 ipReasmTimeout;
|
||||
u32 ipReasmReqds;
|
||||
u32 ipReasmOKs;
|
||||
u32 ipReasmFails;
|
||||
|
||||
u32 reserved[8];
|
||||
|
||||
u32 tcpActiveOpens;
|
||||
u32 tcpPassiveOpens;
|
||||
u32 tcpAttemptFails;
|
||||
u32 tcpEstabResets;
|
||||
u32 tcpOutRsts;
|
||||
u32 tcpCurrEstab;
|
||||
u32 tcpInSegs_hi;
|
||||
u32 tcpInSegs_lo;
|
||||
u32 tcpOutSegs_hi;
|
||||
u32 tcpOutSegs_lo;
|
||||
u32 tcpRetransSeg_hi;
|
||||
u32 tcpRetransSeg_lo;
|
||||
u32 tcpInErrs_hi;
|
||||
u32 tcpInErrs_lo;
|
||||
u32 tcpRtoMin;
|
||||
u32 tcpRtoMax;
|
||||
};
|
||||
|
||||
struct tp_params {
|
||||
unsigned int nchan; /* # of channels */
|
||||
unsigned int pmrx_size; /* total PMRX capacity */
|
||||
unsigned int pmtx_size; /* total PMTX capacity */
|
||||
unsigned int cm_size; /* total CM capacity */
|
||||
unsigned int chan_rx_size; /* per channel Rx size */
|
||||
unsigned int chan_tx_size; /* per channel Tx size */
|
||||
unsigned int rx_pg_size; /* Rx page size */
|
||||
unsigned int tx_pg_size; /* Tx page size */
|
||||
unsigned int rx_num_pgs; /* # of Rx pages */
|
||||
unsigned int tx_num_pgs; /* # of Tx pages */
|
||||
unsigned int ntimer_qs; /* # of timer queues */
|
||||
};
|
||||
|
||||
struct qset_params { /* SGE queue set parameters */
|
||||
unsigned int polling; /* polling/interrupt service for rspq */
|
||||
unsigned int coalesce_nsecs; /* irq coalescing timer */
|
||||
unsigned int rspq_size; /* # of entries in response queue */
|
||||
unsigned int fl_size; /* # of entries in regular free list */
|
||||
unsigned int jumbo_size; /* # of entries in jumbo free list */
|
||||
unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
|
||||
unsigned int cong_thres; /* FL congestion threshold */
|
||||
};
|
||||
|
||||
struct sge_params {
|
||||
unsigned int max_pkt_size; /* max offload pkt size */
|
||||
struct qset_params qset[SGE_QSETS];
|
||||
};
|
||||
|
||||
struct mc5_params {
|
||||
unsigned int mode; /* selects MC5 width */
|
||||
unsigned int nservers; /* size of server region */
|
||||
unsigned int nfilters; /* size of filter region */
|
||||
unsigned int nroutes; /* size of routing region */
|
||||
};
|
||||
|
||||
/* Default MC5 region sizes */
|
||||
enum {
|
||||
DEFAULT_NSERVERS = 512,
|
||||
DEFAULT_NFILTERS = 128
|
||||
};
|
||||
|
||||
/* MC5 modes, these must be non-0 */
|
||||
enum {
|
||||
MC5_MODE_144_BIT = 1,
|
||||
MC5_MODE_72_BIT = 2
|
||||
};
|
||||
|
||||
struct vpd_params {
|
||||
unsigned int cclk;
|
||||
unsigned int mclk;
|
||||
unsigned int uclk;
|
||||
unsigned int mdc;
|
||||
unsigned int mem_timing;
|
||||
u8 eth_base[6];
|
||||
u8 port_type[MAX_NPORTS];
|
||||
unsigned short xauicfg[2];
|
||||
};
|
||||
|
||||
struct pci_params {
|
||||
unsigned int vpd_cap_addr;
|
||||
unsigned int pcie_cap_addr;
|
||||
unsigned short speed;
|
||||
unsigned char width;
|
||||
unsigned char variant;
|
||||
};
|
||||
|
||||
enum {
|
||||
PCI_VARIANT_PCI,
|
||||
PCI_VARIANT_PCIX_MODE1_PARITY,
|
||||
PCI_VARIANT_PCIX_MODE1_ECC,
|
||||
PCI_VARIANT_PCIX_266_MODE2,
|
||||
PCI_VARIANT_PCIE
|
||||
};
|
||||
|
||||
struct adapter_params {
|
||||
struct sge_params sge;
|
||||
struct mc5_params mc5;
|
||||
struct tp_params tp;
|
||||
struct vpd_params vpd;
|
||||
struct pci_params pci;
|
||||
|
||||
const struct adapter_info *info;
|
||||
|
||||
#ifdef CONFIG_CHELSIO_T3_CORE
|
||||
unsigned short mtus[NMTUS];
|
||||
unsigned short a_wnd[NCCTRL_WIN];
|
||||
unsigned short b_wnd[NCCTRL_WIN];
|
||||
#endif
|
||||
unsigned int nports; /* # of ethernet ports */
|
||||
unsigned int stats_update_period; /* MAC stats accumulation period */
|
||||
unsigned int linkpoll_period; /* link poll period in 0.1s */
|
||||
unsigned int rev; /* chip revision */
|
||||
};
|
||||
|
||||
struct trace_params {
|
||||
u32 sip;
|
||||
u32 sip_mask;
|
||||
u32 dip;
|
||||
u32 dip_mask;
|
||||
u16 sport;
|
||||
u16 sport_mask;
|
||||
u16 dport;
|
||||
u16 dport_mask;
|
||||
u32 vlan:12;
|
||||
u32 vlan_mask:12;
|
||||
u32 intf:4;
|
||||
u32 intf_mask:4;
|
||||
u8 proto;
|
||||
u8 proto_mask;
|
||||
};
|
||||
|
||||
struct link_config {
|
||||
unsigned int supported; /* link capabilities */
|
||||
unsigned int advertising; /* advertised capabilities */
|
||||
unsigned short requested_speed; /* speed user has requested */
|
||||
unsigned short speed; /* actual link speed */
|
||||
unsigned char requested_duplex; /* duplex user has requested */
|
||||
unsigned char duplex; /* actual link duplex */
|
||||
unsigned char requested_fc; /* flow control user has requested */
|
||||
unsigned char fc; /* actual link flow control */
|
||||
unsigned char autoneg; /* autonegotiating? */
|
||||
unsigned int link_ok; /* link up? */
|
||||
};
|
||||
|
||||
#define SPEED_INVALID 0xffff
|
||||
#define DUPLEX_INVALID 0xff
|
||||
|
||||
struct mc5 {
|
||||
adapter_t *adapter;
|
||||
unsigned int tcam_size;
|
||||
unsigned char part_type;
|
||||
unsigned char parity_enabled;
|
||||
unsigned char mode;
|
||||
struct mc5_stats stats;
|
||||
};
|
||||
|
||||
static inline unsigned int t3_mc5_size(const struct mc5 *p)
|
||||
{
|
||||
return p->tcam_size;
|
||||
}
|
||||
|
||||
struct mc7 {
|
||||
adapter_t *adapter; /* backpointer to adapter */
|
||||
unsigned int size; /* memory size in bytes */
|
||||
unsigned int width; /* MC7 interface width */
|
||||
unsigned int offset; /* register address offset for MC7 instance */
|
||||
const char *name; /* name of MC7 instance */
|
||||
struct mc7_stats stats; /* MC7 statistics */
|
||||
};
|
||||
|
||||
static inline unsigned int t3_mc7_size(const struct mc7 *p)
|
||||
{
|
||||
return p->size;
|
||||
}
|
||||
|
||||
struct cmac {
|
||||
adapter_t *adapter;
|
||||
unsigned int offset;
|
||||
unsigned int nucast; /* # of address filters for unicast MACs */
|
||||
struct mac_stats stats;
|
||||
};
|
||||
|
||||
enum {
|
||||
MAC_DIRECTION_RX = 1,
|
||||
MAC_DIRECTION_TX = 2,
|
||||
MAC_RXFIFO_SIZE = 32768
|
||||
};
|
||||
|
||||
/* IEEE 802.3ae specified MDIO devices */
|
||||
enum {
|
||||
MDIO_DEV_PMA_PMD = 1,
|
||||
MDIO_DEV_WIS = 2,
|
||||
MDIO_DEV_PCS = 3,
|
||||
MDIO_DEV_XGXS = 4
|
||||
};
|
||||
|
||||
/* PHY loopback direction */
|
||||
enum {
|
||||
PHY_LOOPBACK_TX = 1,
|
||||
PHY_LOOPBACK_RX = 2
|
||||
};
|
||||
|
||||
/* PHY interrupt types */
|
||||
enum {
|
||||
cphy_cause_link_change = 1,
|
||||
cphy_cause_fifo_error = 2
|
||||
};
|
||||
|
||||
/* PHY operations */
|
||||
struct cphy_ops {
|
||||
void (*destroy)(struct cphy *phy);
|
||||
int (*reset)(struct cphy *phy, int wait);
|
||||
|
||||
int (*intr_enable)(struct cphy *phy);
|
||||
int (*intr_disable)(struct cphy *phy);
|
||||
int (*intr_clear)(struct cphy *phy);
|
||||
int (*intr_handler)(struct cphy *phy);
|
||||
|
||||
int (*autoneg_enable)(struct cphy *phy);
|
||||
int (*autoneg_restart)(struct cphy *phy);
|
||||
|
||||
int (*advertise)(struct cphy *phy, unsigned int advertise_map);
|
||||
int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
|
||||
int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
|
||||
int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
|
||||
int *duplex, int *fc);
|
||||
int (*power_down)(struct cphy *phy, int enable);
|
||||
};
|
||||
|
||||
/* A PHY instance */
|
||||
struct cphy {
|
||||
int addr; /* PHY address */
|
||||
adapter_t *adapter; /* associated adapter */
|
||||
unsigned long fifo_errors; /* FIFO over/under-flows */
|
||||
const struct cphy_ops *ops; /* PHY operations */
|
||||
int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *val);
|
||||
int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val);
|
||||
};
|
||||
|
||||
/* Convenience MDIO read/write wrappers */
|
||||
static inline int mdio_read(struct cphy *phy, int mmd, int reg,
|
||||
unsigned int *valp)
|
||||
{
|
||||
return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
|
||||
}
|
||||
|
||||
static inline int mdio_write(struct cphy *phy, int mmd, int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
|
||||
}
|
||||
|
||||
/* Convenience initializer */
|
||||
static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
|
||||
int phy_addr, struct cphy_ops *phy_ops,
|
||||
const struct mdio_ops *mdio_ops)
|
||||
{
|
||||
phy->adapter = adapter;
|
||||
phy->addr = phy_addr;
|
||||
phy->ops = phy_ops;
|
||||
if (mdio_ops) {
|
||||
phy->mdio_read = mdio_ops->read;
|
||||
phy->mdio_write = mdio_ops->write;
|
||||
}
|
||||
}
|
||||
|
||||
/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
|
||||
#define MAC_STATS_ACCUM_SECS 180
|
||||
|
||||
#define XGM_REG(reg_addr, idx) \
|
||||
((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
|
||||
|
||||
struct addr_val_pair {
|
||||
unsigned int reg_addr;
|
||||
unsigned int val;
|
||||
};
|
||||
|
||||
#include <dev/cxgb/cxgb_adapter.h>
|
||||
|
||||
#ifndef PCI_VENDOR_ID_CHELSIO
|
||||
# define PCI_VENDOR_ID_CHELSIO 0x1425
|
||||
#endif
|
||||
|
||||
#define for_each_port(adapter, iter) \
|
||||
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
||||
|
||||
#define adapter_info(adap) ((adap)->params.info)
|
||||
|
||||
static inline int uses_xaui(const adapter_t *adap)
|
||||
{
|
||||
return adapter_info(adap)->caps & SUPPORTED_AUI;
|
||||
}
|
||||
|
||||
static inline int is_10G(const adapter_t *adap)
|
||||
{
|
||||
return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
|
||||
}
|
||||
|
||||
static inline int is_offload(const adapter_t *adap)
|
||||
{
|
||||
#ifdef CONFIG_CHELSIO_T3_CORE
|
||||
return adapter_info(adap)->caps & SUPPORTED_OFFLOAD;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
|
||||
{
|
||||
return adap->params.vpd.cclk / 1000;
|
||||
}
|
||||
|
||||
static inline unsigned int is_pcie(const adapter_t *adap)
|
||||
{
|
||||
return adap->params.pci.variant == PCI_VARIANT_PCIE;
|
||||
}
|
||||
|
||||
void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
|
||||
void t3_read_indirect(adapter_t *adap, unsigned int addr_reg,
|
||||
unsigned int data_reg, u32 *vals, unsigned int nregs,
|
||||
unsigned int start_idx);
|
||||
void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
|
||||
unsigned int offset);
|
||||
int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
|
||||
int attempts, int delay, u32 *valp);
|
||||
|
||||
static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
|
||||
int polarity, int attempts, int delay)
|
||||
{
|
||||
return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
|
||||
delay, NULL);
|
||||
}
|
||||
|
||||
int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
|
||||
unsigned int set);
|
||||
int t3_phy_reset(struct cphy *phy, int mmd, int wait);
|
||||
int t3_phy_advertise(struct cphy *phy, unsigned int advert);
|
||||
int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
|
||||
|
||||
void t3_intr_enable(adapter_t *adapter);
|
||||
void t3_intr_disable(adapter_t *adapter);
|
||||
void t3_intr_clear(adapter_t *adapter);
|
||||
void t3_port_intr_enable(adapter_t *adapter, int idx);
|
||||
void t3_port_intr_disable(adapter_t *adapter, int idx);
|
||||
void t3_port_intr_clear(adapter_t *adapter, int idx);
|
||||
int t3_slow_intr_handler(adapter_t *adapter);
|
||||
int t3_phy_intr_handler(adapter_t *adapter);
|
||||
|
||||
void t3_link_changed(adapter_t *adapter, int port_id);
|
||||
int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
|
||||
const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
|
||||
int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
|
||||
int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
|
||||
int t3_seeprom_wp(adapter_t *adapter, int enable);
|
||||
int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
|
||||
u32 *data, int byte_oriented);
|
||||
int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
|
||||
int t3_get_fw_version(adapter_t *adapter, u32 *vers);
|
||||
int t3_check_fw_version(adapter_t *adapter);
|
||||
int t3_init_hw(adapter_t *adapter, u32 fw_params);
|
||||
void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
|
||||
void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
|
||||
int t3_reset_adapter(adapter_t *adapter);
|
||||
int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
|
||||
void t3_led_ready(adapter_t *adapter);
|
||||
void t3_fatal_err(adapter_t *adapter);
|
||||
void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
|
||||
void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
|
||||
const u16 *rspq);
|
||||
int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
|
||||
int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
|
||||
void t3_port_failover(adapter_t *adapter, int port);
|
||||
void t3_failover_done(adapter_t *adapter, int port);
|
||||
void t3_failover_clear(adapter_t *adapter);
|
||||
int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
|
||||
unsigned int *valp);
|
||||
int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
|
||||
u64 *buf);
|
||||
|
||||
int t3_mac_reset(struct cmac *mac);
|
||||
void t3b_pcs_reset(struct cmac *mac);
|
||||
int t3_mac_enable(struct cmac *mac, int which);
|
||||
int t3_mac_disable(struct cmac *mac, int which);
|
||||
int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
|
||||
int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
|
||||
int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
|
||||
int t3_mac_set_num_ucast(struct cmac *mac, int n);
|
||||
const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
|
||||
int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
|
||||
int fc);
|
||||
|
||||
void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
|
||||
int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
|
||||
unsigned int nroutes);
|
||||
void t3_mc5_intr_handler(struct mc5 *mc5);
|
||||
int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
|
||||
u32 *buf);
|
||||
|
||||
#ifdef CONFIG_CHELSIO_T3_CORE
|
||||
int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
|
||||
void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
|
||||
void t3_tp_set_offload_mode(adapter_t *adap, int enable);
|
||||
void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
|
||||
void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
|
||||
unsigned short alpha[NCCTRL_WIN],
|
||||
unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
|
||||
void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
|
||||
void t3_get_cong_cntl_tab(adapter_t *adap,
|
||||
unsigned short incr[NMTUS][NCCTRL_WIN]);
|
||||
void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
|
||||
int filter_index, int invert, int enable);
|
||||
int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
|
||||
#endif
|
||||
|
||||
void t3_sge_prep(adapter_t *adap, struct sge_params *p);
|
||||
void t3_sge_init(adapter_t *adap, struct sge_params *p);
|
||||
int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
|
||||
enum sge_context_type type, int respq, u64 base_addr,
|
||||
unsigned int size, unsigned int token, int gen,
|
||||
unsigned int cidx);
|
||||
int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
|
||||
u64 base_addr, unsigned int size, unsigned int esize,
|
||||
unsigned int cong_thres, int gen, unsigned int cidx);
|
||||
int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
|
||||
u64 base_addr, unsigned int size,
|
||||
unsigned int fl_thres, int gen, unsigned int cidx);
|
||||
int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
|
||||
unsigned int size, int rspq, int ovfl_mode,
|
||||
unsigned int credits, unsigned int credit_thres);
|
||||
int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
|
||||
int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
|
||||
int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
|
||||
int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
|
||||
int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
|
||||
int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
|
||||
int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
|
||||
int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
|
||||
int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
|
||||
unsigned int credits);
|
||||
|
||||
void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
#endif /* __CHELSIO_COMMON_H */
|
||||
181
sys/dev/cxgb/common/cxgb_firmware_exports.h
Normal file
181
sys/dev/cxgb/common/cxgb_firmware_exports.h
Normal file
@ -0,0 +1,181 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
#ifndef _FIRMWARE_EXPORTS_H_
|
||||
#define _FIRMWARE_EXPORTS_H_
|
||||
|
||||
/* WR OPCODES supported by the firmware.
|
||||
*/
|
||||
#define FW_WROPCODE_FORWARD 0x01
|
||||
#define FW_WROPCODE_BYPASS 0x05
|
||||
|
||||
#define FW_WROPCODE_TUNNEL_TX_PKT 0x03
|
||||
|
||||
#define FW_WROPOCDE_ULPTX_DATA_SGL 0x00
|
||||
#define FW_WROPCODE_ULPTX_MEM_READ 0x02
|
||||
#define FW_WROPCODE_ULPTX_PKT 0x04
|
||||
#define FW_WROPCODE_ULPTX_INVALIDATE 0x06
|
||||
|
||||
#define FW_WROPCODE_TUNNEL_RX_PKT 0x07
|
||||
|
||||
#define FW_WROPCODE_OFLD_GETTCB_RPL 0x08
|
||||
#define FW_WROPCODE_OFLD_CLOSE_CON 0x09
|
||||
#define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ 0x0A
|
||||
#define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
|
||||
#define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
|
||||
#define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL 0x0C
|
||||
#define FW_WROPCODE_OFLD_TX_DATA 0x0D
|
||||
#define FW_WROPCODE_OFLD_TX_DATA_ACK 0x0E
|
||||
|
||||
#define FW_WROPCODE_RI_RDMA_INIT 0x10
|
||||
#define FW_WROPCODE_RI_RDMA_WRITE 0x11
|
||||
#define FW_WROPCODE_RI_RDMA_READ_REQ 0x12
|
||||
#define FW_WROPCODE_RI_RDMA_READ_RESP 0x13
|
||||
#define FW_WROPCODE_RI_SEND 0x14
|
||||
#define FW_WROPCODE_RI_TERMINATE 0x15
|
||||
#define FW_WROPCODE_RI_RDMA_READ 0x16
|
||||
#define FW_WROPCODE_RI_RECEIVE 0x17
|
||||
#define FW_WROPCODE_RI_BIND_MW 0x18
|
||||
#define FW_WROPCODE_RI_FASTREGISTER_MR 0x19
|
||||
#define FW_WROPCODE_RI_LOCAL_INV 0x1A
|
||||
#define FW_WROPCODE_RI_MODIFY_QP 0x1B
|
||||
#define FW_WROPCODE_RI_BYPASS 0x1C
|
||||
|
||||
#define FW_WROPOCDE_RSVD 0x1E
|
||||
|
||||
#define FW_WROPCODE_SGE_EGRESSCONTEXT_RR 0x1F
|
||||
|
||||
#define FW_WROPCODE_MNGT 0x1D
|
||||
#define FW_MNGTOPCODE_PKTSCHED_SET 0x00
|
||||
|
||||
/* Maximum size of a WR sent from the host, limited by the SGE.
|
||||
*
|
||||
* Note: WR coming from ULP or TP are only limited by CIM.
|
||||
*/
|
||||
#define FW_WR_SIZE 128
|
||||
|
||||
/* Maximum number of outstanding WRs sent from the host. Value must be
|
||||
* programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
|
||||
* offload modules to limit the number of WRs per connection.
|
||||
*/
|
||||
#define FW_T3_WR_NUM 16
|
||||
#define FW_N3_WR_NUM 7
|
||||
|
||||
#ifndef N3
|
||||
# define FW_WR_NUM FW_T3_WR_NUM
|
||||
#else
|
||||
# define FW_WR_NUM FW_N3_WR_NUM
|
||||
#endif
|
||||
|
||||
/* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
|
||||
* queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
|
||||
* start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
|
||||
*
|
||||
* Ingress Traffic (e.g. DMA completion credit) for TUNNEL Queue[i] is sent
|
||||
* to RESP Queue[i].
|
||||
*/
|
||||
#define FW_TUNNEL_NUM 8
|
||||
#define FW_TUNNEL_SGEEC_START 8
|
||||
#define FW_TUNNEL_TID_START 65544
|
||||
|
||||
|
||||
/* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
|
||||
* must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
|
||||
* (or 'uP Token') FW_CTRL_TID_START.
|
||||
*
|
||||
* Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
|
||||
*/
|
||||
#define FW_CTRL_NUM 8
|
||||
#define FW_CTRL_SGEEC_START 65528
|
||||
#define FW_CTRL_TID_START 65536
|
||||
|
||||
/* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
|
||||
* queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
|
||||
*
|
||||
* Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
|
||||
* OFFLOAD Queues, as the host is responsible for providing the correct TID in
|
||||
* every WR.
|
||||
*
|
||||
* Ingress Trafffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
|
||||
*/
|
||||
#define FW_OFLD_NUM 8
|
||||
#define FW_OFLD_SGEEC_START 0
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
#define FW_RI_NUM 1
|
||||
#define FW_RI_SGEEC_START 65527
|
||||
#define FW_RI_TID_START 65552
|
||||
|
||||
/*
|
||||
* The RX_PKT_TID
|
||||
*/
|
||||
#define FW_RX_PKT_NUM 1
|
||||
#define FW_RX_PKT_TID_START 65553
|
||||
|
||||
/* FW_WRC_NUM corresponds to the number of Work Request Context that supported
|
||||
* by the firmware.
|
||||
*/
|
||||
#define FW_WRC_NUM \
|
||||
(65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
|
||||
|
||||
/*
|
||||
* FW type and version.
|
||||
*/
|
||||
#define S_FW_VERSION_TYPE 28
|
||||
#define M_FW_VERSION_TYPE 0xF
|
||||
#define V_FW_VERSION_TYPE(x) ((x) << S_FW_VERSION_TYPE)
|
||||
#define G_FW_VERSION_TYPE(x) \
|
||||
(((x) >> S_FW_VERSION_TYPE) & M_FW_VERSION_TYPE)
|
||||
|
||||
#define S_FW_VERSION_MAJOR 16
|
||||
#define M_FW_VERSION_MAJOR 0xFFF
|
||||
#define V_FW_VERSION_MAJOR(x) ((x) << S_FW_VERSION_MAJOR)
|
||||
#define G_FW_VERSION_MAJOR(x) \
|
||||
(((x) >> S_FW_VERSION_MAJOR) & M_FW_VERSION_MAJOR)
|
||||
|
||||
#define S_FW_VERSION_MINOR 8
|
||||
#define M_FW_VERSION_MINOR 0xFF
|
||||
#define V_FW_VERSION_MINOR(x) ((x) << S_FW_VERSION_MINOR)
|
||||
#define G_FW_VERSION_MINOR(x) \
|
||||
(((x) >> S_FW_VERSION_MINOR) & M_FW_VERSION_MINOR)
|
||||
|
||||
#define S_FW_VERSION_MICRO 0
|
||||
#define M_FW_VERSION_MICRO 0xFF
|
||||
#define V_FW_VERSION_MICRO(x) ((x) << S_FW_VERSION_MICRO)
|
||||
#define G_FW_VERSION_MICRO(x) \
|
||||
(((x) >> S_FW_VERSION_MICRO) & M_FW_VERSION_MICRO)
|
||||
|
||||
#endif /* _FIRMWARE_EXPORTS_H_ */
|
||||
474
sys/dev/cxgb/common/cxgb_mc5.c
Normal file
474
sys/dev/cxgb/common/cxgb_mc5.c
Normal file
@ -0,0 +1,474 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <dev/cxgb/common/cxgb_common.h>
|
||||
#include <dev/cxgb/common/cxgb_regs.h>
|
||||
|
||||
enum {
|
||||
IDT75P52100 = 4,
|
||||
IDT75N43102 = 5
|
||||
};
|
||||
|
||||
/* DBGI command mode */
|
||||
enum {
|
||||
DBGI_MODE_MBUS = 0,
|
||||
DBGI_MODE_IDT52100 = 5
|
||||
};
|
||||
|
||||
/* IDT 75P52100 commands */
|
||||
#define IDT_CMD_READ 0
|
||||
#define IDT_CMD_WRITE 1
|
||||
#define IDT_CMD_SEARCH 2
|
||||
#define IDT_CMD_LEARN 3
|
||||
|
||||
/* IDT LAR register address and value for 144-bit mode (low 32 bits) */
|
||||
#define IDT_LAR_ADR0 0x180006
|
||||
#define IDT_LAR_MODE144 0xffff0000
|
||||
|
||||
/* IDT SCR and SSR addresses (low 32 bits) */
|
||||
#define IDT_SCR_ADR0 0x180000
|
||||
#define IDT_SSR0_ADR0 0x180002
|
||||
#define IDT_SSR1_ADR0 0x180004
|
||||
|
||||
/* IDT GMR base address (low 32 bits) */
|
||||
#define IDT_GMR_BASE_ADR0 0x180020
|
||||
|
||||
/* IDT data and mask array base addresses (low 32 bits) */
|
||||
#define IDT_DATARY_BASE_ADR0 0
|
||||
#define IDT_MSKARY_BASE_ADR0 0x80000
|
||||
|
||||
/* IDT 75N43102 commands */
|
||||
#define IDT4_CMD_SEARCH144 3
|
||||
#define IDT4_CMD_WRITE 4
|
||||
#define IDT4_CMD_READ 5
|
||||
|
||||
/* IDT 75N43102 SCR address (low 32 bits) */
|
||||
#define IDT4_SCR_ADR0 0x3
|
||||
|
||||
/* IDT 75N43102 GMR base addresses (low 32 bits) */
|
||||
#define IDT4_GMR_BASE0 0x10
|
||||
#define IDT4_GMR_BASE1 0x20
|
||||
#define IDT4_GMR_BASE2 0x30
|
||||
|
||||
/* IDT 75N43102 data and mask array base addresses (low 32 bits) */
|
||||
#define IDT4_DATARY_BASE_ADR0 0x1000000
|
||||
#define IDT4_MSKARY_BASE_ADR0 0x2000000
|
||||
|
||||
#define MAX_WRITE_ATTEMPTS 5
|
||||
|
||||
#define MAX_ROUTES 2048
|
||||
|
||||
/*
|
||||
* Issue a command to the TCAM and wait for its completion. The address and
|
||||
* any data required by the command must have been setup by the caller.
|
||||
*/
|
||||
static int mc5_cmd_write(adapter_t *adapter, u32 cmd)
|
||||
{
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd);
|
||||
return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS,
|
||||
F_DBGIRSPVALID, 1, MAX_WRITE_ATTEMPTS, 1);
|
||||
}
|
||||
|
||||
static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
|
||||
{
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1);
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2);
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3);
|
||||
}
|
||||
|
||||
static inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
|
||||
{
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1);
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2);
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3);
|
||||
}
|
||||
|
||||
static inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3)
|
||||
{
|
||||
*v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0);
|
||||
*v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1);
|
||||
*v3 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA2);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
|
||||
* command cmd. The data to be written must have been set up by the caller.
|
||||
* Returns -1 on failure, 0 on success.
|
||||
*/
|
||||
static int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd)
|
||||
{
|
||||
t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo);
|
||||
if (mc5_cmd_write(adapter, cmd) == 0)
|
||||
return 0;
|
||||
CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n", addr_lo);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base,
|
||||
u32 data_array_base, u32 write_cmd,
|
||||
int addr_shift)
|
||||
{
|
||||
unsigned int i;
|
||||
adapter_t *adap = mc5->adapter;
|
||||
|
||||
/*
|
||||
* We need the size of the TCAM data and mask arrays in terms of
|
||||
* 72-bit entries.
|
||||
*/
|
||||
unsigned int size72 = mc5->tcam_size;
|
||||
unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
|
||||
|
||||
if (mc5->mode == MC5_MODE_144_BIT) {
|
||||
size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */
|
||||
server_base *= 2;
|
||||
}
|
||||
|
||||
/* Clear the data array */
|
||||
dbgi_wr_data3(adap, 0, 0, 0);
|
||||
for (i = 0; i < size72; i++)
|
||||
if (mc5_write(adap, data_array_base + (i << addr_shift),
|
||||
write_cmd))
|
||||
return -1;
|
||||
|
||||
/* Initialize the mask array. */
|
||||
dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
|
||||
for (i = 0; i < size72; i++) {
|
||||
if (i == server_base) /* entering server or routing region */
|
||||
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0,
|
||||
mc5->mode == MC5_MODE_144_BIT ?
|
||||
0xfffffff9 : 0xfffffffd);
|
||||
if (mc5_write(adap, mask_array_base + (i << addr_shift),
|
||||
write_cmd))
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int init_idt52100(struct mc5 *mc5)
|
||||
{
|
||||
int i;
|
||||
adapter_t *adap = mc5->adapter;
|
||||
|
||||
t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
|
||||
V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15));
|
||||
t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2);
|
||||
|
||||
/*
|
||||
* Use GMRs 14-15 for ELOOKUP, GMRs 12-13 for SYN lookups, and
|
||||
* GMRs 8-9 for ACK- and AOPEN searches.
|
||||
*/
|
||||
t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE);
|
||||
t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE);
|
||||
t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH);
|
||||
t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN);
|
||||
t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);
|
||||
t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN);
|
||||
t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH);
|
||||
t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN);
|
||||
t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH);
|
||||
t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);
|
||||
t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE);
|
||||
t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ);
|
||||
|
||||
/* Set DBGI command mode for IDT TCAM. */
|
||||
t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
|
||||
|
||||
/* Set up LAR */
|
||||
dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);
|
||||
if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
/* Set up SSRs */
|
||||
dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
|
||||
if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) ||
|
||||
mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
/* Set up GMRs */
|
||||
for (i = 0; i < 32; ++i) {
|
||||
if (i >= 12 && i < 15)
|
||||
dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
|
||||
else if (i == 15)
|
||||
dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
|
||||
else
|
||||
dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
|
||||
|
||||
if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE))
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Set up SCR */
|
||||
dbgi_wr_data3(adap, 1, 0, 0);
|
||||
if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
return init_mask_data_array(mc5, IDT_MSKARY_BASE_ADR0,
|
||||
IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0);
|
||||
err:
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int init_idt43102(struct mc5 *mc5)
|
||||
{
|
||||
int i;
|
||||
adapter_t *adap = mc5->adapter;
|
||||
|
||||
t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
|
||||
adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :
|
||||
V_RDLAT(0xd) | V_SRCHLAT(0x12));
|
||||
|
||||
/*
|
||||
* Use GMRs 24-25 for ELOOKUP, GMRs 20-21 for SYN lookups, and no mask
|
||||
* for ACK- and AOPEN searches.
|
||||
*/
|
||||
t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE);
|
||||
t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE);
|
||||
t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD,
|
||||
IDT4_CMD_SEARCH144 | 0x3800);
|
||||
t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144);
|
||||
t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);
|
||||
t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);
|
||||
t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);
|
||||
t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE);
|
||||
t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ);
|
||||
|
||||
t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3);
|
||||
|
||||
/* Set DBGI command mode for IDT TCAM. */
|
||||
t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
|
||||
|
||||
/* Set up GMRs */
|
||||
dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
|
||||
for (i = 0; i < 7; ++i)
|
||||
if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
for (i = 0; i < 4; ++i)
|
||||
if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
|
||||
if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) ||
|
||||
mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) ||
|
||||
mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
|
||||
if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
/* Set up SCR */
|
||||
dbgi_wr_data3(adap, 0xf0000000, 0, 0);
|
||||
if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE))
|
||||
goto err;
|
||||
|
||||
return init_mask_data_array(mc5, IDT4_MSKARY_BASE_ADR0,
|
||||
IDT4_DATARY_BASE_ADR0, IDT4_CMD_WRITE, 1);
|
||||
err:
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Put MC5 in DBGI mode. */
|
||||
static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5)
|
||||
{
|
||||
t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
|
||||
V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_DBGIEN);
|
||||
}
|
||||
|
||||
/* Put MC5 in M-Bus mode. */
|
||||
static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
|
||||
{
|
||||
t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
|
||||
V_TMMODE(mc5->mode == MC5_MODE_72_BIT) |
|
||||
V_COMPEN(mc5->mode == MC5_MODE_72_BIT) |
|
||||
V_PRTYEN(mc5->parity_enabled) | F_MBUSEN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialization that requires the OS and protocol layers to already
|
||||
* be intialized goes here.
|
||||
*/
|
||||
int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
|
||||
unsigned int nroutes)
|
||||
{
|
||||
u32 cfg;
|
||||
int err;
|
||||
unsigned int tcam_size = mc5->tcam_size;
|
||||
adapter_t *adap = mc5->adapter;
|
||||
|
||||
if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size)
|
||||
return -EINVAL;
|
||||
|
||||
/* Reset the TCAM */
|
||||
cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
|
||||
cfg |= V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_TMRST;
|
||||
t3_write_reg(adap, A_MC5_DB_CONFIG, cfg);
|
||||
if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
|
||||
CH_ERR(adap, "TCAM reset timed out\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes);
|
||||
t3_write_reg(adap, A_MC5_DB_FILTER_TABLE,
|
||||
tcam_size - nroutes - nfilters);
|
||||
t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
|
||||
tcam_size - nroutes - nfilters - nservers);
|
||||
|
||||
mc5->parity_enabled = 1;
|
||||
|
||||
/* All the TCAM addresses we access have only the low 32 bits non 0 */
|
||||
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
|
||||
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
|
||||
|
||||
mc5_dbgi_mode_enable(mc5);
|
||||
|
||||
switch (mc5->part_type) {
|
||||
case IDT75P52100:
|
||||
err = init_idt52100(mc5);
|
||||
break;
|
||||
case IDT75N43102:
|
||||
err = init_idt43102(mc5);
|
||||
break;
|
||||
default:
|
||||
CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type);
|
||||
err = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
mc5_dbgi_mode_disable(mc5);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* read_mc5_range - dump a part of the memory managed by MC5
|
||||
* @mc5: the MC5 handle
|
||||
* @start: the start address for the dump
|
||||
* @n: number of 72-bit words to read
|
||||
* @buf: result buffer
|
||||
*
|
||||
* Read n 72-bit words from MC5 memory from the given start location.
|
||||
*/
|
||||
int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start,
|
||||
unsigned int n, u32 *buf)
|
||||
{
|
||||
u32 read_cmd;
|
||||
int err = 0;
|
||||
adapter_t *adap = mc5->adapter;
|
||||
|
||||
if (mc5->part_type == IDT75P52100)
|
||||
read_cmd = IDT_CMD_READ;
|
||||
else if (mc5->part_type == IDT75N43102)
|
||||
read_cmd = IDT4_CMD_READ;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
mc5_dbgi_mode_enable(mc5);
|
||||
|
||||
while (n--) {
|
||||
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR0, start++);
|
||||
if (mc5_cmd_write(adap, read_cmd)) {
|
||||
err = -EIO;
|
||||
break;
|
||||
}
|
||||
dbgi_rd_rsp3(adap, buf + 2, buf + 1, buf);
|
||||
buf += 3;
|
||||
}
|
||||
|
||||
mc5_dbgi_mode_disable(mc5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR)
|
||||
|
||||
/*
|
||||
* MC5 interrupt handler
|
||||
*/
|
||||
void t3_mc5_intr_handler(struct mc5 *mc5)
|
||||
{
|
||||
adapter_t *adap = mc5->adapter;
|
||||
u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
|
||||
|
||||
if ((cause & F_PARITYERR) && mc5->parity_enabled) {
|
||||
CH_ALERT(adap, "MC5 parity error\n");
|
||||
mc5->stats.parity_err++;
|
||||
}
|
||||
|
||||
if (cause & F_REQQPARERR) {
|
||||
CH_ALERT(adap, "MC5 request queue parity error\n");
|
||||
mc5->stats.reqq_parity_err++;
|
||||
}
|
||||
|
||||
if (cause & F_DISPQPARERR) {
|
||||
CH_ALERT(adap, "MC5 dispatch queue parity error\n");
|
||||
mc5->stats.dispq_parity_err++;
|
||||
}
|
||||
|
||||
if (cause & F_ACTRGNFULL)
|
||||
mc5->stats.active_rgn_full++;
|
||||
if (cause & F_NFASRCHFAIL)
|
||||
mc5->stats.nfa_srch_err++;
|
||||
if (cause & F_UNKNOWNCMD)
|
||||
mc5->stats.unknown_cmd++;
|
||||
if (cause & F_DELACTEMPTY)
|
||||
mc5->stats.del_act_empty++;
|
||||
if (cause & MC5_INT_FATAL)
|
||||
t3_fatal_err(adap);
|
||||
|
||||
t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause);
|
||||
}
|
||||
|
||||
void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode)
|
||||
{
|
||||
#define K * 1024
|
||||
|
||||
static unsigned int tcam_part_size[] = { /* in K 72-bit entries */
|
||||
64 K, 128 K, 256 K, 32 K
|
||||
};
|
||||
|
||||
#undef K
|
||||
|
||||
u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
|
||||
|
||||
mc5->adapter = adapter;
|
||||
mc5->mode = (unsigned char) mode;
|
||||
mc5->part_type = (unsigned char) G_TMTYPE(cfg);
|
||||
if (cfg & F_TMTYPEHI)
|
||||
mc5->part_type |= 4;
|
||||
|
||||
mc5->tcam_size = tcam_part_size[G_TMPARTSIZE(cfg)];
|
||||
if (mode == MC5_MODE_144_BIT)
|
||||
mc5->tcam_size /= 2;
|
||||
}
|
||||
302
sys/dev/cxgb/common/cxgb_mv88e1xxx.c
Normal file
302
sys/dev/cxgb/common/cxgb_mv88e1xxx.c
Normal file
@ -0,0 +1,302 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <dev/cxgb/common/cxgb_common.h>
|
||||
|
||||
/* Marvell PHY interrupt status bits. */
|
||||
#define MV_INTR_JABBER 0x0001
|
||||
#define MV_INTR_POLARITY_CHNG 0x0002
|
||||
#define MV_INTR_ENG_DETECT_CHNG 0x0010
|
||||
#define MV_INTR_DOWNSHIFT 0x0020
|
||||
#define MV_INTR_MDI_XOVER_CHNG 0x0040
|
||||
#define MV_INTR_FIFO_OVER_UNDER 0x0080
|
||||
#define MV_INTR_FALSE_CARRIER 0x0100
|
||||
#define MV_INTR_SYMBOL_ERROR 0x0200
|
||||
#define MV_INTR_LINK_CHNG 0x0400
|
||||
#define MV_INTR_AUTONEG_DONE 0x0800
|
||||
#define MV_INTR_PAGE_RECV 0x1000
|
||||
#define MV_INTR_DUPLEX_CHNG 0x2000
|
||||
#define MV_INTR_SPEED_CHNG 0x4000
|
||||
#define MV_INTR_AUTONEG_ERR 0x8000
|
||||
|
||||
/* Marvell PHY specific registers. */
|
||||
#define MV88E1XXX_SPECIFIC_CNTRL 16
|
||||
#define MV88E1XXX_SPECIFIC_STATUS 17
|
||||
#define MV88E1XXX_INTR_ENABLE 18
|
||||
#define MV88E1XXX_INTR_STATUS 19
|
||||
#define MV88E1XXX_EXT_SPECIFIC_CNTRL 20
|
||||
#define MV88E1XXX_RECV_ERR 21
|
||||
#define MV88E1XXX_EXT_ADDR 22
|
||||
#define MV88E1XXX_GLOBAL_STATUS 23
|
||||
#define MV88E1XXX_LED_CNTRL 24
|
||||
#define MV88E1XXX_LED_OVERRIDE 25
|
||||
#define MV88E1XXX_EXT_SPECIFIC_CNTRL2 26
|
||||
#define MV88E1XXX_EXT_SPECIFIC_STATUS 27
|
||||
#define MV88E1XXX_VIRTUAL_CABLE_TESTER 28
|
||||
#define MV88E1XXX_EXTENDED_ADDR 29
|
||||
#define MV88E1XXX_EXTENDED_DATA 30
|
||||
|
||||
/* PHY specific control register fields */
|
||||
#define S_PSCR_MDI_XOVER_MODE 5
|
||||
#define M_PSCR_MDI_XOVER_MODE 0x3
|
||||
#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
|
||||
|
||||
/* Extended PHY specific control register fields */
|
||||
#define S_DOWNSHIFT_ENABLE 8
|
||||
#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
|
||||
|
||||
#define S_DOWNSHIFT_CNT 9
|
||||
#define M_DOWNSHIFT_CNT 0x7
|
||||
#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
|
||||
|
||||
/* PHY specific status register fields */
|
||||
#define S_PSSR_JABBER 0
|
||||
#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
|
||||
|
||||
#define S_PSSR_POLARITY 1
|
||||
#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
|
||||
|
||||
#define S_PSSR_RX_PAUSE 2
|
||||
#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
|
||||
|
||||
#define S_PSSR_TX_PAUSE 3
|
||||
#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
|
||||
|
||||
#define S_PSSR_ENERGY_DETECT 4
|
||||
#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
|
||||
|
||||
#define S_PSSR_DOWNSHIFT_STATUS 5
|
||||
#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
|
||||
|
||||
#define S_PSSR_MDI 6
|
||||
#define V_PSSR_MDI (1 << S_PSSR_MDI)
|
||||
|
||||
#define S_PSSR_CABLE_LEN 7
|
||||
#define M_PSSR_CABLE_LEN 0x7
|
||||
#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
|
||||
#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
|
||||
|
||||
#define S_PSSR_LINK 10
|
||||
#define V_PSSR_LINK (1 << S_PSSR_LINK)
|
||||
|
||||
#define S_PSSR_STATUS_RESOLVED 11
|
||||
#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
|
||||
|
||||
#define S_PSSR_PAGE_RECEIVED 12
|
||||
#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
|
||||
|
||||
#define S_PSSR_DUPLEX 13
|
||||
#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
|
||||
|
||||
#define S_PSSR_SPEED 14
|
||||
#define M_PSSR_SPEED 0x3
|
||||
#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
|
||||
#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
|
||||
|
||||
/* MV88E1XXX MDI crossover register values */
|
||||
#define CROSSOVER_MDI 0
|
||||
#define CROSSOVER_MDIX 1
|
||||
#define CROSSOVER_AUTO 3
|
||||
|
||||
#define INTR_ENABLE_MASK (MV_INTR_SPEED_CHNG | MV_INTR_DUPLEX_CHNG | \
|
||||
MV_INTR_AUTONEG_DONE | MV_INTR_LINK_CHNG | MV_INTR_FIFO_OVER_UNDER | \
|
||||
MV_INTR_ENG_DETECT_CHNG)
|
||||
|
||||
/*
|
||||
* Reset the PHY. If 'wait' is set wait until the reset completes.
|
||||
*/
|
||||
static int mv88e1xxx_reset(struct cphy *cphy, int wait)
|
||||
{
|
||||
return t3_phy_reset(cphy, 0, wait);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_intr_enable(struct cphy *cphy)
|
||||
{
|
||||
return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, INTR_ENABLE_MASK);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_intr_disable(struct cphy *cphy)
|
||||
{
|
||||
return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, 0);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_intr_clear(struct cphy *cphy)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Clear PHY interrupts by reading the register. */
|
||||
return mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &val);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MV88E1XXX_SPECIFIC_CNTRL,
|
||||
V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE),
|
||||
V_PSCR_MDI_XOVER_MODE(crossover));
|
||||
}
|
||||
|
||||
static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
|
||||
{
|
||||
mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
|
||||
|
||||
/* restart autoneg for change to take effect */
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
|
||||
BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
|
||||
BMCR_ANRESTART);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_set_loopback(struct cphy *cphy, int mmd, int dir, int on)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_LOOPBACK,
|
||||
on ? BMCR_LOOPBACK : 0);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
|
||||
int *speed, int *duplex, int *fc)
|
||||
{
|
||||
u32 status;
|
||||
int sp = -1, dplx = -1, pause = 0;
|
||||
|
||||
mdio_read(cphy, 0, MV88E1XXX_SPECIFIC_STATUS, &status);
|
||||
if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
|
||||
if (status & V_PSSR_RX_PAUSE)
|
||||
pause |= PAUSE_RX;
|
||||
if (status & V_PSSR_TX_PAUSE)
|
||||
pause |= PAUSE_TX;
|
||||
dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
|
||||
sp = G_PSSR_SPEED(status);
|
||||
if (sp == 0)
|
||||
sp = SPEED_10;
|
||||
else if (sp == 1)
|
||||
sp = SPEED_100;
|
||||
else
|
||||
sp = SPEED_1000;
|
||||
}
|
||||
if (link_ok)
|
||||
*link_ok = (status & V_PSSR_LINK) != 0;
|
||||
if (speed)
|
||||
*speed = sp;
|
||||
if (duplex)
|
||||
*duplex = dplx;
|
||||
if (fc)
|
||||
*fc = pause;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
|
||||
{
|
||||
/*
|
||||
* Set the downshift counter to 2 so we try to establish Gb link
|
||||
* twice before downshifting.
|
||||
*/
|
||||
return t3_mdio_change_bits(cphy, 0, MV88E1XXX_EXT_SPECIFIC_CNTRL,
|
||||
V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT),
|
||||
downshift_enable ? V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2) : 0);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_power_down(struct cphy *cphy, int enable)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
|
||||
enable ? BMCR_PDOWN : 0);
|
||||
}
|
||||
|
||||
static int mv88e1xxx_intr_handler(struct cphy *cphy)
|
||||
{
|
||||
const u32 link_change_intrs = MV_INTR_LINK_CHNG |
|
||||
MV_INTR_AUTONEG_DONE | MV_INTR_DUPLEX_CHNG |
|
||||
MV_INTR_SPEED_CHNG | MV_INTR_DOWNSHIFT;
|
||||
|
||||
u32 cause;
|
||||
int cphy_cause = 0;
|
||||
|
||||
mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &cause);
|
||||
cause &= INTR_ENABLE_MASK;
|
||||
if (cause & link_change_intrs)
|
||||
cphy_cause |= cphy_cause_link_change;
|
||||
if (cause & MV_INTR_FIFO_OVER_UNDER)
|
||||
cphy_cause |= cphy_cause_fifo_error;
|
||||
return cphy_cause;
|
||||
}
|
||||
|
||||
#ifdef C99_NOT_SUPPORTED
|
||||
static struct cphy_ops mv88e1xxx_ops = {
|
||||
NULL,
|
||||
mv88e1xxx_reset,
|
||||
mv88e1xxx_intr_enable,
|
||||
mv88e1xxx_intr_disable,
|
||||
mv88e1xxx_intr_clear,
|
||||
mv88e1xxx_intr_handler,
|
||||
mv88e1xxx_autoneg_enable,
|
||||
mv88e1xxx_autoneg_restart,
|
||||
t3_phy_advertise,
|
||||
mv88e1xxx_set_loopback,
|
||||
t3_set_phy_speed_duplex,
|
||||
mv88e1xxx_get_link_status,
|
||||
mv88e1xxx_power_down,
|
||||
};
|
||||
#else
|
||||
static struct cphy_ops mv88e1xxx_ops = {
|
||||
.reset = mv88e1xxx_reset,
|
||||
.intr_enable = mv88e1xxx_intr_enable,
|
||||
.intr_disable = mv88e1xxx_intr_disable,
|
||||
.intr_clear = mv88e1xxx_intr_clear,
|
||||
.intr_handler = mv88e1xxx_intr_handler,
|
||||
.autoneg_enable = mv88e1xxx_autoneg_enable,
|
||||
.autoneg_restart = mv88e1xxx_autoneg_restart,
|
||||
.advertise = t3_phy_advertise,
|
||||
.set_loopback = mv88e1xxx_set_loopback,
|
||||
.set_speed_duplex = t3_set_phy_speed_duplex,
|
||||
.get_link_status = mv88e1xxx_get_link_status,
|
||||
.power_down = mv88e1xxx_power_down,
|
||||
};
|
||||
#endif
|
||||
|
||||
void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops)
|
||||
{
|
||||
cphy_init(phy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops);
|
||||
|
||||
/* Configure copper PHY transmitter as class A to reduce EMI. */
|
||||
mdio_write(phy, 0, MV88E1XXX_EXTENDED_ADDR, 0xb);
|
||||
mdio_write(phy, 0, MV88E1XXX_EXTENDED_DATA, 0x8004);
|
||||
|
||||
mv88e1xxx_downshift_set(phy, 1); /* Enable downshift */
|
||||
}
|
||||
7645
sys/dev/cxgb/common/cxgb_regs.h
Normal file
7645
sys/dev/cxgb/common/cxgb_regs.h
Normal file
File diff suppressed because it is too large
Load Diff
289
sys/dev/cxgb/common/cxgb_sge_defs.h
Normal file
289
sys/dev/cxgb/common/cxgb_sge_defs.h
Normal file
@ -0,0 +1,289 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
/*
|
||||
* This file is automatically generated --- any changes will be lost.
|
||||
*/
|
||||
|
||||
#ifndef _SGE_DEFS_H
|
||||
#define _SGE_DEFS_H
|
||||
|
||||
#define S_EC_CREDITS 0
|
||||
#define M_EC_CREDITS 0x7FFF
|
||||
#define V_EC_CREDITS(x) ((x) << S_EC_CREDITS)
|
||||
#define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS)
|
||||
|
||||
#define S_EC_GTS 15
|
||||
#define V_EC_GTS(x) ((x) << S_EC_GTS)
|
||||
#define F_EC_GTS V_EC_GTS(1U)
|
||||
|
||||
#define S_EC_INDEX 16
|
||||
#define M_EC_INDEX 0xFFFF
|
||||
#define V_EC_INDEX(x) ((x) << S_EC_INDEX)
|
||||
#define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX)
|
||||
|
||||
#define S_EC_SIZE 0
|
||||
#define M_EC_SIZE 0xFFFF
|
||||
#define V_EC_SIZE(x) ((x) << S_EC_SIZE)
|
||||
#define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE)
|
||||
|
||||
#define S_EC_BASE_LO 16
|
||||
#define M_EC_BASE_LO 0xFFFF
|
||||
#define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO)
|
||||
#define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO)
|
||||
|
||||
#define S_EC_BASE_HI 0
|
||||
#define M_EC_BASE_HI 0xF
|
||||
#define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI)
|
||||
#define G_EC_BASE_HI(x) (((x) >> S_EC_BASE_HI) & M_EC_BASE_HI)
|
||||
|
||||
#define S_EC_RESPQ 4
|
||||
#define M_EC_RESPQ 0x7
|
||||
#define V_EC_RESPQ(x) ((x) << S_EC_RESPQ)
|
||||
#define G_EC_RESPQ(x) (((x) >> S_EC_RESPQ) & M_EC_RESPQ)
|
||||
|
||||
#define S_EC_TYPE 7
|
||||
#define M_EC_TYPE 0x7
|
||||
#define V_EC_TYPE(x) ((x) << S_EC_TYPE)
|
||||
#define G_EC_TYPE(x) (((x) >> S_EC_TYPE) & M_EC_TYPE)
|
||||
|
||||
#define S_EC_GEN 10
|
||||
#define V_EC_GEN(x) ((x) << S_EC_GEN)
|
||||
#define F_EC_GEN V_EC_GEN(1U)
|
||||
|
||||
#define S_EC_UP_TOKEN 11
|
||||
#define M_EC_UP_TOKEN 0xFFFFF
|
||||
#define V_EC_UP_TOKEN(x) ((x) << S_EC_UP_TOKEN)
|
||||
#define G_EC_UP_TOKEN(x) (((x) >> S_EC_UP_TOKEN) & M_EC_UP_TOKEN)
|
||||
|
||||
#define S_EC_VALID 31
|
||||
#define V_EC_VALID(x) ((x) << S_EC_VALID)
|
||||
#define F_EC_VALID V_EC_VALID(1U)
|
||||
|
||||
#define S_RQ_MSI_VEC 20
|
||||
#define M_RQ_MSI_VEC 0x3F
|
||||
#define V_RQ_MSI_VEC(x) ((x) << S_RQ_MSI_VEC)
|
||||
#define G_RQ_MSI_VEC(x) (((x) >> S_RQ_MSI_VEC) & M_RQ_MSI_VEC)
|
||||
|
||||
#define S_RQ_INTR_EN 26
|
||||
#define V_RQ_INTR_EN(x) ((x) << S_RQ_INTR_EN)
|
||||
#define F_RQ_INTR_EN V_RQ_INTR_EN(1U)
|
||||
|
||||
#define S_RQ_GEN 28
|
||||
#define V_RQ_GEN(x) ((x) << S_RQ_GEN)
|
||||
#define F_RQ_GEN V_RQ_GEN(1U)
|
||||
|
||||
#define S_CQ_INDEX 0
|
||||
#define M_CQ_INDEX 0xFFFF
|
||||
#define V_CQ_INDEX(x) ((x) << S_CQ_INDEX)
|
||||
#define G_CQ_INDEX(x) (((x) >> S_CQ_INDEX) & M_CQ_INDEX)
|
||||
|
||||
#define S_CQ_SIZE 16
|
||||
#define M_CQ_SIZE 0xFFFF
|
||||
#define V_CQ_SIZE(x) ((x) << S_CQ_SIZE)
|
||||
#define G_CQ_SIZE(x) (((x) >> S_CQ_SIZE) & M_CQ_SIZE)
|
||||
|
||||
#define S_CQ_BASE_HI 0
|
||||
#define M_CQ_BASE_HI 0xFFFFF
|
||||
#define V_CQ_BASE_HI(x) ((x) << S_CQ_BASE_HI)
|
||||
#define G_CQ_BASE_HI(x) (((x) >> S_CQ_BASE_HI) & M_CQ_BASE_HI)
|
||||
|
||||
#define S_CQ_RSPQ 20
|
||||
#define M_CQ_RSPQ 0x3F
|
||||
#define V_CQ_RSPQ(x) ((x) << S_CQ_RSPQ)
|
||||
#define G_CQ_RSPQ(x) (((x) >> S_CQ_RSPQ) & M_CQ_RSPQ)
|
||||
|
||||
#define S_CQ_ASYNC_NOTIF 26
|
||||
#define V_CQ_ASYNC_NOTIF(x) ((x) << S_CQ_ASYNC_NOTIF)
|
||||
#define F_CQ_ASYNC_NOTIF V_CQ_ASYNC_NOTIF(1U)
|
||||
|
||||
#define S_CQ_ARMED 27
|
||||
#define V_CQ_ARMED(x) ((x) << S_CQ_ARMED)
|
||||
#define F_CQ_ARMED V_CQ_ARMED(1U)
|
||||
|
||||
#define S_CQ_ASYNC_NOTIF_SOL 28
|
||||
#define V_CQ_ASYNC_NOTIF_SOL(x) ((x) << S_CQ_ASYNC_NOTIF_SOL)
|
||||
#define F_CQ_ASYNC_NOTIF_SOL V_CQ_ASYNC_NOTIF_SOL(1U)
|
||||
|
||||
#define S_CQ_GEN 29
|
||||
#define V_CQ_GEN(x) ((x) << S_CQ_GEN)
|
||||
#define F_CQ_GEN V_CQ_GEN(1U)
|
||||
|
||||
#define S_CQ_OVERFLOW_MODE 31
|
||||
#define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE)
|
||||
#define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U)
|
||||
|
||||
#define S_CQ_CREDITS 0
|
||||
#define M_CQ_CREDITS 0xFFFF
|
||||
#define V_CQ_CREDITS(x) ((x) << S_CQ_CREDITS)
|
||||
#define G_CQ_CREDITS(x) (((x) >> S_CQ_CREDITS) & M_CQ_CREDITS)
|
||||
|
||||
#define S_CQ_CREDIT_THRES 16
|
||||
#define M_CQ_CREDIT_THRES 0x1FFF
|
||||
#define V_CQ_CREDIT_THRES(x) ((x) << S_CQ_CREDIT_THRES)
|
||||
#define G_CQ_CREDIT_THRES(x) (((x) >> S_CQ_CREDIT_THRES) & M_CQ_CREDIT_THRES)
|
||||
|
||||
#define S_FL_BASE_HI 0
|
||||
#define M_FL_BASE_HI 0xFFFFF
|
||||
#define V_FL_BASE_HI(x) ((x) << S_FL_BASE_HI)
|
||||
#define G_FL_BASE_HI(x) (((x) >> S_FL_BASE_HI) & M_FL_BASE_HI)
|
||||
|
||||
#define S_FL_INDEX_LO 20
|
||||
#define M_FL_INDEX_LO 0xFFF
|
||||
#define V_FL_INDEX_LO(x) ((x) << S_FL_INDEX_LO)
|
||||
#define G_FL_INDEX_LO(x) (((x) >> S_FL_INDEX_LO) & M_FL_INDEX_LO)
|
||||
|
||||
#define S_FL_INDEX_HI 0
|
||||
#define M_FL_INDEX_HI 0xF
|
||||
#define V_FL_INDEX_HI(x) ((x) << S_FL_INDEX_HI)
|
||||
#define G_FL_INDEX_HI(x) (((x) >> S_FL_INDEX_HI) & M_FL_INDEX_HI)
|
||||
|
||||
#define S_FL_SIZE 4
|
||||
#define M_FL_SIZE 0xFFFF
|
||||
#define V_FL_SIZE(x) ((x) << S_FL_SIZE)
|
||||
#define G_FL_SIZE(x) (((x) >> S_FL_SIZE) & M_FL_SIZE)
|
||||
|
||||
#define S_FL_GEN 20
|
||||
#define V_FL_GEN(x) ((x) << S_FL_GEN)
|
||||
#define F_FL_GEN V_FL_GEN(1U)
|
||||
|
||||
#define S_FL_ENTRY_SIZE_LO 21
|
||||
#define M_FL_ENTRY_SIZE_LO 0x7FF
|
||||
#define V_FL_ENTRY_SIZE_LO(x) ((x) << S_FL_ENTRY_SIZE_LO)
|
||||
#define G_FL_ENTRY_SIZE_LO(x) (((x) >> S_FL_ENTRY_SIZE_LO) & M_FL_ENTRY_SIZE_LO)
|
||||
|
||||
#define S_FL_ENTRY_SIZE_HI 0
|
||||
#define M_FL_ENTRY_SIZE_HI 0x1FFFFF
|
||||
#define V_FL_ENTRY_SIZE_HI(x) ((x) << S_FL_ENTRY_SIZE_HI)
|
||||
#define G_FL_ENTRY_SIZE_HI(x) (((x) >> S_FL_ENTRY_SIZE_HI) & M_FL_ENTRY_SIZE_HI)
|
||||
|
||||
#define S_FL_CONG_THRES 21
|
||||
#define M_FL_CONG_THRES 0x3FF
|
||||
#define V_FL_CONG_THRES(x) ((x) << S_FL_CONG_THRES)
|
||||
#define G_FL_CONG_THRES(x) (((x) >> S_FL_CONG_THRES) & M_FL_CONG_THRES)
|
||||
|
||||
#define S_FL_GTS 31
|
||||
#define V_FL_GTS(x) ((x) << S_FL_GTS)
|
||||
#define F_FL_GTS V_FL_GTS(1U)
|
||||
|
||||
#define S_FLD_GEN1 31
|
||||
#define V_FLD_GEN1(x) ((x) << S_FLD_GEN1)
|
||||
#define F_FLD_GEN1 V_FLD_GEN1(1U)
|
||||
|
||||
#define S_FLD_GEN2 0
|
||||
#define V_FLD_GEN2(x) ((x) << S_FLD_GEN2)
|
||||
#define F_FLD_GEN2 V_FLD_GEN2(1U)
|
||||
|
||||
#define S_RSPD_TXQ1_CR 0
|
||||
#define M_RSPD_TXQ1_CR 0x7F
|
||||
#define V_RSPD_TXQ1_CR(x) ((x) << S_RSPD_TXQ1_CR)
|
||||
#define G_RSPD_TXQ1_CR(x) (((x) >> S_RSPD_TXQ1_CR) & M_RSPD_TXQ1_CR)
|
||||
|
||||
#define S_RSPD_TXQ1_GTS 7
|
||||
#define V_RSPD_TXQ1_GTS(x) ((x) << S_RSPD_TXQ1_GTS)
|
||||
#define F_RSPD_TXQ1_GTS V_RSPD_TXQ1_GTS(1U)
|
||||
|
||||
#define S_RSPD_TXQ2_CR 8
|
||||
#define M_RSPD_TXQ2_CR 0x7F
|
||||
#define V_RSPD_TXQ2_CR(x) ((x) << S_RSPD_TXQ2_CR)
|
||||
#define G_RSPD_TXQ2_CR(x) (((x) >> S_RSPD_TXQ2_CR) & M_RSPD_TXQ2_CR)
|
||||
|
||||
#define S_RSPD_TXQ2_GTS 15
|
||||
#define V_RSPD_TXQ2_GTS(x) ((x) << S_RSPD_TXQ2_GTS)
|
||||
#define F_RSPD_TXQ2_GTS V_RSPD_TXQ2_GTS(1U)
|
||||
|
||||
#define S_RSPD_TXQ0_CR 16
|
||||
#define M_RSPD_TXQ0_CR 0x7F
|
||||
#define V_RSPD_TXQ0_CR(x) ((x) << S_RSPD_TXQ0_CR)
|
||||
#define G_RSPD_TXQ0_CR(x) (((x) >> S_RSPD_TXQ0_CR) & M_RSPD_TXQ0_CR)
|
||||
|
||||
#define S_RSPD_TXQ0_GTS 23
|
||||
#define V_RSPD_TXQ0_GTS(x) ((x) << S_RSPD_TXQ0_GTS)
|
||||
#define F_RSPD_TXQ0_GTS V_RSPD_TXQ0_GTS(1U)
|
||||
|
||||
#define S_RSPD_EOP 24
|
||||
#define V_RSPD_EOP(x) ((x) << S_RSPD_EOP)
|
||||
#define F_RSPD_EOP V_RSPD_EOP(1U)
|
||||
#define G_RSPD_EOP(x) ((x) & F_RSPD_EOP)
|
||||
|
||||
#define S_RSPD_SOP 25
|
||||
#define V_RSPD_SOP(x) ((x) << S_RSPD_SOP)
|
||||
#define F_RSPD_SOP V_RSPD_SOP(1U)
|
||||
#define G_RSPD_SOP(x) ((x) & F_RSPD_SOP)
|
||||
|
||||
#define G_RSPD_SOP_EOP(x) ((G_RSPD_SOP(x) | G_RSPD_EOP(x)) >> S_RSPD_EOP)
|
||||
|
||||
#define S_RSPD_ASYNC_NOTIF 26
|
||||
#define V_RSPD_ASYNC_NOTIF(x) ((x) << S_RSPD_ASYNC_NOTIF)
|
||||
#define F_RSPD_ASYNC_NOTIF V_RSPD_ASYNC_NOTIF(1U)
|
||||
|
||||
#define S_RSPD_FL0_GTS 27
|
||||
#define V_RSPD_FL0_GTS(x) ((x) << S_RSPD_FL0_GTS)
|
||||
#define F_RSPD_FL0_GTS V_RSPD_FL0_GTS(1U)
|
||||
|
||||
#define S_RSPD_FL1_GTS 28
|
||||
#define V_RSPD_FL1_GTS(x) ((x) << S_RSPD_FL1_GTS)
|
||||
#define F_RSPD_FL1_GTS V_RSPD_FL1_GTS(1U)
|
||||
|
||||
#define S_RSPD_IMM_DATA_VALID 29
|
||||
#define V_RSPD_IMM_DATA_VALID(x) ((x) << S_RSPD_IMM_DATA_VALID)
|
||||
#define F_RSPD_IMM_DATA_VALID V_RSPD_IMM_DATA_VALID(1U)
|
||||
|
||||
#define S_RSPD_OFFLOAD 30
|
||||
#define V_RSPD_OFFLOAD(x) ((x) << S_RSPD_OFFLOAD)
|
||||
#define F_RSPD_OFFLOAD V_RSPD_OFFLOAD(1U)
|
||||
|
||||
#define S_RSPD_GEN1 31
|
||||
#define V_RSPD_GEN1(x) ((x) << S_RSPD_GEN1)
|
||||
#define F_RSPD_GEN1 V_RSPD_GEN1(1U)
|
||||
|
||||
#define S_RSPD_LEN 0
|
||||
#define M_RSPD_LEN 0x7FFFFFFF
|
||||
#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
|
||||
#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
|
||||
|
||||
#define S_RSPD_FLQ 31
|
||||
#define V_RSPD_FLQ(x) ((x) << S_RSPD_FLQ)
|
||||
#define F_RSPD_FLQ V_RSPD_FLQ(1U)
|
||||
|
||||
#define S_RSPD_GEN2 0
|
||||
#define V_RSPD_GEN2(x) ((x) << S_RSPD_GEN2)
|
||||
#define F_RSPD_GEN2 V_RSPD_GEN2(1U)
|
||||
|
||||
#define S_RSPD_INR_VEC 1
|
||||
#define M_RSPD_INR_VEC 0x7F
|
||||
#define V_RSPD_INR_VEC(x) ((x) << S_RSPD_INR_VEC)
|
||||
#define G_RSPD_INR_VEC(x) (((x) >> S_RSPD_INR_VEC) & M_RSPD_INR_VEC)
|
||||
|
||||
#endif /* _SGE_DEFS_H */
|
||||
1490
sys/dev/cxgb/common/cxgb_t3_cpl.h
Normal file
1490
sys/dev/cxgb/common/cxgb_t3_cpl.h
Normal file
File diff suppressed because it is too large
Load Diff
3399
sys/dev/cxgb/common/cxgb_t3_hw.c
Normal file
3399
sys/dev/cxgb/common/cxgb_t3_hw.c
Normal file
File diff suppressed because it is too large
Load Diff
678
sys/dev/cxgb/common/cxgb_tcb.h
Normal file
678
sys/dev/cxgb/common/cxgb_tcb.h
Normal file
@ -0,0 +1,678 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
/* This file is automatically generated --- do not edit */
|
||||
|
||||
#ifndef _TCB_DEFS_H
|
||||
#define _TCB_DEFS_H
|
||||
|
||||
#define W_TCB_T_STATE 0
|
||||
#define S_TCB_T_STATE 0
|
||||
#define M_TCB_T_STATE 0xfULL
|
||||
#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE)
|
||||
|
||||
#define W_TCB_TIMER 0
|
||||
#define S_TCB_TIMER 4
|
||||
#define M_TCB_TIMER 0x1ULL
|
||||
#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER)
|
||||
|
||||
#define W_TCB_DACK_TIMER 0
|
||||
#define S_TCB_DACK_TIMER 5
|
||||
#define M_TCB_DACK_TIMER 0x1ULL
|
||||
#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER)
|
||||
|
||||
#define W_TCB_DEL_FLAG 0
|
||||
#define S_TCB_DEL_FLAG 6
|
||||
#define M_TCB_DEL_FLAG 0x1ULL
|
||||
#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG)
|
||||
|
||||
#define W_TCB_L2T_IX 0
|
||||
#define S_TCB_L2T_IX 7
|
||||
#define M_TCB_L2T_IX 0x7ffULL
|
||||
#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX)
|
||||
|
||||
#define W_TCB_SMAC_SEL 0
|
||||
#define S_TCB_SMAC_SEL 18
|
||||
#define M_TCB_SMAC_SEL 0x3ULL
|
||||
#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL)
|
||||
|
||||
#define W_TCB_TOS 0
|
||||
#define S_TCB_TOS 20
|
||||
#define M_TCB_TOS 0x3fULL
|
||||
#define V_TCB_TOS(x) ((x) << S_TCB_TOS)
|
||||
|
||||
#define W_TCB_MAX_RT 0
|
||||
#define S_TCB_MAX_RT 26
|
||||
#define M_TCB_MAX_RT 0xfULL
|
||||
#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT)
|
||||
|
||||
#define W_TCB_T_RXTSHIFT 0
|
||||
#define S_TCB_T_RXTSHIFT 30
|
||||
#define M_TCB_T_RXTSHIFT 0xfULL
|
||||
#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT)
|
||||
|
||||
#define W_TCB_T_DUPACKS 1
|
||||
#define S_TCB_T_DUPACKS 2
|
||||
#define M_TCB_T_DUPACKS 0xfULL
|
||||
#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS)
|
||||
|
||||
#define W_TCB_T_MAXSEG 1
|
||||
#define S_TCB_T_MAXSEG 6
|
||||
#define M_TCB_T_MAXSEG 0xfULL
|
||||
#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG)
|
||||
|
||||
#define W_TCB_T_FLAGS1 1
|
||||
#define S_TCB_T_FLAGS1 10
|
||||
#define M_TCB_T_FLAGS1 0xffffffffULL
|
||||
#define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1)
|
||||
|
||||
#define W_TCB_T_FLAGS2 2
|
||||
#define S_TCB_T_FLAGS2 10
|
||||
#define M_TCB_T_FLAGS2 0x7fULL
|
||||
#define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2)
|
||||
|
||||
#define W_TCB_SND_SCALE 2
|
||||
#define S_TCB_SND_SCALE 17
|
||||
#define M_TCB_SND_SCALE 0xfULL
|
||||
#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE)
|
||||
|
||||
#define W_TCB_RCV_SCALE 2
|
||||
#define S_TCB_RCV_SCALE 21
|
||||
#define M_TCB_RCV_SCALE 0xfULL
|
||||
#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE)
|
||||
|
||||
#define W_TCB_SND_UNA_RAW 2
|
||||
#define S_TCB_SND_UNA_RAW 25
|
||||
#define M_TCB_SND_UNA_RAW 0x7ffffffULL
|
||||
#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW)
|
||||
|
||||
#define W_TCB_SND_NXT_RAW 3
|
||||
#define S_TCB_SND_NXT_RAW 20
|
||||
#define M_TCB_SND_NXT_RAW 0x7ffffffULL
|
||||
#define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW)
|
||||
|
||||
#define W_TCB_RCV_NXT 4
|
||||
#define S_TCB_RCV_NXT 15
|
||||
#define M_TCB_RCV_NXT 0xffffffffULL
|
||||
#define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT)
|
||||
|
||||
#define W_TCB_RCV_ADV 5
|
||||
#define S_TCB_RCV_ADV 15
|
||||
#define M_TCB_RCV_ADV 0xffffULL
|
||||
#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV)
|
||||
|
||||
#define W_TCB_SND_MAX_RAW 5
|
||||
#define S_TCB_SND_MAX_RAW 31
|
||||
#define M_TCB_SND_MAX_RAW 0x7ffffffULL
|
||||
#define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW)
|
||||
|
||||
#define W_TCB_SND_CWND 6
|
||||
#define S_TCB_SND_CWND 26
|
||||
#define M_TCB_SND_CWND 0x7ffffffULL
|
||||
#define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND)
|
||||
|
||||
#define W_TCB_SND_SSTHRESH 7
|
||||
#define S_TCB_SND_SSTHRESH 21
|
||||
#define M_TCB_SND_SSTHRESH 0x7ffffffULL
|
||||
#define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH)
|
||||
|
||||
#define W_TCB_T_RTT_TS_RECENT_AGE 8
|
||||
#define S_TCB_T_RTT_TS_RECENT_AGE 16
|
||||
#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL
|
||||
#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE)
|
||||
|
||||
#define W_TCB_T_RTSEQ_RECENT 9
|
||||
#define S_TCB_T_RTSEQ_RECENT 16
|
||||
#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL
|
||||
#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT)
|
||||
|
||||
#define W_TCB_T_SRTT 10
|
||||
#define S_TCB_T_SRTT 16
|
||||
#define M_TCB_T_SRTT 0xffffULL
|
||||
#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT)
|
||||
|
||||
#define W_TCB_T_RTTVAR 11
|
||||
#define S_TCB_T_RTTVAR 0
|
||||
#define M_TCB_T_RTTVAR 0xffffULL
|
||||
#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR)
|
||||
|
||||
#define W_TCB_TS_LAST_ACK_SENT_RAW 11
|
||||
#define S_TCB_TS_LAST_ACK_SENT_RAW 16
|
||||
#define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL
|
||||
#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW)
|
||||
|
||||
#define W_TCB_DIP 12
|
||||
#define S_TCB_DIP 11
|
||||
#define M_TCB_DIP 0xffffffffULL
|
||||
#define V_TCB_DIP(x) ((x) << S_TCB_DIP)
|
||||
|
||||
#define W_TCB_SIP 13
|
||||
#define S_TCB_SIP 11
|
||||
#define M_TCB_SIP 0xffffffffULL
|
||||
#define V_TCB_SIP(x) ((x) << S_TCB_SIP)
|
||||
|
||||
#define W_TCB_DP 14
|
||||
#define S_TCB_DP 11
|
||||
#define M_TCB_DP 0xffffULL
|
||||
#define V_TCB_DP(x) ((x) << S_TCB_DP)
|
||||
|
||||
#define W_TCB_SP 14
|
||||
#define S_TCB_SP 27
|
||||
#define M_TCB_SP 0xffffULL
|
||||
#define V_TCB_SP(x) ((x) << S_TCB_SP)
|
||||
|
||||
#define W_TCB_TIMESTAMP 15
|
||||
#define S_TCB_TIMESTAMP 11
|
||||
#define M_TCB_TIMESTAMP 0xffffffffULL
|
||||
#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP)
|
||||
|
||||
#define W_TCB_TIMESTAMP_OFFSET 16
|
||||
#define S_TCB_TIMESTAMP_OFFSET 11
|
||||
#define M_TCB_TIMESTAMP_OFFSET 0xfULL
|
||||
#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET)
|
||||
|
||||
#define W_TCB_TX_MAX 16
|
||||
#define S_TCB_TX_MAX 15
|
||||
#define M_TCB_TX_MAX 0xffffffffULL
|
||||
#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX)
|
||||
|
||||
#define W_TCB_TX_HDR_PTR_RAW 17
|
||||
#define S_TCB_TX_HDR_PTR_RAW 15
|
||||
#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW)
|
||||
|
||||
#define W_TCB_TX_LAST_PTR_RAW 18
|
||||
#define S_TCB_TX_LAST_PTR_RAW 0
|
||||
#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW)
|
||||
|
||||
#define W_TCB_TX_COMPACT 18
|
||||
#define S_TCB_TX_COMPACT 17
|
||||
#define M_TCB_TX_COMPACT 0x1ULL
|
||||
#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT)
|
||||
|
||||
#define W_TCB_RX_COMPACT 18
|
||||
#define S_TCB_RX_COMPACT 18
|
||||
#define M_TCB_RX_COMPACT 0x1ULL
|
||||
#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT)
|
||||
|
||||
#define W_TCB_RCV_WND 18
|
||||
#define S_TCB_RCV_WND 19
|
||||
#define M_TCB_RCV_WND 0x7ffffffULL
|
||||
#define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND)
|
||||
|
||||
#define W_TCB_RX_HDR_OFFSET 19
|
||||
#define S_TCB_RX_HDR_OFFSET 14
|
||||
#define M_TCB_RX_HDR_OFFSET 0x7ffffffULL
|
||||
#define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET)
|
||||
|
||||
#define W_TCB_RX_FRAG0_START_IDX_RAW 20
|
||||
#define S_TCB_RX_FRAG0_START_IDX_RAW 9
|
||||
#define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG1_START_IDX_OFFSET 21
|
||||
#define S_TCB_RX_FRAG1_START_IDX_OFFSET 4
|
||||
#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
|
||||
|
||||
#define W_TCB_RX_FRAG0_LEN 21
|
||||
#define S_TCB_RX_FRAG0_LEN 31
|
||||
#define M_TCB_RX_FRAG0_LEN 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN)
|
||||
|
||||
#define W_TCB_RX_FRAG1_LEN 22
|
||||
#define S_TCB_RX_FRAG1_LEN 26
|
||||
#define M_TCB_RX_FRAG1_LEN 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN)
|
||||
|
||||
#define W_TCB_NEWRENO_RECOVER 23
|
||||
#define S_TCB_NEWRENO_RECOVER 21
|
||||
#define M_TCB_NEWRENO_RECOVER 0x7ffffffULL
|
||||
#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER)
|
||||
|
||||
#define W_TCB_PDU_HAVE_LEN 24
|
||||
#define S_TCB_PDU_HAVE_LEN 16
|
||||
#define M_TCB_PDU_HAVE_LEN 0x1ULL
|
||||
#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN)
|
||||
|
||||
#define W_TCB_PDU_LEN 24
|
||||
#define S_TCB_PDU_LEN 17
|
||||
#define M_TCB_PDU_LEN 0xffffULL
|
||||
#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN)
|
||||
|
||||
#define W_TCB_RX_QUIESCE 25
|
||||
#define S_TCB_RX_QUIESCE 1
|
||||
#define M_TCB_RX_QUIESCE 0x1ULL
|
||||
#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE)
|
||||
|
||||
#define W_TCB_RX_PTR_RAW 25
|
||||
#define S_TCB_RX_PTR_RAW 2
|
||||
#define M_TCB_RX_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW)
|
||||
|
||||
#define W_TCB_CPU_NO 25
|
||||
#define S_TCB_CPU_NO 19
|
||||
#define M_TCB_CPU_NO 0x7fULL
|
||||
#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO)
|
||||
|
||||
#define W_TCB_ULP_TYPE 25
|
||||
#define S_TCB_ULP_TYPE 26
|
||||
#define M_TCB_ULP_TYPE 0xfULL
|
||||
#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE)
|
||||
|
||||
#define W_TCB_RX_FRAG1_PTR_RAW 25
|
||||
#define S_TCB_RX_FRAG1_PTR_RAW 30
|
||||
#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26
|
||||
#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15
|
||||
#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG2_PTR_RAW 27
|
||||
#define S_TCB_RX_FRAG2_PTR_RAW 10
|
||||
#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG2_LEN_RAW 27
|
||||
#define S_TCB_RX_FRAG2_LEN_RAW 27
|
||||
#define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG3_PTR_RAW 28
|
||||
#define S_TCB_RX_FRAG3_PTR_RAW 22
|
||||
#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG3_LEN_RAW 29
|
||||
#define S_TCB_RX_FRAG3_LEN_RAW 7
|
||||
#define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW)
|
||||
|
||||
#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30
|
||||
#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2
|
||||
#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL
|
||||
#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
|
||||
|
||||
#define W_TCB_PDU_HDR_LEN 30
|
||||
#define S_TCB_PDU_HDR_LEN 29
|
||||
#define M_TCB_PDU_HDR_LEN 0xffULL
|
||||
#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN)
|
||||
|
||||
#define W_TCB_SLUSH1 31
|
||||
#define S_TCB_SLUSH1 5
|
||||
#define M_TCB_SLUSH1 0x7ffffULL
|
||||
#define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1)
|
||||
|
||||
#define W_TCB_ULP_RAW 31
|
||||
#define S_TCB_ULP_RAW 24
|
||||
#define M_TCB_ULP_RAW 0xffULL
|
||||
#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW)
|
||||
|
||||
#define W_TCB_DDP_RDMAP_VERSION 25
|
||||
#define S_TCB_DDP_RDMAP_VERSION 30
|
||||
#define M_TCB_DDP_RDMAP_VERSION 0x1ULL
|
||||
#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION)
|
||||
|
||||
#define W_TCB_MARKER_ENABLE_RX 25
|
||||
#define S_TCB_MARKER_ENABLE_RX 31
|
||||
#define M_TCB_MARKER_ENABLE_RX 0x1ULL
|
||||
#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX)
|
||||
|
||||
#define W_TCB_MARKER_ENABLE_TX 26
|
||||
#define S_TCB_MARKER_ENABLE_TX 0
|
||||
#define M_TCB_MARKER_ENABLE_TX 0x1ULL
|
||||
#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX)
|
||||
|
||||
#define W_TCB_CRC_ENABLE 26
|
||||
#define S_TCB_CRC_ENABLE 1
|
||||
#define M_TCB_CRC_ENABLE 0x1ULL
|
||||
#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE)
|
||||
|
||||
#define W_TCB_IRS_ULP 26
|
||||
#define S_TCB_IRS_ULP 2
|
||||
#define M_TCB_IRS_ULP 0x1ffULL
|
||||
#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP)
|
||||
|
||||
#define W_TCB_ISS_ULP 26
|
||||
#define S_TCB_ISS_ULP 11
|
||||
#define M_TCB_ISS_ULP 0x1ffULL
|
||||
#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP)
|
||||
|
||||
#define W_TCB_TX_PDU_LEN 26
|
||||
#define S_TCB_TX_PDU_LEN 20
|
||||
#define M_TCB_TX_PDU_LEN 0x3fffULL
|
||||
#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN)
|
||||
|
||||
#define W_TCB_TX_PDU_OUT 27
|
||||
#define S_TCB_TX_PDU_OUT 2
|
||||
#define M_TCB_TX_PDU_OUT 0x1ULL
|
||||
#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT)
|
||||
|
||||
#define W_TCB_CQ_IDX_SQ 27
|
||||
#define S_TCB_CQ_IDX_SQ 3
|
||||
#define M_TCB_CQ_IDX_SQ 0xffffULL
|
||||
#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ)
|
||||
|
||||
#define W_TCB_CQ_IDX_RQ 27
|
||||
#define S_TCB_CQ_IDX_RQ 19
|
||||
#define M_TCB_CQ_IDX_RQ 0xffffULL
|
||||
#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ)
|
||||
|
||||
#define W_TCB_QP_ID 28
|
||||
#define S_TCB_QP_ID 3
|
||||
#define M_TCB_QP_ID 0xffffULL
|
||||
#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID)
|
||||
|
||||
#define W_TCB_PD_ID 28
|
||||
#define S_TCB_PD_ID 19
|
||||
#define M_TCB_PD_ID 0xffffULL
|
||||
#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID)
|
||||
|
||||
#define W_TCB_STAG 29
|
||||
#define S_TCB_STAG 3
|
||||
#define M_TCB_STAG 0xffffffffULL
|
||||
#define V_TCB_STAG(x) ((x) << S_TCB_STAG)
|
||||
|
||||
#define W_TCB_RQ_START 30
|
||||
#define S_TCB_RQ_START 3
|
||||
#define M_TCB_RQ_START 0x3ffffffULL
|
||||
#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START)
|
||||
|
||||
#define W_TCB_RQ_MSN 30
|
||||
#define S_TCB_RQ_MSN 29
|
||||
#define M_TCB_RQ_MSN 0x3ffULL
|
||||
#define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN)
|
||||
|
||||
#define W_TCB_RQ_MAX_OFFSET 31
|
||||
#define S_TCB_RQ_MAX_OFFSET 7
|
||||
#define M_TCB_RQ_MAX_OFFSET 0xfULL
|
||||
#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET)
|
||||
|
||||
#define W_TCB_RQ_WRITE_PTR 31
|
||||
#define S_TCB_RQ_WRITE_PTR 11
|
||||
#define M_TCB_RQ_WRITE_PTR 0x3ffULL
|
||||
#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR)
|
||||
|
||||
#define W_TCB_INB_WRITE_PERM 31
|
||||
#define S_TCB_INB_WRITE_PERM 21
|
||||
#define M_TCB_INB_WRITE_PERM 0x1ULL
|
||||
#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM)
|
||||
|
||||
#define W_TCB_INB_READ_PERM 31
|
||||
#define S_TCB_INB_READ_PERM 22
|
||||
#define M_TCB_INB_READ_PERM 0x1ULL
|
||||
#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM)
|
||||
|
||||
#define W_TCB_ORD_L_BIT_VLD 31
|
||||
#define S_TCB_ORD_L_BIT_VLD 23
|
||||
#define M_TCB_ORD_L_BIT_VLD 0x1ULL
|
||||
#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD)
|
||||
|
||||
#define W_TCB_RDMAP_OPCODE 31
|
||||
#define S_TCB_RDMAP_OPCODE 24
|
||||
#define M_TCB_RDMAP_OPCODE 0xfULL
|
||||
#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE)
|
||||
|
||||
#define W_TCB_TX_FLUSH 31
|
||||
#define S_TCB_TX_FLUSH 28
|
||||
#define M_TCB_TX_FLUSH 0x1ULL
|
||||
#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH)
|
||||
|
||||
#define W_TCB_TX_OOS_RXMT 31
|
||||
#define S_TCB_TX_OOS_RXMT 29
|
||||
#define M_TCB_TX_OOS_RXMT 0x1ULL
|
||||
#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT)
|
||||
|
||||
#define W_TCB_TX_OOS_TXMT 31
|
||||
#define S_TCB_TX_OOS_TXMT 30
|
||||
#define M_TCB_TX_OOS_TXMT 0x1ULL
|
||||
#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT)
|
||||
|
||||
#define W_TCB_SLUSH_AUX2 31
|
||||
#define S_TCB_SLUSH_AUX2 31
|
||||
#define M_TCB_SLUSH_AUX2 0x1ULL
|
||||
#define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2)
|
||||
|
||||
#define W_TCB_RX_FRAG1_PTR_RAW2 25
|
||||
#define S_TCB_RX_FRAG1_PTR_RAW2 30
|
||||
#define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL
|
||||
#define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2)
|
||||
|
||||
#define W_TCB_RX_DDP_FLAGS 26
|
||||
#define S_TCB_RX_DDP_FLAGS 15
|
||||
#define M_TCB_RX_DDP_FLAGS 0xffffULL
|
||||
#define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS)
|
||||
|
||||
#define W_TCB_SLUSH_AUX3 26
|
||||
#define S_TCB_SLUSH_AUX3 31
|
||||
#define M_TCB_SLUSH_AUX3 0x1ffULL
|
||||
#define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3)
|
||||
|
||||
#define W_TCB_RX_DDP_BUF0_OFFSET 27
|
||||
#define S_TCB_RX_DDP_BUF0_OFFSET 8
|
||||
#define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL
|
||||
#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET)
|
||||
|
||||
#define W_TCB_RX_DDP_BUF0_LEN 27
|
||||
#define S_TCB_RX_DDP_BUF0_LEN 30
|
||||
#define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL
|
||||
#define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN)
|
||||
|
||||
#define W_TCB_RX_DDP_BUF1_OFFSET 28
|
||||
#define S_TCB_RX_DDP_BUF1_OFFSET 20
|
||||
#define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL
|
||||
#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET)
|
||||
|
||||
#define W_TCB_RX_DDP_BUF1_LEN 29
|
||||
#define S_TCB_RX_DDP_BUF1_LEN 10
|
||||
#define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL
|
||||
#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN)
|
||||
|
||||
#define W_TCB_RX_DDP_BUF0_TAG 30
|
||||
#define S_TCB_RX_DDP_BUF0_TAG 0
|
||||
#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL
|
||||
#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG)
|
||||
|
||||
#define W_TCB_RX_DDP_BUF1_TAG 31
|
||||
#define S_TCB_RX_DDP_BUF1_TAG 0
|
||||
#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL
|
||||
#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG)
|
||||
|
||||
#define S_TF_DACK 10
|
||||
#define V_TF_DACK(x) ((x) << S_TF_DACK)
|
||||
|
||||
#define S_TF_NAGLE 11
|
||||
#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE)
|
||||
|
||||
#define S_TF_RECV_SCALE 12
|
||||
#define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE)
|
||||
|
||||
#define S_TF_RECV_TSTMP 13
|
||||
#define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP)
|
||||
|
||||
#define S_TF_RECV_SACK 14
|
||||
#define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK)
|
||||
|
||||
#define S_TF_TURBO 15
|
||||
#define V_TF_TURBO(x) ((x) << S_TF_TURBO)
|
||||
|
||||
#define S_TF_KEEPALIVE 16
|
||||
#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE)
|
||||
|
||||
#define S_TF_TCAM_BYPASS 17
|
||||
#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS)
|
||||
|
||||
#define S_TF_CORE_FIN 18
|
||||
#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN)
|
||||
|
||||
#define S_TF_CORE_MORE 19
|
||||
#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE)
|
||||
|
||||
#define S_TF_MIGRATING 20
|
||||
#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING)
|
||||
|
||||
#define S_TF_ACTIVE_OPEN 21
|
||||
#define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN)
|
||||
|
||||
#define S_TF_ASK_MODE 22
|
||||
#define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE)
|
||||
|
||||
#define S_TF_NON_OFFLOAD 23
|
||||
#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD)
|
||||
|
||||
#define S_TF_MOD_SCHD 24
|
||||
#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD)
|
||||
|
||||
#define S_TF_MOD_SCHD_REASON0 25
|
||||
#define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0)
|
||||
|
||||
#define S_TF_MOD_SCHD_REASON1 26
|
||||
#define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1)
|
||||
|
||||
#define S_TF_MOD_SCHD_RX 27
|
||||
#define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX)
|
||||
|
||||
#define S_TF_CORE_PUSH 28
|
||||
#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH)
|
||||
|
||||
#define S_TF_RCV_COALESCE_ENABLE 29
|
||||
#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE)
|
||||
|
||||
#define S_TF_RCV_COALESCE_PUSH 30
|
||||
#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH)
|
||||
|
||||
#define S_TF_RCV_COALESCE_LAST_PSH 31
|
||||
#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH)
|
||||
|
||||
#define S_TF_RCV_COALESCE_HEARTBEAT 32
|
||||
#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT)
|
||||
|
||||
#define S_TF_LOCK_TID 33
|
||||
#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID)
|
||||
|
||||
#define S_TF_DACK_MSS 34
|
||||
#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS)
|
||||
|
||||
#define S_TF_CCTRL_SEL0 35
|
||||
#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0)
|
||||
|
||||
#define S_TF_CCTRL_SEL1 36
|
||||
#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1)
|
||||
|
||||
#define S_TF_TCP_NEWRENO_FAST_RECOVERY 37
|
||||
#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY)
|
||||
|
||||
#define S_TF_TX_PACE_AUTO 38
|
||||
#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO)
|
||||
|
||||
#define S_TF_PEER_FIN_HELD 39
|
||||
#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD)
|
||||
|
||||
#define S_TF_CORE_URG 40
|
||||
#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG)
|
||||
|
||||
#define S_TF_RDMA_ERROR 41
|
||||
#define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR)
|
||||
|
||||
#define S_TF_SSWS_DISABLED 42
|
||||
#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED)
|
||||
|
||||
#define S_TF_DUPACK_COUNT_ODD 43
|
||||
#define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD)
|
||||
|
||||
#define S_TF_TX_CHANNEL 44
|
||||
#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL)
|
||||
|
||||
#define S_TF_RX_CHANNEL 45
|
||||
#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL)
|
||||
|
||||
#define S_TF_TX_PACE_FIXED 46
|
||||
#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED)
|
||||
|
||||
#define S_TF_RDMA_FLM_ERROR 47
|
||||
#define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR)
|
||||
|
||||
#define S_TF_RX_FLOW_CONTROL_DISABLE 48
|
||||
#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE)
|
||||
|
||||
#define S_TF_DDP_INDICATE_OUT 15
|
||||
#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT)
|
||||
|
||||
#define S_TF_DDP_ACTIVE_BUF 16
|
||||
#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF)
|
||||
|
||||
#define S_TF_DDP_BUF0_VALID 17
|
||||
#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID)
|
||||
|
||||
#define S_TF_DDP_BUF1_VALID 18
|
||||
#define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID)
|
||||
|
||||
#define S_TF_DDP_BUF0_INDICATE 19
|
||||
#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE)
|
||||
|
||||
#define S_TF_DDP_BUF1_INDICATE 20
|
||||
#define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE)
|
||||
|
||||
#define S_TF_DDP_PUSH_DISABLE_0 21
|
||||
#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0)
|
||||
|
||||
#define S_TF_DDP_PUSH_DISABLE_1 22
|
||||
#define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1)
|
||||
|
||||
#define S_TF_DDP_OFF 23
|
||||
#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF)
|
||||
|
||||
#define S_TF_DDP_WAIT_FRAG 24
|
||||
#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG)
|
||||
|
||||
#define S_TF_DDP_BUF_INF 25
|
||||
#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF)
|
||||
|
||||
#define S_TF_DDP_RX2TX 26
|
||||
#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX)
|
||||
|
||||
#define S_TF_DDP_BUF0_FLUSH 27
|
||||
#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH)
|
||||
|
||||
#define S_TF_DDP_BUF1_FLUSH 28
|
||||
#define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH)
|
||||
|
||||
#define S_TF_DDP_PSH_NO_INVALIDATE 29
|
||||
#define V_TF_DDP_PSH_NO_INVALIDATE(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE)
|
||||
|
||||
#endif /* _TCB_DEFS_H */
|
||||
41
sys/dev/cxgb/common/cxgb_version.h
Normal file
41
sys/dev/cxgb/common/cxgb_version.h
Normal file
@ -0,0 +1,41 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __CHELSIO_VERSION_H
|
||||
#define __CHELSIO_VERSION_H
|
||||
#define DRV_DESC "Chelsio T3 Network Driver"
|
||||
#define DRV_NAME "cxgb"
|
||||
#define DRV_VERSION "1.0"
|
||||
#endif
|
||||
251
sys/dev/cxgb/common/cxgb_vsc8211.c
Normal file
251
sys/dev/cxgb/common/cxgb_vsc8211.c
Normal file
@ -0,0 +1,251 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <dev/cxgb/common/cxgb_common.h>
|
||||
|
||||
/* VSC8211 PHY specific registers. */
|
||||
enum {
|
||||
VSC8211_INTR_ENABLE = 25,
|
||||
VSC8211_INTR_STATUS = 26,
|
||||
VSC8211_AUX_CTRL_STAT = 28,
|
||||
};
|
||||
|
||||
enum {
|
||||
VSC_INTR_RX_ERR = 1 << 0,
|
||||
VSC_INTR_MS_ERR = 1 << 1, /* master/slave resolution error */
|
||||
VSC_INTR_CABLE = 1 << 2, /* cable impairment */
|
||||
VSC_INTR_FALSE_CARR = 1 << 3, /* false carrier */
|
||||
VSC_INTR_MEDIA_CHG = 1 << 4, /* AMS media change */
|
||||
VSC_INTR_RX_FIFO = 1 << 5, /* Rx FIFO over/underflow */
|
||||
VSC_INTR_TX_FIFO = 1 << 6, /* Tx FIFO over/underflow */
|
||||
VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
|
||||
VSC_INTR_SYMBOL_ERR = 1 << 8, /* symbol error */
|
||||
VSC_INTR_NEG_DONE = 1 << 10, /* autoneg done */
|
||||
VSC_INTR_NEG_ERR = 1 << 11, /* autoneg error */
|
||||
VSC_INTR_LINK_CHG = 1 << 13, /* link change */
|
||||
VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */
|
||||
};
|
||||
|
||||
#define CFG_CHG_INTR_MASK (VSC_INTR_LINK_CHG | VSC_INTR_NEG_ERR | \
|
||||
VSC_INTR_NEG_DONE)
|
||||
#define INTR_MASK (CFG_CHG_INTR_MASK | VSC_INTR_TX_FIFO | VSC_INTR_RX_FIFO | \
|
||||
VSC_INTR_ENABLE)
|
||||
|
||||
/* PHY specific auxiliary control & status register fields */
|
||||
#define S_ACSR_ACTIPHY_TMR 0
|
||||
#define M_ACSR_ACTIPHY_TMR 0x3
|
||||
#define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR)
|
||||
|
||||
#define S_ACSR_SPEED 3
|
||||
#define M_ACSR_SPEED 0x3
|
||||
#define G_ACSR_SPEED(x) (((x) >> S_ACSR_SPEED) & M_ACSR_SPEED)
|
||||
|
||||
#define S_ACSR_DUPLEX 5
|
||||
#define F_ACSR_DUPLEX (1 << S_ACSR_DUPLEX)
|
||||
|
||||
#define S_ACSR_ACTIPHY 6
|
||||
#define F_ACSR_ACTIPHY (1 << S_ACSR_ACTIPHY)
|
||||
|
||||
/*
|
||||
* Reset the PHY. This PHY completes reset immediately so we never wait.
|
||||
*/
|
||||
static int vsc8211_reset(struct cphy *cphy, int wait)
|
||||
{
|
||||
return t3_phy_reset(cphy, 0, 0);
|
||||
}
|
||||
|
||||
static int vsc8211_intr_enable(struct cphy *cphy)
|
||||
{
|
||||
return mdio_write(cphy, 0, VSC8211_INTR_ENABLE, INTR_MASK);
|
||||
}
|
||||
|
||||
static int vsc8211_intr_disable(struct cphy *cphy)
|
||||
{
|
||||
return mdio_write(cphy, 0, VSC8211_INTR_ENABLE, 0);
|
||||
}
|
||||
|
||||
static int vsc8211_intr_clear(struct cphy *cphy)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Clear PHY interrupts by reading the register. */
|
||||
return mdio_read(cphy, 0, VSC8211_INTR_STATUS, &val);
|
||||
}
|
||||
|
||||
static int vsc8211_autoneg_enable(struct cphy *cphy)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
|
||||
BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
}
|
||||
|
||||
static int vsc8211_autoneg_restart(struct cphy *cphy)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
|
||||
BMCR_ANRESTART);
|
||||
}
|
||||
|
||||
static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok,
|
||||
int *speed, int *duplex, int *fc)
|
||||
{
|
||||
unsigned int bmcr, status, lpa, adv;
|
||||
int err, sp = -1, dplx = -1, pause = 0;
|
||||
|
||||
err = mdio_read(cphy, 0, MII_BMCR, &bmcr);
|
||||
if (!err)
|
||||
err = mdio_read(cphy, 0, MII_BMSR, &status);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (link_ok) {
|
||||
/*
|
||||
* BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
|
||||
* once more to get the current link state.
|
||||
*/
|
||||
if (!(status & BMSR_LSTATUS))
|
||||
err = mdio_read(cphy, 0, MII_BMSR, &status);
|
||||
if (err)
|
||||
return err;
|
||||
*link_ok = (status & BMSR_LSTATUS) != 0;
|
||||
}
|
||||
if (!(bmcr & BMCR_ANENABLE)) {
|
||||
dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
|
||||
if (bmcr & BMCR_SPEED1000)
|
||||
sp = SPEED_1000;
|
||||
else if (bmcr & BMCR_SPEED100)
|
||||
sp = SPEED_100;
|
||||
else
|
||||
sp = SPEED_10;
|
||||
} else if (status & BMSR_ANEGCOMPLETE) {
|
||||
err = mdio_read(cphy, 0, VSC8211_AUX_CTRL_STAT, &status);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
dplx = (status & F_ACSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
|
||||
sp = G_ACSR_SPEED(status);
|
||||
if (sp == 0)
|
||||
sp = SPEED_10;
|
||||
else if (sp == 1)
|
||||
sp = SPEED_100;
|
||||
else
|
||||
sp = SPEED_1000;
|
||||
|
||||
if (fc && dplx == DUPLEX_FULL) {
|
||||
err = mdio_read(cphy, 0, MII_LPA, &lpa);
|
||||
if (!err)
|
||||
err = mdio_read(cphy, 0, MII_ADVERTISE, &adv);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (lpa & adv & ADVERTISE_PAUSE_CAP)
|
||||
pause = PAUSE_RX | PAUSE_TX;
|
||||
else if ((lpa & ADVERTISE_PAUSE_CAP) &&
|
||||
(lpa & ADVERTISE_PAUSE_ASYM) &&
|
||||
(adv & ADVERTISE_PAUSE_ASYM))
|
||||
pause = PAUSE_TX;
|
||||
else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
|
||||
(adv & ADVERTISE_PAUSE_CAP))
|
||||
pause = PAUSE_RX;
|
||||
}
|
||||
}
|
||||
if (speed)
|
||||
*speed = sp;
|
||||
if (duplex)
|
||||
*duplex = dplx;
|
||||
if (fc)
|
||||
*fc = pause;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vsc8211_power_down(struct cphy *cphy, int enable)
|
||||
{
|
||||
return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
|
||||
enable ? BMCR_PDOWN : 0);
|
||||
}
|
||||
|
||||
static int vsc8211_intr_handler(struct cphy *cphy)
|
||||
{
|
||||
unsigned int cause;
|
||||
int err, cphy_cause = 0;
|
||||
|
||||
err = mdio_read(cphy, 0, VSC8211_INTR_STATUS, &cause);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
cause &= INTR_MASK;
|
||||
if (cause & CFG_CHG_INTR_MASK)
|
||||
cphy_cause |= cphy_cause_link_change;
|
||||
if (cause & (VSC_INTR_RX_FIFO | VSC_INTR_TX_FIFO))
|
||||
cphy_cause |= cphy_cause_fifo_error;
|
||||
return cphy_cause;
|
||||
}
|
||||
|
||||
#ifdef C99_NOT_SUPPORTED
|
||||
static struct cphy_ops vsc8211_ops = {
|
||||
NULL,
|
||||
vsc8211_reset,
|
||||
vsc8211_intr_enable,
|
||||
vsc8211_intr_disable,
|
||||
vsc8211_intr_clear,
|
||||
vsc8211_intr_handler,
|
||||
vsc8211_autoneg_enable,
|
||||
vsc8211_autoneg_restart,
|
||||
t3_phy_advertise,
|
||||
NULL,
|
||||
t3_set_phy_speed_duplex,
|
||||
vsc8211_get_link_status,
|
||||
vsc8211_power_down,
|
||||
};
|
||||
#else
|
||||
static struct cphy_ops vsc8211_ops = {
|
||||
.reset = vsc8211_reset,
|
||||
.intr_enable = vsc8211_intr_enable,
|
||||
.intr_disable = vsc8211_intr_disable,
|
||||
.intr_clear = vsc8211_intr_clear,
|
||||
.intr_handler = vsc8211_intr_handler,
|
||||
.autoneg_enable = vsc8211_autoneg_enable,
|
||||
.autoneg_restart = vsc8211_autoneg_restart,
|
||||
.advertise = t3_phy_advertise,
|
||||
.set_speed_duplex = t3_set_phy_speed_duplex,
|
||||
.get_link_status = vsc8211_get_link_status,
|
||||
.power_down = vsc8211_power_down,
|
||||
};
|
||||
#endif
|
||||
|
||||
void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops)
|
||||
{
|
||||
cphy_init(phy, adapter, phy_addr, &vsc8211_ops, mdio_ops);
|
||||
}
|
||||
415
sys/dev/cxgb/common/cxgb_xgmac.c
Normal file
415
sys/dev/cxgb/common/cxgb_xgmac.c
Normal file
@ -0,0 +1,415 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <dev/cxgb/common/cxgb_common.h>
|
||||
#include <dev/cxgb/common/cxgb_regs.h>
|
||||
|
||||
/*
|
||||
* # of exact address filters. The first one is used for the station address,
|
||||
* the rest are available for multicast addresses.
|
||||
*/
|
||||
#define EXACT_ADDR_FILTERS 8
|
||||
|
||||
static inline int macidx(const struct cmac *mac)
|
||||
{
|
||||
return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
|
||||
}
|
||||
|
||||
static void xaui_serdes_reset(struct cmac *mac)
|
||||
{
|
||||
static const unsigned int clear[] = {
|
||||
F_PWRDN0 | F_PWRDN1, F_RESETPLL01, F_RESET0 | F_RESET1,
|
||||
F_PWRDN2 | F_PWRDN3, F_RESETPLL23, F_RESET2 | F_RESET3
|
||||
};
|
||||
|
||||
int i;
|
||||
adapter_t *adap = mac->adapter;
|
||||
u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;
|
||||
|
||||
t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
|
||||
F_RESET3 | F_RESET2 | F_RESET1 | F_RESET0 |
|
||||
F_PWRDN3 | F_PWRDN2 | F_PWRDN1 | F_PWRDN0 |
|
||||
F_RESETPLL23 | F_RESETPLL01);
|
||||
(void)t3_read_reg(adap, ctrl);
|
||||
udelay(15);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clear); i++) {
|
||||
t3_set_reg_field(adap, ctrl, clear[i], 0);
|
||||
udelay(15);
|
||||
}
|
||||
}
|
||||
|
||||
void t3b_pcs_reset(struct cmac *mac)
|
||||
{
|
||||
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
|
||||
F_PCS_RESET_, 0);
|
||||
udelay(20);
|
||||
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, 0,
|
||||
F_PCS_RESET_);
|
||||
}
|
||||
|
||||
int t3_mac_reset(struct cmac *mac)
|
||||
{
|
||||
static struct addr_val_pair mac_reset_avp[] = {
|
||||
{ A_XGM_TX_CTRL, 0 },
|
||||
{ A_XGM_RX_CTRL, 0 },
|
||||
{ A_XGM_RX_CFG, F_DISPAUSEFRAMES | F_EN1536BFRAMES |
|
||||
F_RMFCS | F_ENJUMBO | F_ENHASHMCAST },
|
||||
{ A_XGM_RX_HASH_LOW, 0 },
|
||||
{ A_XGM_RX_HASH_HIGH, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_1, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_2, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_3, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_4, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_5, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_6, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_7, 0 },
|
||||
{ A_XGM_RX_EXACT_MATCH_LOW_8, 0 },
|
||||
{ A_XGM_STAT_CTRL, F_CLRSTATS }
|
||||
};
|
||||
u32 val;
|
||||
adapter_t *adap = mac->adapter;
|
||||
unsigned int oft = mac->offset;
|
||||
|
||||
t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
|
||||
(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
|
||||
|
||||
t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
|
||||
t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
|
||||
F_RXSTRFRWRD | F_DISERRFRAMES,
|
||||
uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
|
||||
|
||||
if (uses_xaui(adap)) {
|
||||
if (adap->params.rev == 0) {
|
||||
t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
|
||||
F_RXENABLE | F_TXENABLE);
|
||||
if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
|
||||
F_CMULOCK, 1, 5, 2)) {
|
||||
CH_ERR(adap,
|
||||
"MAC %d XAUI SERDES CMU lock failed\n",
|
||||
macidx(mac));
|
||||
return -1;
|
||||
}
|
||||
t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
|
||||
F_SERDESRESET_);
|
||||
} else
|
||||
xaui_serdes_reset(mac);
|
||||
}
|
||||
|
||||
if (adap->params.rev > 0)
|
||||
t3_write_reg(adap, A_XGM_PAUSE_TIMER + oft, 0xf000);
|
||||
|
||||
val = F_MAC_RESET_;
|
||||
if (is_10G(adap))
|
||||
val |= F_PCS_RESET_;
|
||||
else if (uses_xaui(adap))
|
||||
val |= F_PCS_RESET_ | F_XG2G_RESET_;
|
||||
else
|
||||
val |= F_RGMII_RESET_ | F_XG2G_RESET_;
|
||||
t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
|
||||
(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
|
||||
if ((val & F_PCS_RESET_) && adap->params.rev) {
|
||||
t3_os_sleep(1);
|
||||
t3b_pcs_reset(mac);
|
||||
}
|
||||
|
||||
memset(&mac->stats, 0, sizeof(mac->stats));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the exact match register 'idx' to recognize the given Ethernet address.
|
||||
*/
|
||||
static void set_addr_filter(struct cmac *mac, int idx, const u8 *addr)
|
||||
{
|
||||
u32 addr_lo, addr_hi;
|
||||
unsigned int oft = mac->offset + idx * 8;
|
||||
|
||||
addr_lo = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
|
||||
addr_hi = (addr[5] << 8) | addr[4];
|
||||
|
||||
t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
|
||||
t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
|
||||
}
|
||||
|
||||
/* Set one of the station's unicast MAC addresses. */
|
||||
int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6])
|
||||
{
|
||||
if (idx >= mac->nucast)
|
||||
return -EINVAL;
|
||||
set_addr_filter(mac, idx, addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Specify the number of exact address filters that should be reserved for
|
||||
* unicast addresses. Caller should reload the unicast and multicast addresses
|
||||
* after calling this.
|
||||
*/
|
||||
int t3_mac_set_num_ucast(struct cmac *mac, int n)
|
||||
{
|
||||
if (n > EXACT_ADDR_FILTERS)
|
||||
return -EINVAL;
|
||||
mac->nucast = n;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Calculate the RX hash filter index of an Ethernet address */
|
||||
static int hash_hw_addr(const u8 *addr)
|
||||
{
|
||||
int hash = 0, octet, bit, i = 0, c;
|
||||
|
||||
for (octet = 0; octet < 6; ++octet)
|
||||
for (c = addr[octet], bit = 0; bit < 8; c >>= 1, ++bit) {
|
||||
hash ^= (c & 1) << i;
|
||||
if (++i == 6)
|
||||
i = 0;
|
||||
}
|
||||
return hash;
|
||||
}
|
||||
|
||||
int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm)
|
||||
{
|
||||
u32 val, hash_lo, hash_hi;
|
||||
adapter_t *adap = mac->adapter;
|
||||
unsigned int oft = mac->offset;
|
||||
|
||||
val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
|
||||
if (promisc_rx_mode(rm))
|
||||
val |= F_COPYALLFRAMES;
|
||||
t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
|
||||
|
||||
if (allmulti_rx_mode(rm))
|
||||
hash_lo = hash_hi = 0xffffffff;
|
||||
else {
|
||||
u8 *addr;
|
||||
int exact_addr_idx = mac->nucast;
|
||||
|
||||
hash_lo = hash_hi = 0;
|
||||
while ((addr = t3_get_next_mcaddr(rm)))
|
||||
if (exact_addr_idx < EXACT_ADDR_FILTERS)
|
||||
set_addr_filter(mac, exact_addr_idx++, addr);
|
||||
else {
|
||||
int hash = hash_hw_addr(addr);
|
||||
|
||||
if (hash < 32)
|
||||
hash_lo |= (1 << hash);
|
||||
else
|
||||
hash_hi |= (1 << (hash - 32));
|
||||
}
|
||||
}
|
||||
|
||||
t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
|
||||
t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
|
||||
{
|
||||
int hwm, lwm;
|
||||
unsigned int thres, v;
|
||||
adapter_t *adap = mac->adapter;
|
||||
|
||||
/*
|
||||
* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max
|
||||
* packet size register includes header, but not FCS.
|
||||
*/
|
||||
mtu += 14;
|
||||
if (mtu > MAX_FRAME_SIZE - 4)
|
||||
return -EINVAL;
|
||||
t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
|
||||
|
||||
/*
|
||||
* Adjust the PAUSE frame watermarks. We always set the LWM, and the
|
||||
* HWM only if flow-control is enabled.
|
||||
*/
|
||||
hwm = max(MAC_RXFIFO_SIZE - 3 * mtu, MAC_RXFIFO_SIZE / 2U);
|
||||
hwm = min(hwm, 3 * MAC_RXFIFO_SIZE / 4 + 1024);
|
||||
lwm = hwm - 1024;
|
||||
v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
|
||||
v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
|
||||
v |= V_RXFIFOPAUSELWM(lwm / 8);
|
||||
if (G_RXFIFOPAUSEHWM(v))
|
||||
v = (v & ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM)) |
|
||||
V_RXFIFOPAUSEHWM(hwm / 8);
|
||||
t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
|
||||
|
||||
/* Adjust the TX FIFO threshold based on the MTU */
|
||||
thres = (adap->params.vpd.cclk * 1000) / 15625;
|
||||
thres = (thres * mtu) / 1000;
|
||||
if (is_10G(adap))
|
||||
thres /= 10;
|
||||
thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
|
||||
thres = max(thres, 8U); /* need at least 8 */
|
||||
t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
|
||||
V_TXFIFOTHRESH(M_TXFIFOTHRESH),
|
||||
V_TXFIFOTHRESH(thres));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
|
||||
{
|
||||
u32 val;
|
||||
adapter_t *adap = mac->adapter;
|
||||
unsigned int oft = mac->offset;
|
||||
|
||||
if (duplex >= 0 && duplex != DUPLEX_FULL)
|
||||
return -EINVAL;
|
||||
if (speed >= 0) {
|
||||
if (speed == SPEED_10)
|
||||
val = V_PORTSPEED(0);
|
||||
else if (speed == SPEED_100)
|
||||
val = V_PORTSPEED(1);
|
||||
else if (speed == SPEED_1000)
|
||||
val = V_PORTSPEED(2);
|
||||
else if (speed == SPEED_10000)
|
||||
val = V_PORTSPEED(3);
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
|
||||
V_PORTSPEED(M_PORTSPEED), val);
|
||||
}
|
||||
|
||||
val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
|
||||
val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
|
||||
if (fc & PAUSE_TX)
|
||||
val |= V_RXFIFOPAUSEHWM(G_RXFIFOPAUSELWM(val) + 128); /* +1KB */
|
||||
t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
|
||||
|
||||
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
|
||||
(fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int t3_mac_enable(struct cmac *mac, int which)
|
||||
{
|
||||
int idx = macidx(mac);
|
||||
adapter_t *adap = mac->adapter;
|
||||
unsigned int oft = mac->offset;
|
||||
|
||||
if (which & MAC_DIRECTION_TX) {
|
||||
t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
|
||||
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
|
||||
t3_write_reg(adap, A_TP_PIO_DATA, 0xbf000001);
|
||||
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
|
||||
t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
|
||||
}
|
||||
if (which & MAC_DIRECTION_RX)
|
||||
t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int t3_mac_disable(struct cmac *mac, int which)
|
||||
{
|
||||
int idx = macidx(mac);
|
||||
adapter_t *adap = mac->adapter;
|
||||
|
||||
if (which & MAC_DIRECTION_TX) {
|
||||
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
|
||||
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
|
||||
t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
|
||||
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
|
||||
t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 0);
|
||||
}
|
||||
if (which & MAC_DIRECTION_RX)
|
||||
t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is called periodically to accumulate the current values of the
|
||||
* RMON counters into the port statistics. Since the packet counters are only
|
||||
* 32 bits they can overflow in ~286 secs at 10G, so the function should be
|
||||
* called more frequently than that. The byte counters are 45-bit wide, they
|
||||
* would overflow in ~7.8 hours.
|
||||
*/
|
||||
const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
|
||||
{
|
||||
#define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
|
||||
#define RMON_UPDATE(mac, name, reg) \
|
||||
(mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
|
||||
#define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
|
||||
(mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
|
||||
((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
|
||||
|
||||
u32 v, lo;
|
||||
|
||||
RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
|
||||
RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
|
||||
RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
|
||||
RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
|
||||
RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
|
||||
RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
|
||||
RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
|
||||
RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);
|
||||
RMON_UPDATE(mac, rx_symbol_errs, RX_SYM_CODE_ERR_FRAMES);
|
||||
|
||||
RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
|
||||
mac->stats.rx_too_long += RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
|
||||
|
||||
RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
|
||||
RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
|
||||
RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);
|
||||
RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES);
|
||||
RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES);
|
||||
RMON_UPDATE(mac, rx_frames_1024_1518, RX_1024_1518B_FRAMES);
|
||||
RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES);
|
||||
|
||||
RMON_UPDATE64(mac, tx_octets, TX_BYTE_LOW, TX_BYTE_HIGH);
|
||||
RMON_UPDATE64(mac, tx_frames, TX_FRAME_LOW, TX_FRAME_HIGH);
|
||||
RMON_UPDATE(mac, tx_mcast_frames, TX_MCAST);
|
||||
RMON_UPDATE(mac, tx_bcast_frames, TX_BCAST);
|
||||
RMON_UPDATE(mac, tx_pause, TX_PAUSE);
|
||||
/* This counts error frames in general (bad FCS, underrun, etc). */
|
||||
RMON_UPDATE(mac, tx_underrun, TX_ERR_FRAMES);
|
||||
|
||||
RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES);
|
||||
RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES);
|
||||
RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES);
|
||||
RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES);
|
||||
RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES);
|
||||
RMON_UPDATE(mac, tx_frames_1024_1518, TX_1024_1518B_FRAMES);
|
||||
RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES);
|
||||
|
||||
/* The next stat isn't clear-on-read. */
|
||||
t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);
|
||||
v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
|
||||
lo = (u32)mac->stats.rx_cong_drops;
|
||||
mac->stats.rx_cong_drops += (u64)(v - lo);
|
||||
|
||||
return &mac->stats;
|
||||
}
|
||||
438
sys/dev/cxgb/cxgb_adapter.h
Normal file
438
sys/dev/cxgb/cxgb_adapter.h
Normal file
@ -0,0 +1,438 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef _CXGB_ADAPTER_H_
|
||||
#define _CXGB_ADAPTER_H_
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/mbuf.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/sockio.h>
|
||||
|
||||
#include <net/ethernet.h>
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/bus_dma.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
struct adapter;
|
||||
struct sge_qset;
|
||||
extern int cxgb_debug;
|
||||
|
||||
struct port_info {
|
||||
struct adapter *adapter;
|
||||
struct ifnet *ifp;
|
||||
int if_flags;
|
||||
const struct port_type_info *port_type;
|
||||
struct cphy phy;
|
||||
struct cmac mac;
|
||||
struct link_config link_config;
|
||||
int activity;
|
||||
struct ifmedia media;
|
||||
struct mtx lock;
|
||||
|
||||
int port;
|
||||
uint8_t hw_addr[ETHER_ADDR_LEN];
|
||||
uint8_t nqsets;
|
||||
uint8_t first_qset;
|
||||
struct taskqueue *tq;
|
||||
struct task start_task;
|
||||
struct cdev *port_cdev;
|
||||
};
|
||||
|
||||
enum { /* adapter flags */
|
||||
FULL_INIT_DONE = (1 << 0),
|
||||
USING_MSI = (1 << 1),
|
||||
USING_MSIX = (1 << 2),
|
||||
QUEUES_BOUND = (1 << 3),
|
||||
FW_UPTODATE = (1 << 4),
|
||||
};
|
||||
|
||||
/* Max active LRO sessions per queue set */
|
||||
#define MAX_LRO_PER_QSET 8
|
||||
|
||||
|
||||
#define FL_Q_SIZE 4096
|
||||
#define JUMBO_Q_SIZE 512
|
||||
#define RSPQ_Q_SIZE 1024
|
||||
#define TX_ETH_Q_SIZE 1024
|
||||
|
||||
/*
|
||||
* Types of Tx queues in each queue set. Order here matters, do not change.
|
||||
* XXX TOE is not implemented yet, so the extra queues are just placeholders.
|
||||
*/
|
||||
enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
|
||||
|
||||
|
||||
/* careful, the following are set on priv_flags and must not collide with
|
||||
* IFF_ flags!
|
||||
*/
|
||||
enum {
|
||||
LRO_ACTIVE = (1 << 8),
|
||||
};
|
||||
|
||||
struct sge_lro_session {
|
||||
struct t3_mbuf_hdr mh;
|
||||
uint32_t seq;
|
||||
uint16_t ip_len;
|
||||
};
|
||||
|
||||
struct sge_lro {
|
||||
unsigned int enabled;
|
||||
unsigned int num_active;
|
||||
struct sge_lro_session *last_s;
|
||||
struct sge_lro_session s[MAX_LRO_PER_QSET];
|
||||
};
|
||||
|
||||
/* has its own header on linux XXX
|
||||
* but I don't even know what it is :-/
|
||||
*/
|
||||
|
||||
struct t3cdev {
|
||||
int foo; /* XXX fill in */
|
||||
};
|
||||
|
||||
#define RX_BUNDLE_SIZE 8
|
||||
|
||||
struct rsp_desc;
|
||||
|
||||
struct sge_rspq {
|
||||
uint32_t credits;
|
||||
uint32_t size;
|
||||
uint32_t cidx;
|
||||
uint32_t gen;
|
||||
uint32_t polling;
|
||||
uint32_t holdoff_tmr;
|
||||
uint32_t next_holdoff;
|
||||
uint32_t imm_data;
|
||||
uint32_t pure_rsps;
|
||||
struct rsp_desc *desc;
|
||||
bus_addr_t phys_addr;
|
||||
uint32_t cntxt_id;
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
struct t3_mbuf_hdr mh;
|
||||
struct mtx lock;
|
||||
};
|
||||
|
||||
struct rx_desc;
|
||||
struct rx_sw_desc;
|
||||
|
||||
struct sge_fl {
|
||||
uint32_t buf_size;
|
||||
uint32_t credits;
|
||||
uint32_t size;
|
||||
uint32_t cidx;
|
||||
uint32_t pidx;
|
||||
uint32_t gen;
|
||||
struct rx_desc *desc;
|
||||
struct rx_sw_desc *sdesc;
|
||||
bus_addr_t phys_addr;
|
||||
uint32_t cntxt_id;
|
||||
uint64_t empty;
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
struct mtx fl_locks[8];
|
||||
};
|
||||
|
||||
struct tx_desc;
|
||||
struct tx_sw_desc;
|
||||
|
||||
struct sge_txq {
|
||||
uint64_t flags;
|
||||
uint32_t in_use;
|
||||
uint32_t size;
|
||||
uint32_t processed;
|
||||
uint32_t cleaned;
|
||||
uint32_t stop_thres;
|
||||
uint32_t cidx;
|
||||
uint32_t pidx;
|
||||
uint32_t gen;
|
||||
uint32_t unacked;
|
||||
struct tx_desc *desc;
|
||||
struct tx_sw_desc *sdesc;
|
||||
uint32_t token;
|
||||
bus_addr_t phys_addr;
|
||||
uint32_t cntxt_id;
|
||||
uint64_t stops;
|
||||
uint64_t restarts;
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
struct mtx lock;
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
SGE_PSTAT_TSO, /* # of TSO requests */
|
||||
SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
|
||||
SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
|
||||
SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
|
||||
SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
|
||||
SGE_PSTATS_LRO_QUEUED, /* # of LRO appended packets */
|
||||
SGE_PSTATS_LRO_FLUSHED, /* # of LRO flushed packets */
|
||||
SGE_PSTATS_LRO_X_STREAMS, /* # of exceeded LRO contexts */
|
||||
};
|
||||
|
||||
#define SGE_PSTAT_MAX (SGE_PSTATS_LRO_X_STREAMS+1)
|
||||
|
||||
struct sge_qset {
|
||||
struct sge_rspq rspq;
|
||||
struct sge_fl fl[SGE_RXQ_PER_SET];
|
||||
struct sge_lro lro;
|
||||
struct sge_txq txq[SGE_TXQ_PER_SET];
|
||||
unsigned long txq_stopped; /* which Tx queues are stopped */
|
||||
uint64_t port_stats[SGE_PSTAT_MAX];
|
||||
struct port_info *port;
|
||||
};
|
||||
|
||||
struct sge {
|
||||
struct sge_qset qs[SGE_QSETS];
|
||||
struct mtx reg_lock;
|
||||
};
|
||||
|
||||
struct adapter {
|
||||
device_t dev;
|
||||
int flags;
|
||||
|
||||
/* PCI register resources */
|
||||
uint32_t regs_rid;
|
||||
struct resource *regs_res;
|
||||
bus_space_handle_t bh;
|
||||
bus_space_tag_t bt;
|
||||
bus_size_t mmio_len;
|
||||
|
||||
/* DMA resources */
|
||||
bus_dma_tag_t parent_dmat;
|
||||
bus_dma_tag_t rx_dmat;
|
||||
bus_dma_tag_t rx_jumbo_dmat;
|
||||
bus_dma_tag_t tx_dmat;
|
||||
|
||||
/* Interrupt resources */
|
||||
struct resource *irq_res;
|
||||
int irq_rid;
|
||||
void *intr_tag;
|
||||
|
||||
uint32_t msix_regs_rid;
|
||||
struct resource *msix_regs_res;
|
||||
|
||||
struct resource *msix_irq_res[SGE_QSETS];
|
||||
int msix_irq_rid[SGE_QSETS];
|
||||
void *msix_intr_tag[SGE_QSETS];
|
||||
|
||||
/* Tasks */
|
||||
struct task ext_intr_task;
|
||||
struct task timer_reclaim_task;
|
||||
struct task slow_intr_task;
|
||||
struct task process_responses_task;
|
||||
struct task mr_refresh_task;
|
||||
struct taskqueue *tq;
|
||||
struct callout cxgb_tick_ch;
|
||||
struct callout sge_timer_ch;
|
||||
|
||||
/* Register lock for use by the hardware layer */
|
||||
struct mtx mdio_lock;
|
||||
|
||||
/* Bookkeeping for the hardware layer */
|
||||
struct adapter_params params;
|
||||
unsigned int slow_intr_mask;
|
||||
unsigned long irq_stats[IRQ_NUM_STATS];
|
||||
|
||||
struct sge sge;
|
||||
struct mc7 pmrx;
|
||||
struct mc7 pmtx;
|
||||
struct mc7 cm;
|
||||
struct mc5 mc5;
|
||||
|
||||
struct port_info port[MAX_NPORTS];
|
||||
device_t portdev[MAX_NPORTS];
|
||||
struct t3cdev tdev;
|
||||
char fw_version[64];
|
||||
uint32_t open_device_map;
|
||||
struct mtx lock;
|
||||
};
|
||||
|
||||
struct t3_rx_mode {
|
||||
|
||||
uint32_t idx;
|
||||
struct port_info *port;
|
||||
};
|
||||
|
||||
|
||||
#define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
|
||||
#define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
|
||||
|
||||
#define PORT_LOCK(port) mtx_lock(&(port)->lock);
|
||||
#define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
|
||||
|
||||
#define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
|
||||
#define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
|
||||
|
||||
|
||||
|
||||
static __inline uint32_t
|
||||
t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
|
||||
{
|
||||
return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
|
||||
}
|
||||
|
||||
static __inline void
|
||||
t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
|
||||
{
|
||||
bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
|
||||
{
|
||||
*val = pci_read_config(adapter->dev, reg, 4);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
|
||||
{
|
||||
pci_write_config(adapter->dev, reg, val, 4);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
|
||||
{
|
||||
*val = pci_read_config(adapter->dev, reg, 2);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
|
||||
{
|
||||
pci_write_config(adapter->dev, reg, val, 2);
|
||||
}
|
||||
|
||||
static __inline uint8_t *
|
||||
t3_get_next_mcaddr(struct t3_rx_mode *rm)
|
||||
{
|
||||
uint8_t *macaddr = NULL;
|
||||
|
||||
if (rm->idx == 0)
|
||||
macaddr = rm->port->hw_addr;
|
||||
|
||||
rm->idx++;
|
||||
return (macaddr);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
|
||||
{
|
||||
rm->idx = 0;
|
||||
rm->port = port;
|
||||
}
|
||||
|
||||
static __inline struct port_info *
|
||||
adap2pinfo(struct adapter *adap, int idx)
|
||||
{
|
||||
return &adap->port[idx];
|
||||
}
|
||||
|
||||
int t3_os_find_pci_capability(adapter_t *adapter, int cap);
|
||||
int t3_os_pci_save_state(struct adapter *adapter);
|
||||
int t3_os_pci_restore_state(struct adapter *adapter);
|
||||
void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
|
||||
int speed, int duplex, int fc);
|
||||
void t3_sge_err_intr_handler(adapter_t *adapter);
|
||||
void t3_os_ext_intr_handler(adapter_t *adapter);
|
||||
void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
|
||||
int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
|
||||
|
||||
|
||||
int t3_sge_alloc(struct adapter *);
|
||||
int t3_sge_free(struct adapter *);
|
||||
int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
|
||||
int, struct port_info *);
|
||||
void t3_free_sge_resources(adapter_t *);
|
||||
void t3_sge_start(adapter_t *);
|
||||
void t3b_intr(void *data);
|
||||
void t3_intr_msi(void *data);
|
||||
void t3_intr_msix(void *data);
|
||||
int t3_encap(struct port_info *, struct mbuf **);
|
||||
|
||||
int t3_sge_init_sw(adapter_t *);
|
||||
void t3_sge_deinit_sw(adapter_t *);
|
||||
|
||||
void t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct t3_mbuf_hdr *mh,
|
||||
int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro);
|
||||
void t3_rx_eth(struct port_info *p, struct sge_rspq *rq, struct mbuf *m, int ethpad);
|
||||
void t3_sge_lro_flush_all(adapter_t *adap, struct sge_qset *qs);
|
||||
|
||||
void t3_add_sysctls(adapter_t *sc);
|
||||
int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
|
||||
unsigned char *data);
|
||||
void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
|
||||
/*
|
||||
* XXX figure out how we can return this to being private to sge
|
||||
*/
|
||||
#define desc_reclaimable(q) (q->processed - q->cleaned - TX_MAX_DESC)
|
||||
|
||||
#define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
|
||||
|
||||
static __inline struct sge_qset *
|
||||
fl_to_qset(struct sge_fl *q, int qidx)
|
||||
{
|
||||
return container_of(q, struct sge_qset, fl[qidx]);
|
||||
}
|
||||
|
||||
static __inline struct sge_qset *
|
||||
rspq_to_qset(struct sge_rspq *q)
|
||||
{
|
||||
return container_of(q, struct sge_qset, rspq);
|
||||
}
|
||||
|
||||
static __inline struct sge_qset *
|
||||
txq_to_qset(struct sge_txq *q, int qidx)
|
||||
{
|
||||
return container_of(q, struct sge_qset, txq[qidx]);
|
||||
}
|
||||
|
||||
#undef container_of
|
||||
|
||||
#endif
|
||||
222
sys/dev/cxgb/cxgb_ioctl.h
Normal file
222
sys/dev/cxgb/cxgb_ioctl.h
Normal file
@ -0,0 +1,222 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
#ifndef __CHIOCTL_H__
|
||||
#define __CHIOCTL_H__
|
||||
|
||||
/*
|
||||
* Ioctl commands specific to this driver.
|
||||
*/
|
||||
enum {
|
||||
CH_SETREG = 0x40,
|
||||
CH_GETREG,
|
||||
CH_SETTPI,
|
||||
CH_GETTPI,
|
||||
CH_DEVUP,
|
||||
CH_GETMTUTAB,
|
||||
CH_SETMTUTAB,
|
||||
CH_GETMTU,
|
||||
CH_SET_PM,
|
||||
CH_GET_PM,
|
||||
CH_GET_TCAM,
|
||||
CH_SET_TCAM,
|
||||
CH_GET_TCB,
|
||||
CH_READ_TCAM_WORD,
|
||||
CH_GET_MEM,
|
||||
CH_GET_SGE_CONTEXT,
|
||||
CH_GET_SGE_DESC,
|
||||
CH_LOAD_FW,
|
||||
CH_GET_PROTO,
|
||||
CH_SET_PROTO,
|
||||
CH_SET_TRACE_FILTER,
|
||||
CH_SET_QSET_PARAMS,
|
||||
CH_GET_QSET_PARAMS,
|
||||
CH_SET_QSET_NUM,
|
||||
CH_GET_QSET_NUM,
|
||||
CH_SET_PKTSCHED,
|
||||
CH_IFCONF_GETREGS,
|
||||
CH_GETMIIREGS,
|
||||
CH_SETMIIREGS,
|
||||
|
||||
};
|
||||
|
||||
struct ch_reg {
|
||||
uint32_t addr;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
struct ch_cntxt {
|
||||
uint32_t cntxt_type;
|
||||
uint32_t cntxt_id;
|
||||
uint32_t data[4];
|
||||
};
|
||||
|
||||
/* context types */
|
||||
enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
|
||||
|
||||
struct ch_desc {
|
||||
uint32_t cmd;
|
||||
uint32_t queue_num;
|
||||
uint32_t idx;
|
||||
uint32_t size;
|
||||
uint8_t data[128];
|
||||
};
|
||||
|
||||
struct ch_mem_range {
|
||||
uint32_t cmd;
|
||||
uint32_t mem_id;
|
||||
uint32_t addr;
|
||||
uint32_t len;
|
||||
uint32_t version;
|
||||
uint8_t *buf;
|
||||
};
|
||||
|
||||
struct ch_qset_params {
|
||||
uint32_t qset_idx;
|
||||
int32_t txq_size[3];
|
||||
int32_t rspq_size;
|
||||
int32_t fl_size[2];
|
||||
int32_t intr_lat;
|
||||
int32_t polling;
|
||||
int32_t cong_thres;
|
||||
};
|
||||
|
||||
struct ch_pktsched_params {
|
||||
uint32_t cmd;
|
||||
uint8_t sched;
|
||||
uint8_t idx;
|
||||
uint8_t min;
|
||||
uint8_t max;
|
||||
uint8_t binding;
|
||||
};
|
||||
|
||||
#ifndef TCB_SIZE
|
||||
# define TCB_SIZE 128
|
||||
#endif
|
||||
|
||||
/* TCB size in 32-bit words */
|
||||
#define TCB_WORDS (TCB_SIZE / 4)
|
||||
|
||||
enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */
|
||||
|
||||
struct ch_mtus {
|
||||
uint32_t cmd;
|
||||
uint32_t nmtus;
|
||||
uint16_t mtus[NMTUS];
|
||||
};
|
||||
|
||||
struct ch_pm {
|
||||
uint32_t cmd;
|
||||
uint32_t tx_pg_sz;
|
||||
uint32_t tx_num_pg;
|
||||
uint32_t rx_pg_sz;
|
||||
uint32_t rx_num_pg;
|
||||
uint32_t pm_total;
|
||||
};
|
||||
|
||||
struct ch_tcam {
|
||||
uint32_t cmd;
|
||||
uint32_t tcam_size;
|
||||
uint32_t nservers;
|
||||
uint32_t nroutes;
|
||||
uint32_t nfilters;
|
||||
};
|
||||
|
||||
struct ch_tcb {
|
||||
uint32_t cmd;
|
||||
uint32_t tcb_index;
|
||||
uint32_t tcb_data[TCB_WORDS];
|
||||
};
|
||||
|
||||
struct ch_tcam_word {
|
||||
uint32_t cmd;
|
||||
uint32_t addr;
|
||||
uint32_t buf[3];
|
||||
};
|
||||
|
||||
struct ch_trace {
|
||||
uint32_t cmd;
|
||||
uint32_t sip;
|
||||
uint32_t sip_mask;
|
||||
uint32_t dip;
|
||||
uint32_t dip_mask;
|
||||
uint16_t sport;
|
||||
uint16_t sport_mask;
|
||||
uint16_t dport;
|
||||
uint16_t dport_mask;
|
||||
uint32_t vlan:12,
|
||||
vlan_mask:12,
|
||||
intf:4,
|
||||
intf_mask:4;
|
||||
uint8_t proto;
|
||||
uint8_t proto_mask;
|
||||
uint8_t invert_match:1,
|
||||
config_tx:1,
|
||||
config_rx:1,
|
||||
trace_tx:1,
|
||||
trace_rx:1;
|
||||
};
|
||||
|
||||
#define REGDUMP_SIZE (4 * 1024)
|
||||
|
||||
struct ifconf_regs {
|
||||
uint32_t version;
|
||||
uint32_t len; /* bytes */
|
||||
uint8_t *data;
|
||||
};
|
||||
|
||||
struct mii_data {
|
||||
uint32_t phy_id;
|
||||
uint32_t reg_num;
|
||||
uint32_t val_in;
|
||||
uint32_t val_out;
|
||||
};
|
||||
|
||||
#define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg)
|
||||
#define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg)
|
||||
#define CHELSIO_GET_MEM _IOWR('f', CH_GET_MEM, struct ch_mem_range)
|
||||
#define CHELSIO_GET_SGE_CONTEXT _IOWR('f', CH_GET_SGE_CONTEXT, struct ch_cntxt)
|
||||
#define CHELSIO_GET_SGE_DESC _IOWR('f', CH_GET_SGE_DESC, struct ch_desc)
|
||||
#define CHELSIO_GET_QSET_PARAMS _IOWR('f', CH_GET_QSET_PARAMS, struct ch_qset_params)
|
||||
#define CHELSIO_SET_QSET_PARAMS _IOW('f', CH_SET_QSET_PARAMS, struct ch_qset_params)
|
||||
#define CHELSIO_GET_QSET_NUM _IOWR('f', CH_GET_QSET_NUM, struct ch_reg)
|
||||
#define CHELSIO_SET_QSET_NUM _IOW('f', CH_SET_QSET_NUM, struct ch_reg)
|
||||
|
||||
|
||||
#define CHELSIO_SET_TRACE_FILTER _IOW('f', CH_SET_TRACE_FILTER, struct ch_trace)
|
||||
#define CHELSIO_SET_PKTSCHED _IOW('f', CH_SET_PKTSCHED, struct ch_pktsched_params)
|
||||
#define CHELSIO_IFCONF_GETREGS _IOWR('f', CH_IFCONF_GETREGS, struct ifconf_regs)
|
||||
#define SIOCGMIIREG _IOWR('f', CH_GETMIIREGS, struct mii_data)
|
||||
#define SIOCSMIIREG _IOWR('f', CH_SETMIIREGS, struct mii_data)
|
||||
#endif
|
||||
427
sys/dev/cxgb/cxgb_lro.c
Normal file
427
sys/dev/cxgb/cxgb_lro.c
Normal file
@ -0,0 +1,427 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/conf.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/bus_dma.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/queue.h>
|
||||
#include <sys/taskqueue.h>
|
||||
|
||||
#include <netinet/in_systm.h>
|
||||
#include <netinet/in.h>
|
||||
#include <netinet/ip.h>
|
||||
#include <netinet/tcp.h>
|
||||
|
||||
#include <dev/cxgb/cxgb_osdep.h>
|
||||
#include <dev/cxgb/common/cxgb_common.h>
|
||||
#include <dev/cxgb/common/cxgb_t3_cpl.h>
|
||||
|
||||
#include <machine/in_cksum.h>
|
||||
|
||||
|
||||
#ifndef M_LRO
|
||||
#define M_LRO 0x0200
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
#define MBUF_HEADER_CHECK(mh) do { \
|
||||
struct mbuf *head = mh->mh_head; \
|
||||
struct mbuf *tail = mh->mh_tail; \
|
||||
if (head->m_len == 0 || head->m_pkthdr.len == 0 \
|
||||
|| (head->m_flags & M_PKTHDR) == 0) \
|
||||
panic("lro_flush_session - mbuf len=%d pktlen=%d flags=0x%x\n", \
|
||||
head->m_len, head->m_pkthdr.len, head->m_flags); \
|
||||
if ((head->m_flags & M_PKTHDR) == 0) \
|
||||
panic("first mbuf is not packet header - flags=0x%x\n", \
|
||||
head->m_flags); \
|
||||
if ((head == tail && head->m_len != head->m_pkthdr.len)) \
|
||||
panic("len=%d pktlen=%d mismatch\n", \
|
||||
head->m_len, head->m_pkthdr.len); \
|
||||
if (head->m_len < ETHER_HDR_LEN || head->m_pkthdr.len < ETHER_HDR_LEN) \
|
||||
panic("packet too small len=%d pktlen=%d\n", \
|
||||
head->m_len, head->m_pkthdr.len);\
|
||||
} while (0)
|
||||
#else
|
||||
#define MBUF_HEADER_CHECK(m)
|
||||
#endif
|
||||
|
||||
#define IPH_OFFSET (2 + sizeof (struct cpl_rx_pkt) + ETHER_HDR_LEN)
|
||||
#define LRO_SESSION_IDX_HINT_HASH(hash) (hash & (MAX_LRO_PER_QSET - 1))
|
||||
#define LRO_IDX_INC(idx) idx = (idx + 1) & (MAX_LRO_PER_QSET - 1)
|
||||
|
||||
static __inline struct sge_lro_session *
|
||||
lro_session(struct sge_lro *l, int idx)
|
||||
{
|
||||
return l->s + idx;
|
||||
}
|
||||
|
||||
static __inline int
|
||||
lro_match_session(struct sge_lro_session *s,
|
||||
struct ip *ih, struct tcphdr *th)
|
||||
{
|
||||
struct ip *sih = (struct ip *)(s->mh.mh_head->m_data + IPH_OFFSET);
|
||||
struct tcphdr *sth = (struct tcphdr *) (sih + 1);
|
||||
|
||||
/*
|
||||
* Linux driver doesn't include destination port check --
|
||||
* need to find out why XXX
|
||||
*/
|
||||
return (*(uint32_t *)&th->th_sport == *(uint32_t *)&sth->th_sport &&
|
||||
*(uint32_t *)&th->th_dport == *(uint32_t *)&sth->th_dport &&
|
||||
ih->ip_src.s_addr == ih->ip_src.s_addr &&
|
||||
ih->ip_dst.s_addr == sih->ip_dst.s_addr);
|
||||
}
|
||||
|
||||
static __inline struct sge_lro_session *
|
||||
lro_find_session(struct sge_lro *l, int idx, struct ip *ih, struct tcphdr *th)
|
||||
{
|
||||
struct sge_lro_session *s;
|
||||
int active = 0;
|
||||
|
||||
while (active < l->num_active) {
|
||||
s = lro_session(l, idx);
|
||||
if (s->mh.mh_head) {
|
||||
if (lro_match_session(s, ih, th)) {
|
||||
l->last_s = s;
|
||||
return s;
|
||||
}
|
||||
active++;
|
||||
}
|
||||
LRO_IDX_INC(idx);
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static __inline int
|
||||
can_lro_packet(struct cpl_rx_pkt *cpl, unsigned int rss_hi)
|
||||
{
|
||||
struct ether_header *eh = (struct ether_header *)(cpl + 1);
|
||||
struct ip *ih = (struct ip *)(eh + 1);
|
||||
|
||||
/*
|
||||
* XXX VLAN support?
|
||||
*/
|
||||
if (__predict_false(G_HASHTYPE(ntohl(rss_hi)) != RSS_HASH_4_TUPLE ||
|
||||
(*((uint8_t *)cpl + 1) & 0x90) != 0x10 ||
|
||||
cpl->csum != 0xffff || eh->ether_type != ntohs(ETHERTYPE_IP) ||
|
||||
ih->ip_hl != (sizeof (*ih) >> 2))) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
can_lro_tcpsegment(struct tcphdr *th)
|
||||
{
|
||||
int olen = (th->th_off << 2) - sizeof (*th);
|
||||
u8 control_bits = *((u8 *)th + 13);
|
||||
|
||||
if (__predict_false((control_bits & 0xB7) != 0x10))
|
||||
goto no_lro;
|
||||
|
||||
if (olen) {
|
||||
uint32_t *ptr = (u32 *)(th + 1);
|
||||
if (__predict_false(olen != TCPOLEN_TSTAMP_APPA ||
|
||||
*ptr != ntohl((TCPOPT_NOP << 24) |
|
||||
(TCPOPT_NOP << 16) |
|
||||
(TCPOPT_TIMESTAMP << 8) |
|
||||
TCPOLEN_TIMESTAMP)))
|
||||
goto no_lro;
|
||||
}
|
||||
|
||||
return 1;
|
||||
|
||||
no_lro:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __inline void
|
||||
lro_new_session_init(struct sge_lro_session *s, struct t3_mbuf_hdr *mh)
|
||||
{
|
||||
struct ip *ih = (struct ip *)(mh->mh_head->m_data + IPH_OFFSET);
|
||||
struct tcphdr *th = (struct tcphdr *) (ih + 1);
|
||||
int ip_len = ntohs(ih->ip_len);
|
||||
|
||||
DPRINTF("%s(s=%p, mh->mh_head=%p, mh->mh_tail=%p)\n", __FUNCTION__,
|
||||
s, mh->mh_head, mh->mh_tail);
|
||||
|
||||
*&(s->mh) = *mh;
|
||||
|
||||
MBUF_HEADER_CHECK(mh);
|
||||
s->ip_len = ip_len;
|
||||
s->seq = ntohl(th->th_seq) + ip_len - sizeof(*ih) - (th->th_off << 2);
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
lro_flush_session(struct sge_qset *qs, struct sge_lro_session *s, struct t3_mbuf_hdr *mh)
|
||||
{
|
||||
struct sge_lro *l = &qs->lro;
|
||||
struct t3_mbuf_hdr *smh = &s->mh;
|
||||
struct ip *ih = (struct ip *)(smh->mh_head->m_data + IPH_OFFSET);
|
||||
|
||||
|
||||
DPRINTF("%s(qs=%p, s=%p, ", __FUNCTION__,
|
||||
qs, s);
|
||||
|
||||
if (mh)
|
||||
DPRINTF("mh->mh_head=%p, mh->mh_tail=%p)\n",
|
||||
mh->mh_head, mh->mh_tail);
|
||||
else
|
||||
DPRINTF("mh=NULL)\n");
|
||||
|
||||
ih->ip_len = htons(s->ip_len);
|
||||
ih->ip_sum = 0;
|
||||
ih->ip_sum = in_cksum_hdr(ih);
|
||||
|
||||
MBUF_HEADER_CHECK(smh);
|
||||
|
||||
smh->mh_head->m_flags |= M_LRO;
|
||||
t3_rx_eth(qs->port, &qs->rspq, smh->mh_head, 2);
|
||||
|
||||
if (mh) {
|
||||
*smh = *mh;
|
||||
lro_new_session_init(s, mh);
|
||||
} else {
|
||||
smh->mh_head = NULL;
|
||||
smh->mh_tail = NULL;
|
||||
l->num_active--;
|
||||
}
|
||||
|
||||
qs->port_stats[SGE_PSTATS_LRO_FLUSHED]++;
|
||||
}
|
||||
|
||||
static __inline struct sge_lro_session *
|
||||
lro_new_session(struct sge_qset *qs, struct t3_mbuf_hdr *mh, uint32_t rss_hash)
|
||||
{
|
||||
struct sge_lro *l = &qs->lro;
|
||||
int idx = LRO_SESSION_IDX_HINT_HASH(rss_hash);
|
||||
struct sge_lro_session *s = lro_session(l, idx);
|
||||
|
||||
DPRINTF("%s(qs=%p, mh->mh_head=%p, mh->mh_tail=%p, rss_hash=0x%x)\n", __FUNCTION__,
|
||||
qs, mh->mh_head, mh->mh_tail, rss_hash);
|
||||
|
||||
if (__predict_true(!s->mh.mh_head))
|
||||
goto done;
|
||||
|
||||
if (l->num_active > MAX_LRO_PER_QSET)
|
||||
panic("MAX_LRO_PER_QSET exceeded");
|
||||
|
||||
if (l->num_active == MAX_LRO_PER_QSET) {
|
||||
lro_flush_session(qs, s, mh);
|
||||
qs->port_stats[SGE_PSTATS_LRO_X_STREAMS]++;
|
||||
return s;
|
||||
}
|
||||
|
||||
while (1) {
|
||||
LRO_IDX_INC(idx);
|
||||
s = lro_session(l, idx);
|
||||
if (!s->mh.mh_head)
|
||||
break;
|
||||
}
|
||||
done:
|
||||
lro_new_session_init(s, mh);
|
||||
|
||||
l->num_active++;
|
||||
|
||||
return s;
|
||||
|
||||
}
|
||||
|
||||
static __inline int
|
||||
lro_update_session(struct sge_lro_session *s, struct t3_mbuf_hdr *mh)
|
||||
{
|
||||
struct mbuf *m = mh->mh_head;
|
||||
struct t3_mbuf_hdr *smh = &s->mh;
|
||||
struct cpl_rx_pkt *cpl = (struct cpl_rx_pkt *)(smh->mh_head->m_data + 2);
|
||||
struct cpl_rx_pkt *ncpl = (struct cpl_rx_pkt *)(m->m_data + 2);
|
||||
struct ip *nih = (struct ip *)(m->m_data + IPH_OFFSET);
|
||||
struct tcphdr *th, *nth = (struct tcphdr *)(nih + 1);
|
||||
uint32_t seq = ntohl(nth->th_seq);
|
||||
int plen, tcpiphlen, olen = (nth->th_off << 2) - sizeof (*nth);
|
||||
|
||||
|
||||
DPRINTF("%s(s=%p, mh->mh_head=%p, mh->mh_tail=%p)\n", __FUNCTION__,
|
||||
s, mh->mh_head, mh->mh_tail);
|
||||
if (cpl->vlan_valid && cpl->vlan != ncpl->vlan) {
|
||||
return -1;
|
||||
}
|
||||
if (__predict_false(seq != s->seq)) {
|
||||
DPRINTF("sequence mismatch\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
MBUF_HEADER_CHECK(smh);
|
||||
th = (struct tcphdr *)(smh->mh_head->m_data + IPH_OFFSET + sizeof (struct ip));
|
||||
|
||||
if (olen) {
|
||||
uint32_t *ptr = (uint32_t *)(th + 1);
|
||||
uint32_t *nptr = (uint32_t *)(nth + 1);
|
||||
|
||||
if (__predict_false(ntohl(*(ptr + 1)) > ntohl(*(nptr + 1)) ||
|
||||
!*(nptr + 2))) {
|
||||
return -1;
|
||||
}
|
||||
*(ptr + 1) = *(nptr + 1);
|
||||
*(ptr + 2) = *(nptr + 2);
|
||||
}
|
||||
th->th_ack = nth->th_ack;
|
||||
th->th_win = nth->th_win;
|
||||
|
||||
tcpiphlen = (nth->th_off << 2) + sizeof (*nih);
|
||||
plen = ntohs(nih->ip_len) - tcpiphlen;
|
||||
s->seq += plen;
|
||||
s->ip_len += plen;
|
||||
smh->mh_head->m_pkthdr.len += plen;
|
||||
|
||||
#if 0
|
||||
/* XXX this I *do not* understand */
|
||||
if (plen > skb_shinfo(s->skb)->gso_size)
|
||||
skb_shinfo(s->skb)->gso_size = plen;
|
||||
#endif
|
||||
#if __FreeBSD_version > 700000
|
||||
if (plen > smh->mh_head->m_pkthdr.tso_segsz)
|
||||
smh->mh_head->m_pkthdr.tso_segsz = plen;
|
||||
#endif
|
||||
DPRINTF("m_adj(%d)\n", (int)(IPH_OFFSET + tcpiphlen));
|
||||
m_adj(m, IPH_OFFSET + tcpiphlen);
|
||||
#if 0
|
||||
if (__predict_false(!skb_shinfo(s->skb)->frag_list))
|
||||
skb_shinfo(s->skb)->frag_list = skb;
|
||||
|
||||
#endif
|
||||
mh->mh_head->m_flags &= ~M_PKTHDR;
|
||||
smh->mh_tail->m_next = mh->mh_head;
|
||||
smh->mh_tail = mh->mh_tail;
|
||||
#if 0
|
||||
|
||||
/*
|
||||
* XXX we really need to be able to
|
||||
* support vectors of buffers in FreeBSD
|
||||
*/
|
||||
int nr = skb_shinfo(s->skb)->nr_frags;
|
||||
skb_shinfo(s->skb)->frags[nr].page = frag->page;
|
||||
skb_shinfo(s->skb)->frags[nr].page_offset =
|
||||
frag->page_offset + IPH_OFFSET + tcpiphlen;
|
||||
skb_shinfo(s->skb)->frags[nr].size = plen;
|
||||
skb_shinfo(s->skb)->nr_frags = ++nr;
|
||||
|
||||
#endif
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct t3_mbuf_hdr *mh,
|
||||
int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro)
|
||||
{
|
||||
struct mbuf *m = mh->mh_head;
|
||||
struct sge_qset *qs = rspq_to_qset(rq);
|
||||
struct cpl_rx_pkt *cpl = (struct cpl_rx_pkt *)(m->m_data + ethpad);
|
||||
struct ether_header *eh = (struct ether_header *)(cpl + 1);
|
||||
struct ip *ih;
|
||||
struct tcphdr *th;
|
||||
struct sge_lro_session *s = NULL;
|
||||
struct port_info *pi = qs->port;
|
||||
|
||||
if (lro == 0)
|
||||
goto no_lro;
|
||||
|
||||
if (!can_lro_packet(cpl, rss_csum))
|
||||
goto no_lro;
|
||||
|
||||
if (&adap->port[cpl->iff] != pi)
|
||||
panic("bad port index %d\n", cpl->iff);
|
||||
|
||||
ih = (struct ip *)(eh + 1);
|
||||
th = (struct tcphdr *)(ih + 1);
|
||||
|
||||
s = lro_find_session(&qs->lro,
|
||||
LRO_SESSION_IDX_HINT_HASH(rss_hash), ih, th);
|
||||
|
||||
if (__predict_false(!can_lro_tcpsegment(th))) {
|
||||
goto no_lro;
|
||||
} else if (__predict_false(!s)) {
|
||||
s = lro_new_session(qs, mh, rss_hash);
|
||||
} else {
|
||||
if (lro_update_session(s, mh)) {
|
||||
lro_flush_session(qs, s, mh);
|
||||
}
|
||||
if (__predict_false(s->mh.mh_head->m_pkthdr.len + pi->ifp->if_mtu > 65535)) {
|
||||
lro_flush_session(qs, s, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
qs->port_stats[SGE_PSTATS_LRO_QUEUED]++;
|
||||
return;
|
||||
no_lro:
|
||||
if (s)
|
||||
lro_flush_session(qs, s, NULL);
|
||||
|
||||
if (m->m_len == 0 || m->m_pkthdr.len == 0 || (m->m_flags & M_PKTHDR) == 0)
|
||||
DPRINTF("rx_eth_lro mbuf len=%d pktlen=%d flags=0x%x\n",
|
||||
m->m_len, m->m_pkthdr.len, m->m_flags);
|
||||
t3_rx_eth(pi, rq, m, ethpad);
|
||||
}
|
||||
|
||||
void
|
||||
t3_sge_lro_flush_all(adapter_t *adap, struct sge_qset *qs)
|
||||
{
|
||||
struct sge_lro *l = &qs->lro;
|
||||
struct sge_lro_session *s = l->last_s;
|
||||
int active = 0, idx = 0, num_active = l->num_active;
|
||||
|
||||
if (__predict_false(!s))
|
||||
s = lro_session(l, idx);
|
||||
|
||||
while (active < num_active) {
|
||||
if (s->mh.mh_head) {
|
||||
lro_flush_session(qs, s, NULL);
|
||||
active++;
|
||||
}
|
||||
LRO_IDX_INC(idx);
|
||||
s = lro_session(l, idx);
|
||||
}
|
||||
}
|
||||
1792
sys/dev/cxgb/cxgb_main.c
Normal file
1792
sys/dev/cxgb/cxgb_main.c
Normal file
File diff suppressed because it is too large
Load Diff
246
sys/dev/cxgb/cxgb_osdep.h
Normal file
246
sys/dev/cxgb/cxgb_osdep.h
Normal file
@ -0,0 +1,246 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/ctype.h>
|
||||
#include <sys/endian.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
|
||||
#include <dev/cxgb/common/cxgb_version.h>
|
||||
|
||||
#ifndef _CXGB_OSDEP_H_
|
||||
#define _CXGB_OSDEP_H_
|
||||
|
||||
typedef struct adapter adapter_t;
|
||||
|
||||
struct sge_rspq;
|
||||
|
||||
struct t3_mbuf_hdr {
|
||||
struct mbuf *mh_head;
|
||||
struct mbuf *mh_tail;
|
||||
};
|
||||
|
||||
#if __FreeBSD_version > 700030
|
||||
#define INTR_FILTERS
|
||||
#define FIRMWARE_LATEST
|
||||
#endif
|
||||
|
||||
#if ((__FreeBSD_version > 602103) && (__FreeBSD_version < 700000))
|
||||
#define FIRMWARE_LATEST
|
||||
#endif
|
||||
|
||||
#if __FreeBSD_version > 700000
|
||||
#define MSI_SUPPORTED
|
||||
#define TSO_SUPPORTED
|
||||
#define VLAN_SUPPORTED
|
||||
#define TASKQUEUE_CURRENT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Workaround for weird Chelsio issue
|
||||
*/
|
||||
#if __FreeBSD_version > 700029
|
||||
#define PRIV_SUPPORTED
|
||||
#endif
|
||||
|
||||
#define CXGB_TX_CLEANUP_THRESHOLD 32
|
||||
|
||||
|
||||
#ifdef DEBUG_PRINT
|
||||
#define DPRINTF printf
|
||||
#else
|
||||
#define DPRINTF(...)
|
||||
#endif
|
||||
|
||||
#define TX_MAX_SIZE (1 << 16) /* 64KB */
|
||||
#define TX_MAX_SEGS 36 /* maximum supported by card */
|
||||
#define TX_MAX_DESC 4 /* max descriptors per packet */
|
||||
#define TX_START_MAX_DESC (TX_MAX_DESC << 1) /* maximum number of descriptors
|
||||
* call to start used per */
|
||||
#define TX_CLEAN_MAX_DESC (TX_MAX_DESC << 2) /* maximum tx descriptors
|
||||
* to clean per iteration */
|
||||
|
||||
|
||||
#if defined(__i386__) || defined(__amd64__)
|
||||
#define mb() __asm volatile("mfence":::"memory")
|
||||
#define rmb() __asm volatile("lfence":::"memory")
|
||||
#define wmb() __asm volatile("sfence" ::: "memory")
|
||||
#define smp_mb() mb()
|
||||
#endif
|
||||
#define DBG_RX (1 << 0)
|
||||
static const int debug_flags = DBG_RX;
|
||||
|
||||
#ifdef DEBUG_PRINT
|
||||
#define DBG(flag, msg) do { \
|
||||
if ((flag & debug_flags)) \
|
||||
printf msg; \
|
||||
} while (0)
|
||||
#else
|
||||
#define DBG(...)
|
||||
#endif
|
||||
|
||||
#define promisc_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_PROMISC)
|
||||
#define allmulti_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_ALLMULTI)
|
||||
|
||||
#define CH_ERR(adap, fmt, ...)device_printf(adap->dev, fmt, ##__VA_ARGS__);
|
||||
|
||||
#define CH_WARN(adap, fmt, ...) device_printf(adap->dev, fmt, ##__VA_ARGS__)
|
||||
#define CH_ALERT(adap, fmt, ...) device_printf(adap->dev, fmt, ##__VA_ARGS__)
|
||||
|
||||
#define t3_os_sleep(x) DELAY((x) * 1000)
|
||||
|
||||
/* Standard PHY definitions */
|
||||
#define BMCR_LOOPBACK BMCR_LOOP
|
||||
#define BMCR_ISOLATE BMCR_ISO
|
||||
#define BMCR_ANENABLE BMCR_AUTOEN
|
||||
#define BMCR_SPEED1000 BMCR_SPEED1
|
||||
#define BMCR_SPEED100 BMCR_SPEED0
|
||||
#define BMCR_ANRESTART BMCR_STARTNEG
|
||||
#define BMCR_FULLDPLX BMCR_FDX
|
||||
#define BMSR_LSTATUS BMSR_LINK
|
||||
#define BMSR_ANEGCOMPLETE BMSR_ACOMP
|
||||
|
||||
#define MII_LPA MII_ANLPAR
|
||||
#define MII_ADVERTISE MII_ANAR
|
||||
#define MII_CTRL1000 MII_100T2CR
|
||||
|
||||
#define ADVERTISE_PAUSE_CAP ANAR_FC
|
||||
#define ADVERTISE_PAUSE_ASYM 0x0800
|
||||
#define ADVERTISE_1000HALF ANAR_X_HD
|
||||
#define ADVERTISE_1000FULL ANAR_X_FD
|
||||
#define ADVERTISE_10FULL ANAR_10_FD
|
||||
#define ADVERTISE_10HALF ANAR_10
|
||||
#define ADVERTISE_100FULL ANAR_TX_FD
|
||||
#define ADVERTISE_100HALF ANAR_TX
|
||||
|
||||
/* Standard PCI Extended Capaibilities definitions */
|
||||
#define PCI_CAP_ID_VPD 0x03
|
||||
#define PCI_VPD_ADDR 2
|
||||
#define PCI_VPD_ADDR_F 0x8000
|
||||
#define PCI_VPD_DATA 4
|
||||
|
||||
#define PCI_CAP_ID_EXP 0x10
|
||||
#define PCI_EXP_DEVCTL 8
|
||||
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
|
||||
#define PCI_EXP_LNKCTL 16
|
||||
#define PCI_EXP_LNKSTA 18
|
||||
|
||||
/*
|
||||
* Linux compatibility macros
|
||||
*/
|
||||
|
||||
/* Some simple translations */
|
||||
#define __devinit
|
||||
#define udelay(x) DELAY(x)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#define le32_to_cpu(x) le32toh(x)
|
||||
#define cpu_to_le32(x) htole32(x)
|
||||
#define swab32(x) bswap32(x)
|
||||
#define simple_strtoul strtoul
|
||||
|
||||
/* More types and endian definitions */
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef uint64_t u64;
|
||||
|
||||
typedef uint8_t __u8;
|
||||
typedef uint16_t __u16;
|
||||
typedef uint32_t __u32;
|
||||
typedef uint8_t __be8;
|
||||
typedef uint16_t __be16;
|
||||
typedef uint32_t __be32;
|
||||
typedef uint64_t __be64;
|
||||
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
#define __BIG_ENDIAN_BITFIELD
|
||||
#elif BYTE_ORDER == LITTLE_ENDIAN
|
||||
#define __LITTLE_ENDIAN_BITFIELD
|
||||
#else
|
||||
#error "Must set BYTE_ORDER"
|
||||
#endif
|
||||
|
||||
/* Indicates what features are supported by the interface. */
|
||||
#define SUPPORTED_10baseT_Half (1 << 0)
|
||||
#define SUPPORTED_10baseT_Full (1 << 1)
|
||||
#define SUPPORTED_100baseT_Half (1 << 2)
|
||||
#define SUPPORTED_100baseT_Full (1 << 3)
|
||||
#define SUPPORTED_1000baseT_Half (1 << 4)
|
||||
#define SUPPORTED_1000baseT_Full (1 << 5)
|
||||
#define SUPPORTED_Autoneg (1 << 6)
|
||||
#define SUPPORTED_TP (1 << 7)
|
||||
#define SUPPORTED_AUI (1 << 8)
|
||||
#define SUPPORTED_MII (1 << 9)
|
||||
#define SUPPORTED_FIBRE (1 << 10)
|
||||
#define SUPPORTED_BNC (1 << 11)
|
||||
#define SUPPORTED_10000baseT_Full (1 << 12)
|
||||
#define SUPPORTED_Pause (1 << 13)
|
||||
#define SUPPORTED_Asym_Pause (1 << 14)
|
||||
|
||||
/* Indicates what features are advertised by the interface. */
|
||||
#define ADVERTISED_10baseT_Half (1 << 0)
|
||||
#define ADVERTISED_10baseT_Full (1 << 1)
|
||||
#define ADVERTISED_100baseT_Half (1 << 2)
|
||||
#define ADVERTISED_100baseT_Full (1 << 3)
|
||||
#define ADVERTISED_1000baseT_Half (1 << 4)
|
||||
#define ADVERTISED_1000baseT_Full (1 << 5)
|
||||
#define ADVERTISED_Autoneg (1 << 6)
|
||||
#define ADVERTISED_TP (1 << 7)
|
||||
#define ADVERTISED_AUI (1 << 8)
|
||||
#define ADVERTISED_MII (1 << 9)
|
||||
#define ADVERTISED_FIBRE (1 << 10)
|
||||
#define ADVERTISED_BNC (1 << 11)
|
||||
#define ADVERTISED_10000baseT_Full (1 << 12)
|
||||
#define ADVERTISED_Pause (1 << 13)
|
||||
#define ADVERTISED_Asym_Pause (1 << 14)
|
||||
|
||||
/* Enable or disable autonegotiation. If this is set to enable,
|
||||
* the forced link modes above are completely ignored.
|
||||
*/
|
||||
#define AUTONEG_DISABLE 0x00
|
||||
#define AUTONEG_ENABLE 0x01
|
||||
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
#define SPEED_10000 10000
|
||||
#define DUPLEX_HALF 0
|
||||
#define DUPLEX_FULL 1
|
||||
|
||||
#endif
|
||||
2323
sys/dev/cxgb/cxgb_sge.c
Normal file
2323
sys/dev/cxgb/cxgb_sge.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user