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Fix abuses of cpu_critical_{enter,exit} by converting to

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intr_{disable,restore} as well as providing an implemenation of
intr_{disable,restore}.
This commit is contained in:
Warner Losh 2002-03-21 06:14:58 +00:00
parent cb9a238a8a
commit b70c0e8b00
9 changed files with 61 additions and 48 deletions
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6
sys/alpha/alpha/db_interface.c
View File

@ -155,7 +155,7 @@ kdb_trap(a0, a1, a2, entry, regs)
db_regs_t *regs;
{
int ddb_mode = !(boothowto & RB_GDB);
critical_t s;
register_t s;
/*
* Don't bother checking for usermode, since a benign entry
@ -192,7 +192,7 @@ kdb_trap(a0, a1, a2, entry, regs)
ddb_regs = *regs;
s = cpu_critical_enter();
s = intr_disable();
#ifdef SMP
#ifdef DIAGNOSTIC
@ -219,7 +219,7 @@ kdb_trap(a0, a1, a2, entry, regs)
restart_cpus(stopped_cpus);
#endif
cpu_critical_exit(s);
intr_restore(s);
*regs = ddb_regs;

6
sys/alpha/alpha/interrupt.c
View File

@ -93,20 +93,20 @@ interrupt(a0, a1, a2, framep)
{
struct thread *td;
#ifdef SMP
critical_t s;
register_t s;
#endif
/*
* Find our per-cpu globals.
*/
#ifdef SMP
s = cpu_critical_enter();
s = intr_disable();
#endif
pcpup = (struct pcpu *) alpha_pal_rdval();
td = curthread;
#ifdef SMP
td->td_md.md_kernnest++;
cpu_critical_exit(s);
intr_restore(s);
#endif
atomic_add_int(&td->td_intr_nesting_level, 1);
#ifndef KSTACK_GUARD

24
sys/alpha/alpha/machdep.c
View File

@ -2020,13 +2020,13 @@ alpha_fpstate_check(struct thread *td)
* For SMP, we should check the fpcurthread of each cpu.
*/
#ifndef SMP
critical_t s;
register_t s;
s = cpu_critical_enter();
s = intr_disable();
if (td->td_pcb->pcb_hw.apcb_flags & ALPHA_PCB_FLAGS_FEN)
if (td != PCPU_GET(fpcurthread))
panic("alpha_check_fpcurthread: bogus");
cpu_critical_exit(s);
intr_restore(s);
#endif
}
@ -2046,9 +2046,9 @@ alpha_fpstate_check(struct thread *td)
void
alpha_fpstate_save(struct thread *td, int write)
{
critical_t s;
register_t s;
s = cpu_critical_enter();
s = intr_disable();
if (td != NULL && td == PCPU_GET(fpcurthread)) {
/*
* If curthread != fpcurthread, then we need to enable FEN
@ -2083,7 +2083,7 @@ alpha_fpstate_save(struct thread *td, int write)
alpha_pal_wrfen(0);
}
}
cpu_critical_exit(s);
intr_restore(s);
}
/*
@ -2094,9 +2094,9 @@ alpha_fpstate_save(struct thread *td, int write)
void
alpha_fpstate_drop(struct thread *td)
{
critical_t s;
register_t s;
s = cpu_critical_enter();
s = intr_disable();
if (td == PCPU_GET(fpcurthread)) {
if (td == curthread) {
/*
@ -2112,7 +2112,7 @@ alpha_fpstate_drop(struct thread *td)
}
PCPU_SET(fpcurthread, NULL);
}
cpu_critical_exit(s);
intr_restore(s);
}
/*
@ -2122,12 +2122,12 @@ alpha_fpstate_drop(struct thread *td)
void
alpha_fpstate_switch(struct thread *td)
{
critical_t s;
register_t s;
/*
* Enable FEN so that we can access the fp registers.
*/
s = cpu_critical_enter();
s = intr_disable();
alpha_pal_wrfen(1);
if (PCPU_GET(fpcurthread)) {
/*
@ -2154,7 +2154,7 @@ alpha_fpstate_switch(struct thread *td)
}
td->td_md.md_flags |= MDP_FPUSED;
cpu_critical_exit(s);
intr_restore(s);
}
/*

22
sys/alpha/alpha/prom.c
View File

@ -112,7 +112,7 @@ init_bootstrap_console()
promcnattach(alpha_console);
}
static critical_t enter_prom(void);
static register_t enter_prom(void);
static void leave_prom(critical_t);
@ -133,7 +133,7 @@ promcnputc(dev, c)
{
prom_return_t ret;
unsigned char *to = (unsigned char *)0x20000000;
critical_t s;
register_t s;
s = enter_prom(); /* critical_enter() and map prom */
*to = c;
@ -155,7 +155,7 @@ promcngetc(dev)
dev_t dev;
{
prom_return_t ret;
int s;
register_t s;
for (;;) {
s = enter_prom();
@ -176,7 +176,7 @@ promcncheckc(dev)
dev_t dev;
{
prom_return_t ret;
int s;
register_t s;
s = enter_prom();
ret.bits = prom_getc(alpha_console);
@ -187,13 +187,13 @@ promcncheckc(dev)
return (-1);
}
static critical_t
static register_t
enter_prom()
{
pt_entry_t *lev1map;
critical_t s;
register_t s;
s = cpu_critical_enter();
s = intr_disable();
if (!prom_mapped) {
#ifdef SIMOS
@ -220,7 +220,7 @@ enter_prom()
static void
leave_prom(s)
critical_t s;
register_t s;
{
pt_entry_t *lev1map;
@ -232,7 +232,7 @@ leave_prom(s)
lev1map[0] = saved_pte[0]; /* XXX */
prom_cache_sync(); /* XXX */
}
cpu_critical_exit(s);
intr_restore(s);
}
static void
@ -249,7 +249,7 @@ prom_getenv(id, buf, len)
{
unsigned char *to = (unsigned char *)0x20000000;
prom_return_t ret;
int s;
register_t s;
s = enter_prom();
ret.bits = prom_getenv_disp(id, to, len);
@ -272,7 +272,7 @@ prom_halt(halt)
/*
* Turn off interrupts, for sanity.
*/
cpu_critical_enter();
intr_disable();
/*
* Set "boot request" part of the CPU state depending on what

12
sys/alpha/alpha/trap.c
View File

@ -263,14 +263,14 @@ trap(a0, a1, a2, entry, framep)
u_int sticks;
int user;
#ifdef SMP
critical_t s;
register_t s;
#endif
/*
* Find our per-cpu globals.
*/
#ifdef SMP
s = cpu_critical_enter();
s = intr_disable();
#endif
pcpup = (struct pcpu *) alpha_pal_rdval();
td = curthread;
@ -280,7 +280,7 @@ trap(a0, a1, a2, entry, framep)
cpu_halt();
}
td->td_md.md_kernnest++;
cpu_critical_exit(s);
intr_restore(s);
#endif
p = td->td_proc;
@ -666,20 +666,20 @@ syscall(code, framep)
u_int64_t args[10]; /* XXX */
u_int hidden = 0, nargs;
#ifdef SMP
critical_t s;
register_t s;
#endif
/*
* Find our per-cpu globals.
*/
#ifdef SMP
s = cpu_critical_enter();
s = intr_disable();
#endif
pcpup = (struct pcpu *) alpha_pal_rdval();
td = curthread;
#ifdef SMP
td->td_md.md_kernnest++;
cpu_critical_exit(s);
intr_restore(s);
#endif
p = td->td_proc;

13
sys/alpha/include/cpufunc.h
View File

@ -59,6 +59,19 @@ cpu_critical_exit(critical_t ipl)
alpha_pal_swpipl(ipl);
}
static __inline register_t
intr_disable(void)
{
return (alpha_pal_swpipl(ALPHA_PSL_IPL_MCES));
}
static __inline void
intr_restore(register_t ipl)
{
alpha_pal_swpipl(ipl);
}
#endif /* _KERNEL */
#endif /* !_MACHINE_CPUFUNC_H_ */

12
sys/alpha/pci/cia.c
View File

@ -156,14 +156,14 @@ cia_swiz_set_hae_mem(void *arg, u_int32_t pa)
* Seems fairly paranoid but this is what Linux does...
*/
u_int32_t msb = pa & REG1;
critical_t s;
register_t s;
s = cpu_critical_enter();
s = intr_disable();
cia_hae_mem = (cia_hae_mem & ~REG1) | msb;
REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem;
alpha_mb();
cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
cpu_critical_exit(s);
intr_restore(s);
}
return pa & ~REG1;
}
@ -226,9 +226,9 @@ cia_sgmap_invalidate_pyxis(void)
volatile u_int64_t dummy;
u_int32_t ctrl;
int i;
critical_t s;
register_t s;
s = cpu_critical_enter();
s = intr_disable();
/*
* Put the Pyxis into PCI loopback mode.
@ -259,7 +259,7 @@ cia_sgmap_invalidate_pyxis(void)
REGVAL(CIA_CSR_CTRL) = ctrl;
alpha_mb();
cpu_critical_exit(s);
intr_restore(s);
}
static void

6
sys/alpha/pci/t2.c
View File

@ -110,7 +110,7 @@ static u_int32_t t2_hae_mem[2];
static u_int32_t
t2_set_hae_mem(void *arg, u_int32_t pa)
{
int s;
register_t s;
u_int32_t msb;
int hose;
@ -120,14 +120,14 @@ t2_set_hae_mem(void *arg, u_int32_t pa)
msb = pa & 0xf8000000;
pa -= msb;
msb >>= 27; /* t2 puts high bits in the bottom of the register */
s = cpu_critical_enter();
s = intr_disable();
if (msb != t2_hae_mem[hose]) {
t2_hae_mem[hose] = msb;
t2_csr[hose]->hae0_1 = t2_hae_mem[hose];
alpha_mb();
t2_hae_mem[hose] = t2_csr[hose]->hae0_1;
}
cpu_critical_exit(s);
intr_restore(s);
}
return pa;
}

8
sys/alpha/pci/t2_pci.c
View File

@ -92,7 +92,7 @@ t2_pcib_maxslots(device_t dev)
#define T2_TYPE1_SETUP(b,s,old_hae3) if((b)) { \
do { \
(s) = cpu_critical_enter(); \
(s) = intr_disable(); \
(old_hae3) = REGVAL(T2_HAE0_3); \
alpha_mb(); \
REGVAL(T2_HAE0_3) = (old_hae3) | (1<<30); \
@ -105,13 +105,13 @@ t2_pcib_maxslots(device_t dev)
alpha_mb(); \
REGVAL(T2_HAE0_3) = (old_hae3); \
alpha_mb(); \
cpu_critical_exit((s)); \
intr_restore((s)); \
} while(0); \
}
#define SWIZ_CFGREAD(b, s, f, r, width, type) do { \
type val = ~0; \
int ipl = 0; \
register_t ipl = 0; \
u_int32_t old_hae3 = 0; \
vm_offset_t off = T2_CFGOFF(b, s, f, r); \
vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF), off); \
@ -125,7 +125,7 @@ t2_pcib_maxslots(device_t dev)
} while (0)
#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) do { \
int ipl = 0; \
register_t ipl = 0; \
u_int32_t old_hae3 = 0; \
vm_offset_t off = T2_CFGOFF(b, s, f, r); \
vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF), off); \