Initialize the clocks before we call cninit() so that the serial
console so initialized will work upon return from cninit. While this is the very next line, other platforms setup all this stuff before calling cninit. Also, initialize the SDRAM base register in the inner block in at91_ramsize().
This commit is contained in:
Warner Losh
parent
198b3ad636
commit
b8b0747b3c
@ -209,12 +209,11 @@ const struct pmap_devmap at91_devmap[] = {
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long
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at91_ramsize(void)
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{
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uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
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uint32_t cr, mr;
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int banks, rows, cols, bw;
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if (at91_is_rm92()) {
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SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
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uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
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cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
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mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
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banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
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@ -222,9 +221,9 @@ at91_ramsize(void)
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cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
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bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
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} else {
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/* This should be good for the 9260, 9261 and 9G20 as addresses
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/* This should be good for the 9260, 9261, 9G20, 9G35 and 9X25 as addresses
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* and registers are the same */
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SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
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uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
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cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
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mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
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banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
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@ -361,12 +360,13 @@ initarm(void *arg, void *arg2)
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cpu_tlb_flushID();
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cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
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cninit();
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/* Initialize all the clocks, so that the console can work */
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at91_pmc_init_clock();
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at91_pmc_init_clock();
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/* Get chip id so device drivers know about differences */
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at91_chip_id = *(volatile uint32_t *)
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(AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
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at91_chip_id = *(uint32_t *)(AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
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cninit();
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memsize = board_init();
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physmem = memsize / PAGE_SIZE;
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@ -69,6 +69,11 @@ __FBSDID("$FreeBSD$");
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#define BBSZ 512
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/*
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* Note: This driver only supports the SlotA card. No attempt has been made
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* to support SlotB.
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*/
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struct at91_mci_softc {
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void *intrhand; /* Interrupt handle */
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device_t dev;
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@ -244,6 +249,13 @@ at91_mci_attach(device_t dev)
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sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
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sc->host.caps = 0;
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/*
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* The in-tree Linux driver doesn't allow 4-wire operation for the
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* at91rm9200, but does for other members of the family. The atmel
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* patches to this do allow it, or have in the past. It is unclear
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* that the hardware even works, but my boot loader uses 4-bit bus
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* in polling mode successfully.
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*/
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if (sc->sc_cap & CAP_HAS_4WIRE)
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sc->host.caps |= MMC_CAP_4_BIT_DATA;
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child = device_add_child(dev, "mmc", 0);
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@ -363,9 +375,9 @@ at91_mci_update_ios(device_t brdev, device_t reqdev)
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clkdiv = (at91_master_clock / ios->clock) / 2;
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}
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if (ios->bus_width == bus_width_4)
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WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
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WR4(sc, MCI_SDCR, MCI_SDCR_SDCBUS);
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else
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WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
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WR4(sc, MCI_SDCR, 0);
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WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
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/* Do we need a settle time here? */
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/* XXX We need to turn the device on/off here with a GPIO pin */
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@ -407,7 +419,9 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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if (!data) {
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// The no data case is fairly simple
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at91_mci_pdc_disable(sc);
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// printf("CMDR %x ARGR %x\n", cmdr, cmd->arg);
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#ifdef AT91_MCI_DEBUG
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printf("CMDR %x ARGR %x\n", cmdr, cmd->arg);
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#endif
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WR4(sc, MCI_ARGR, cmd->arg);
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WR4(sc, MCI_CMDR, cmdr);
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WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
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@ -479,7 +493,9 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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ier = MCI_SR_TXBUFE;
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}
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}
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// printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg);
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#ifdef AT91_MCI_DEBUG
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printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg);
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#endif
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WR4(sc, MCI_ARGR, cmd->arg);
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if (cmdr & MCI_CMDR_TRCMD_START) {
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if (cmdr & MCI_CMDR_TRDIR) {
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@ -518,6 +534,14 @@ at91_mci_start(struct at91_mci_softc *sc)
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sc->req = NULL;
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sc->curcmd = NULL;
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req->done(req);
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/*
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* Attempted hack-a-round for the DMA bug for multiple reads.
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*/
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if (req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) {
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at91_mci_fini(sc->dev);
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at91_mci_init(sc->dev);
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at91_mci_update_ios(sc->dev, NULL);
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}
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}
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static int
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@ -578,7 +602,9 @@ at91_mci_read_done(struct at91_mci_softc *sc)
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uint32_t *walker;
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struct mmc_command *cmd;
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int i, len;
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#ifdef AT91_MCI_DEBUG
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char *w2;
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#endif
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cmd = sc->curcmd;
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bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
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bus_dmamap_unload(sc->dmatag, sc->map);
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@ -589,6 +615,15 @@ at91_mci_read_done(struct at91_mci_softc *sc)
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for (i = 0; i < len; i++)
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walker[i] = bswap32(walker[i]);
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}
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#ifdef AT91_MCI_DEBUG
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printf("Read data\n");
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for (i = 0, w2 = cmd->data->data; i < cmd->data->len; i++) {
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if (i % 16 == 0)
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printf("%08x ", cmd->arg + i);
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printf("%02x%s", w2[i], (i + 1) % 16 ? " " : "\n");
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}
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printf("\n");
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#endif
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// Finish up the sequence...
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WR4(sc, MCI_IDR, MCI_SR_ENDRX);
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WR4(sc, MCI_IER, MCI_SR_RXBUFF);
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@ -624,14 +659,19 @@ at91_mci_intr(void *arg)
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if ((sr & MCI_SR_RCRCE) && (cmd->opcode == MMC_SEND_OP_COND ||
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cmd->opcode == ACMD_SD_SEND_OP_COND))
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cmd->error = MMC_ERR_NONE;
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else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE))
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else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE)) {
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printf("TIMEOUT %#x\n", sr);
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cmd->error = MMC_ERR_TIMEOUT;
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else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
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} else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE)) {
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printf("CRC %#x\n", sr);
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cmd->error = MMC_ERR_BADCRC;
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else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE))
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} else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE)) {
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printf("FIFO %#x\n", sr);
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cmd->error = MMC_ERR_FIFO;
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else
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} else {
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printf("FAILED %#x\n", sr);
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cmd->error = MMC_ERR_FAILED;
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}
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done = 1;
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if (sc->mapped && cmd->error) {
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bus_dmamap_unload(sc->dmatag, sc->map);
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@ -743,7 +783,7 @@ at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
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*(int *)result = sc->host.caps;
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break;
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case MMCBR_IVAR_MAX_DATA:
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*(int *)result = 1;
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*(int *)result = 1024;
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break;
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}
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return (0);
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@ -67,6 +67,7 @@
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#define AT91_CPU_SAM9XE128 0x329973a0
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#define AT91_CPU_SAM9XE256 0x329a93a0
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#define AT91_CPU_SAM9XE512 0x329aa3a0
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#define AT91_CPU_SAM9X25 0x819a05a0 /* Same as the SAM9G35 */
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#define AT91_ARCH(chipid) ((chipid >> 20) & 0xff)
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#define AT91_CPU(chipid) (chipid & ~AT91_CPU_VERSION_MASK)
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@ -399,6 +399,10 @@
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#define AT91RM92_OHCI_PA_BASE 0x00300000
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#define AT91RM92_OHCI_SIZE 0x00100000
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#define AT91RM92_FLS_BASE 0xdf000000
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#define AT91RM92_FLS_PA_BASE 0x10000000
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#define AT91RM92_FLS_SIZE 0x02000000 /* Support up to 32MB flash */
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#define AT91RM92_CF_BASE 0xdfd00000
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#define AT91RM92_CF_PA_BASE 0x51400000
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#define AT91RM92_CF_SIZE 0x00100000
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@ -25,13 +25,15 @@ dev/usb/controller/ohci_atmelarm.c optional ohci
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#
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# All the "systems on a chip" we support
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#
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arm/at91/at91sam9g20.c optional at91sam9g20
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arm/at91/at91sam9260.c optional at91sam9260
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arm/at91/at91sam9g20.c optional at91sam9g20
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arm/at91/at91sam9x25.c optional at91sam9x25
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#
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#
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# All the boards we support
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#
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arm/at91/board_ethernut5.c optional at91_board_ethernut5
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arm/at91/board_hl201.c optional at91_board_hl201
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arm/at91/board_sam9g20ek.c optional at91_board_sam9g20ek
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arm/at91/board_qila9g20.c optional at91_board_qila9g20
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arm/at91/board_sam9g20ek.c optional at91_board_sam9g20ek
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arm/at91/board_sam9x25ek.c optional at91_board_sam9x25ek
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@ -7,3 +7,4 @@ options PHYSADDR=0x20000000
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device at91sam9g20
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device at91sam9260
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device at91sam9x25
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