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Synchronize with sys/i386/i386/microtime.s revision 1.26.

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This commit is contained in:
KATO Takenori 1997-07-21 13:12:45 +00:00
parent 50902335e5
commit b8b1bfc496
1 changed files with 20 additions and 2 deletions
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22
sys/pc98/i386/microtime.s
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@ -32,7 +32,7 @@
* SUCH DAMAGE.
*
* from: Steve McCanne's microtime code
* $Id: microtime.s,v 1.11 1997/06/23 09:35:37 kato Exp $
* $Id: microtime.s,v 1.12 1997/07/20 11:56:48 kato Exp $
*/
#include "opt_cpu.h"
@ -40,7 +40,7 @@
#include <machine/asmacros.h>
#ifdef APIC_IO
#include <machine/smptests.h> /** APIC_PIN0_TIMER */
#include <machine/smptests.h> /** NEW STRATEGY, APIC_PIN0_TIMER */
#endif /* APIC_IO */
#include <i386/isa/icu.h>
@ -118,12 +118,21 @@ ENTRY(microtime)
movl _timer0_max_count, %edx /* prepare for 2 uses */
#ifdef APIC_IO
#ifdef NEW_STRATEGY
movl _ipending, %eax
testl %eax, _mask8254 /* is soft timer interrupt pending? */
#else /** NEW_STRATEGY */
#ifdef APIC_PIN0_TIMER
testl $IRQ0, _ipending /* is soft timer interrupt pending? */
#else
movl _ipending, %eax
testl %eax, _mask8254 /* is soft timer interrupt pending? */
#endif /* APIC_PIN0_TIMER */
#endif /** NEW_STRATEGY */
#else
testb $IRQ0, _ipending /* is soft timer interrupt pending? */
#endif /* APIC_IO */
@ -134,12 +143,21 @@ ENTRY(microtime)
jbe 1f
#ifdef APIC_IO
#ifdef NEW_STRATEGY
movl lapic_irr1, %eax /** XXX assumption: IRQ0-24 */
testl %eax, _mask8254 /* is hard timer interrupt pending? */
#else /** NEW_STRATEGY */
#ifdef APIC_PIN0_TIMER
testl $IRQ0, lapic_irr1
#else
movl lapic_irr1, %eax /** XXX assumption: IRQ0-24 */
testl %eax, _mask8254 /* is hard timer interrupt pending? */
#endif /* APIC_PIN0_TIMER */
#endif /** NEW_STRATEGY */
#else
inb $IO_ICU1, %al /* read IRR in ICU */
testb $IRQ0, %al /* is hard timer interrupt pending? */