MFp4: A bunch of patches from myself and Tisco to improve the
robustness of IIC transactions when parts aren't present. This also removes a bunch of debug. This also moves this driver to 7-1 addressing rather than 6-0 addressing, which is more inline with all the other iic drivers in the tree. I've tested this for about a million years on the systems at work.
This commit is contained in:
Warner Losh
parent
7409f6cd91
commit
bac394d579
@ -45,6 +45,10 @@ __FBSDID("$FreeBSD$");
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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#define TWI_SLOW_CLOCK 1500
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#define TWI_FAST_CLOCK 45000
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#define TWI_FASTEST_CLOCK 90000
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struct at91_twi_softc
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{
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device_t dev; /* Myself */
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@ -123,7 +127,7 @@ at91_twi_attach(device_t dev)
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AT91_TWI_LOCK_DESTROY(sc);
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goto out;
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}
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sc->cwgr = TWI_CWGR_CKDIV(8 * AT91C_MASTER_CLOCK / 90000) |
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sc->cwgr = TWI_CWGR_CKDIV(8 * AT91C_MASTER_CLOCK / TWI_FASTEST_CLOCK) |
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TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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@ -226,14 +230,13 @@ at91_twi_wait(struct at91_twi_softc *sc, uint32_t bit)
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int counter = 100000;
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uint32_t sr;
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while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0)
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while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 &&
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!(sr & TWI_SR_NACK))
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continue;
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if (counter <= 0)
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err = EBUSY;
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else if (sr & TWI_SR_NACK)
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err = EADDRNOTAVAIL;
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if (sr & ~bit)
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printf("status is %x\n", sr);
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err = ENXIO; // iic nack convention
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return (err);
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}
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@ -253,17 +256,17 @@ at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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*/
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switch (speed) {
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case IIC_SLOW:
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clk = 1500;
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clk = TWI_SLOW_CLOCK;
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break;
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case IIC_FAST:
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clk = 45000;
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clk = TWI_FAST_CLOCK;
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break;
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case IIC_UNKNOWN:
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case IIC_FASTEST:
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default:
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clk = 90000;
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clk = TWI_FASTEST_CLOCK;
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break;
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}
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sc->cwgr = TWI_CWGR_CKDIV(1) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(clk)) |
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@ -302,6 +305,7 @@ at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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int i, len, err;
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uint32_t rdwr;
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uint8_t *buf;
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uint32_t sr;
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sc = device_get_softc(dev);
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err = 0;
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@ -320,26 +324,36 @@ at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr);
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len = msgs[i].len;
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buf = msgs[i].buf;
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if (len != 0 && buf == NULL)
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return (EINVAL);
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WR4(sc, TWI_CR, TWI_CR_START);
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/* zero byte transfers aren't allowed */
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if (len == 0 || buf == NULL) {
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err = EINVAL;
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goto out;
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}
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if (len == 1)
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WR4(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP);
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else
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WR4(sc, TWI_CR, TWI_CR_START);
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if (msgs[i].flags & IIC_M_RD) {
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while (len--) {
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if (len == 0)
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WR4(sc, TWI_CR, TWI_CR_STOP);
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if ((err = at91_twi_wait(sc, TWI_SR_RXRDY)))
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goto out;
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*buf++ = RD4(sc, TWI_RHR) & 0xff;
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sr = RD4(sc, TWI_SR);
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while (!(sr & TWI_SR_TXCOMP)) {
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if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) {
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len--;
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*buf++ = RD4(sc, TWI_RHR) & 0xff;
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if (len == 0 && msgs[i].len != 1)
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WR4(sc, TWI_CR, TWI_CR_STOP);
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}
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}
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if (len > 0 || (sr & TWI_SR_NACK)) {
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err = ENXIO; // iic nack convention
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goto out;
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}
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} else {
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while (len--) {
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WR4(sc, TWI_THR, *buf++);
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if (len == 0)
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if (len == 0 && msgs[i].len != 1)
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WR4(sc, TWI_CR, TWI_CR_STOP);
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if ((err = at91_twi_wait(sc, TWI_SR_TXRDY))) {
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printf("Len %d\n", len);
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if ((err = at91_twi_wait(sc, TWI_SR_TXRDY)))
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goto out;
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}
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WR4(sc, TWI_THR, *buf++);
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}
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}
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if ((err = at91_twi_wait(sc, TWI_SR_TXCOMP)))
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@ -347,8 +361,9 @@ at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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}
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out:;
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if (err) {
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WR4(sc, TWI_CR, TWI_CR_STOP);
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printf("Err is %d\n", err);
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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}
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AT91_TWI_UNLOCK(sc);
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return (err);
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@ -56,7 +56,7 @@
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#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
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#define TWI_MMR_MWRITE 0U /* Master Read Direction */
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#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
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#define TWI_MMR_DADR(n) ((n) << 16) /* Device Address */
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#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */
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/* TWI_CWGR */
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#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
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