Update comments about setting PLLA and refernce the tables in the
datasheet that express the limits.
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@ -122,21 +122,30 @@ static const struct cpu_devs at91_devs[] =
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{ 0, 0, 0, 0, 0 }
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};
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/*
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* The following is unused currently since we don't ever set the PLLA
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* frequency of the device.
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*/
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static uint32_t
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at91_pll_outa(int freq)
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{
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uint32_t outa = 0;
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if (freq > 195000000)
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return (0x20000000);
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else
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return (0x20008000);
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/*
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* Set OUTA, per the data sheet. See Table 40-15 titled
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* PLLA Characteristics in the SAM9260 doc.
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*/
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if (freq > 155000000)
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outa = 2 << 14;
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return ((1 << 29) | outa);
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}
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static uint32_t
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at91_pll_outb(int freq)
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{
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return (0x4000);
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return (1 << 14);
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}
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static void
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@ -173,7 +182,7 @@ at91_clock_init(void)
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* to be near the optimal 2 MHz per datasheet. We know
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* we are going to be using this for the USB clock at 96 MHz.
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* Causes no extra frequency deviation for all recomended crystal
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* values.
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* values. See Note 1, table 40-16 SAM9260 doc.
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*/
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clk = at91_pmc_clock_ref("pllb");
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clk->pll_min_in = SAM9260_PLL_B_MIN_IN_FREQ; /* 1 MHz */
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