Additional features for the tsec(4) Ethernet driver.
- interrupt coalescing - polling - jumbo frames - multicast - VLAN tagging The enhanced version of the chip (eTSEC) can also take advantage of: - TCP/IP checksum calculation h/w offloading Obtained from: Freescale, Semihalf
This commit is contained in:
Rafal Jaworowski
parent
553bf6a453
commit
bd37530ee4
File diff suppressed because it is too large
Load Diff
@ -31,6 +31,17 @@
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#define TSEC_RX_NUM_DESC 256
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#define TSEC_TX_NUM_DESC 256
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/* Interrupt Coalescing types */
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#define TSEC_IC_RX 0
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#define TSEC_IC_TX 1
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/* eTSEC ID */
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#define TSEC_ETSEC_ID 0x0124
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/* Frame sizes */
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#define TSEC_MIN_FRAME_SIZE 64
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#define TSEC_MAX_FRAME_SIZE 9600
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struct tsec_softc {
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/* XXX MII bus requires that struct ifnet is first!!! */
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struct ifnet *tsec_ifp;
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@ -84,6 +95,7 @@ struct tsec_softc {
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int sc_error_irid;
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int tsec_if_flags;
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int is_etsec;
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/* Watchdog and MII tick related */
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struct callout tsec_callout;
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@ -106,6 +118,16 @@ struct tsec_softc {
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uint32_t tx_mbuf_used_get_cnt;
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uint32_t tx_mbuf_used_put_cnt;
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struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC];
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/* interrupt coalescing */
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struct mtx ic_lock;
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uint32_t rx_ic_time; /* RW, valid values 0..65535 */
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uint32_t rx_ic_count; /* RW, valid values 0..255 */
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uint32_t tx_ic_time;
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uint32_t tx_ic_count;
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/* currently received frame */
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struct mbuf *frame;
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};
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/* interface to get/put generic objects */
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@ -235,14 +257,23 @@ struct tsec_softc {
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#define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED)
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/* Lock for receiver */
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#define TSEC_RECEIVE_LOCK(sc) do { \
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mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->receive_lock); \
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#define TSEC_RECEIVE_LOCK(sc) do { \
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mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->receive_lock); \
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} while (0)
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#define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock)
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#define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED)
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/* Lock for interrupts coalescing */
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#define TSEC_IC_LOCK(sc) do { \
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mtx_assert(&(sc)->ic_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->ic_lock); \
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} while (0)
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#define TSEC_IC_UNLOCK(sc) mtx_unlock(&(sc)->ic_lock)
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#define TSEC_IC_LOCK_ASSERT(sc) mtx_assert(&(sc)->ic_lock, MA_OWNED)
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/* Global tsec lock (with all locks) */
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#define TSEC_GLOBAL_LOCK(sc) do { \
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if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \
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@ -273,14 +304,49 @@ struct tsec_softc {
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} while (0)
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struct tsec_desc {
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volatile uint16_t flags; /* descriptor flags */
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volatile uint16_t length; /* buffer length */
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volatile uint32_t bufptr; /* buffer pointer */
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volatile uint16_t flags; /* descriptor flags */
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volatile uint16_t length; /* buffer length */
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volatile uint32_t bufptr; /* buffer pointer */
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};
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#define TSEC_READ_RETRY 10000
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#define TSEC_READ_DELAY 100
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/* Structures and defines for TCP/IP Off-load */
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struct tsec_tx_fcb {
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volatile uint16_t flags;
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volatile uint8_t l4_offset;
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volatile uint8_t l3_offset;
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volatile uint16_t ph_chsum;
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volatile uint16_t vlan;
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};
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struct tsec_rx_fcb {
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volatile uint16_t flags;
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volatile uint8_t rq_index;
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volatile uint8_t protocol;
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volatile uint16_t unused;
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volatile uint16_t vlan;
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};
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#define TSEC_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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#define TSEC_TX_FCB_IP4 TSEC_TX_FCB_L3_IS_IP
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#define TSEC_TX_FCB_IP6 (TSEC_TX_FCB_L3_IS_IP | TSEC_TX_FCB_L3_IS_IP6)
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#define TSEC_TX_FCB_TCP TSEC_TX_FCB_L4_IS_TCP_UDP
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#define TSEC_TX_FCB_UDP (TSEC_TX_FCB_L4_IS_TCP_UDP | TSEC_TX_FCB_L4_IS_UDP)
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#define TSEC_RX_FCB_IP_CSUM_CHECKED(flags) \
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((flags & (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP6_FOUND | \
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TSEC_RX_FCB_IP_CSUM | TSEC_RX_FCB_PARSE_ERROR)) \
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== (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP_CSUM))
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#define TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) \
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((flags & (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM \
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| TSEC_RX_FCB_PARSE_ERROR)) \
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== (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM))
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/* Prototypes */
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extern devclass_t tsec_devclass;
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@ -134,15 +134,23 @@ tsec_ocp_probe(device_t dev)
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sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
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sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
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/* Check that we actually have a TSEC at this address */
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id = TSEC_READ(sc, TSEC_REG_ID) | TSEC_READ(sc, TSEC_REG_ID2);
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/* Check if we are eTSEC (enhanced TSEC) */
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id = TSEC_READ(sc, TSEC_REG_ID);
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sc->is_etsec = ((id >> 16) == TSEC_ETSEC_ID) ? 1 : 0;
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id |= TSEC_READ(sc, TSEC_REG_ID2);
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres);
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if (id == 0)
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if (id == 0) {
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device_printf(dev, "could not identify TSEC type\n");
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return (ENXIO);
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}
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if (sc->is_etsec)
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device_set_desc(dev, "Enhanced Three-Speed Ethernet Controller");
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else
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device_set_desc(dev, "Three-Speed Ethernet Controller");
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device_set_desc(dev, "Three-Speed Ethernet Controller");
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return (BUS_PROBE_DEFAULT);
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}
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@ -167,6 +175,8 @@ tsec_ocp_attach(device_t dev)
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MTX_DEF);
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mtx_init(&sc->receive_lock, device_get_nameunit(dev), "TSEC RX lock",
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MTX_DEF);
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mtx_init(&sc->ic_lock, device_get_nameunit(dev), "TSEC IC lock",
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MTX_DEF);
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/* Allocate IO memory for TSEC registers */
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sc->sc_rrid = 0;
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@ -300,6 +310,7 @@ tsec_ocp_detach(device_t dev)
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/* Destroy locks */
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mtx_destroy(&sc->receive_lock);
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mtx_destroy(&sc->transmit_lock);
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mtx_destroy(&sc->ic_lock);
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return (0);
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}
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@ -1,9 +1,8 @@
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/*-
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* Copyright (C) 2006-2007 Semihalf
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* Copyright (C) 2008-2009 Semihalf, Piotr Ziecik
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* Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
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* All rights reserved.
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*
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* Written by: Piotr Kruszynski <ppk@semihalf.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -12,8 +11,6 @@
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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@ -192,13 +189,15 @@
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#define TSEC_REG_GADDR5 0x894 /* Group address register 5 */
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#define TSEC_REG_GADDR6 0x898 /* Group address register 6 */
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#define TSEC_REG_GADDR7 0x89c /* Group address register 7 */
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#define TSEC_REG_IADDR(n) (TSEC_REG_IADDR0 + (n << 2))
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#define TSEC_REG_GADDR(n) (TSEC_REG_GADDR0 + (n << 2))
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/* TSEC attribute registers */
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#define TSEC_REG_ATTR 0xbf8 /* Attributes Register */
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#define TSEC_REG_ATTRELI 0xbfc /* Attributes EL & EI register */
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/* Size of TSEC registers area */
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#define TSEC_IO_SIZE 0x1000
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#define TSEC_IO_SIZE 0x1000
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/* reg bits */
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#define TSEC_FIFO_PAUSE_CTRL_EN 0x0002
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@ -210,10 +209,25 @@
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#define DMACTRL_WWR 0x00000002 /* Write with response */
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#define DMACTRL_WOP 0x00000001 /* Wait or poll */
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#define TSEC_RCTRL_VLEX 0x00002000 /* Enable automatic VLAN tag
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* extraction and deletion
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* from Ethernet frames */
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#define TSEC_RCTRL_IPCSEN 0x00000200 /* IP Checksum verification enable */
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#define TSEC_RCTRL_TUCSEN 0x00000100 /* TCP or UDP Checksum verification enable */
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#define TSEC_RCTRL_PRSDEP 0x000000C0 /* Parser control */
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#define TSEC_RCRTL_PRSFM 0x00000020 /* FIFO-mode parsing */
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#define TSEC_RCTRL_BC_REJ 0x00000010 /* Broadcast frame reject */
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#define TSEC_RCTRL_PROM 0x00000008 /* Promiscuous mode */
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#define TSEC_RCTRL_RSF 0x00000004 /* Receive short frame mode */
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#define TSEC_RCTRL_PRSDEP_PARSER_OFF 0x00000000 /* Parser Disabled */
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#define TSEC_RCTRL_PRSDEP_PARSE_L2 0x00000040 /* Parse L2 */
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#define TSEC_RCTRL_PRSDEP_PARSE_L23 0x00000080 /* Parse L2 and L3 */
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#define TSEC_RCTRL_PRSDEP_PARSE_L234 0x000000C0 /* Parse L2, L3 and L4 */
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#define TSEC_TCTRL_IPCSEN 0x00004000 /* IP header checksum generation enable */
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#define TSEC_TCTRL_TUCSEN 0x00002000 /* TCP/UDP header checksum generation enable */
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#define TSEC_TSTAT_THLT 0x80000000 /* Transmit halt */
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#define TSEC_RSTAT_QHLT 0x00800000 /* RxBD queue is halted */
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@ -325,6 +339,7 @@
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#define TSEC_TXBD_HFE 0x0080 /* Huge frame enable (written by user) */
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#define TSEC_TXBD_LC 0x0080 /* Late collision (written by TSEC) */
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#define TSEC_TXBD_RL 0x0040 /* Retransmission Limit */
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#define TSEC_TXBD_TOE 0x0002 /* TCP/IP Offload Enable */
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#define TSEC_TXBD_UN 0x0002 /* Underrun */
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#define TSEC_TXBD_TXTRUNC 0x0001 /* TX truncation */
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@ -351,5 +366,25 @@
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#define TSEC_TXBUFFER_ALIGNMENT 64
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#define TSEC_RXBUFFER_ALIGNMENT 64
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#define TSEC_DEFAULT_MAX_RX_BUFFER_SIZE 0x0600
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#define TSEC_DEFAULT_MIN_RX_BUFFER_SIZE 0x0040
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/* Transmit Path Off-Load Frame Control Block flags */
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#define TSEC_TX_FCB_VLAN 0x8000 /* VLAN control word valid */
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#define TSEC_TX_FCB_L3_IS_IP 0x4000 /* Layer 3 header is an IP header */
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#define TSEC_TX_FCB_L3_IS_IP6 0x2000 /* IP header is IP version 6 */
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#define TSEC_TX_FCB_L4_IS_TCP_UDP 0x1000 /* Layer 4 header is a TCP or UDP header */
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#define TSEC_TX_FCB_L4_IS_UDP 0x0800 /* UDP protocol at layer 4 */
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#define TSEC_TX_FCB_CSUM_IP 0x0400 /* Checksum IP header enable */
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#define TSEC_TX_FCB_CSUM_TCP_UDP 0x0200 /* Checksum TCP or UDP header enable */
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#define TSEC_TX_FCB_FLAG_NO_PH_CSUM 0x0100 /* Disable pseudo-header checksum */
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#define TSEC_TX_FCB_FLAG_PTP 0x0001 /* This is a PTP packet */
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/* Receive Path Off-Load Frame Control Block flags */
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#define TSEC_RX_FCB_VLAN 0x8000 /* VLAN tag recognized */
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#define TSEC_RX_FCB_IP_FOUND 0x4000 /* IP header found at layer 3 */
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#define TSEC_RX_FCB_IP6_FOUND 0x2000 /* IP version 6 header found at layer 3 */
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#define TSEC_RX_FCB_TCP_UDP_FOUND 0x1000 /* TCP or UDP header found at layer 4 */
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#define TSEC_RX_FCB_IP_CSUM 0x0800 /* IPv4 header checksum checked */
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#define TSEC_RX_FCB_TCP_UDP_CSUM 0x0400 /* TCP or UDP header checksum checked */
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#define TSEC_RX_FCB_IP_CSUM_ERROR 0x0200 /* IPv4 header checksum verification error */
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#define TSEC_RX_FCB_TCP_UDP_CSUM_ERROR 0x0100 /* TCP or UDP header checksum verification error */
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#define TSEC_RX_FCB_PARSE_ERROR 0x000C /* Parse error */
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@ -22,6 +22,8 @@ options BOOTP_WIRED_TO=tsec0
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options CD9660
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options COMPAT_43
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options DDB
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options DEVICE_POLLING
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options HZ=1000
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#options DIAGNOSTIC
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options FFS
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options GDB
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@ -72,3 +74,4 @@ device ugen
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#device uhci
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device umass
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device usb
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device vlan
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