ioat(4): Implement CRC and MOVECRC APIs
And document them in ioat.4. Sponsored by: EMC / Isilon Storage Division
This commit is contained in:
Conrad Meyer
parent
be3cbf60a5
commit
bec7ff798a
@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd January 14, 2016
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.Dd May 3, 2016
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.Dt IOAT 4
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.Os
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.Sh NAME
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@ -99,6 +99,29 @@ In
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.Fa "uint32_t flags"
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.Fc
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.Ft struct bus_dmadesc *
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.Fo ioat_copy_crc
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_addr_t dst"
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.Fa "bus_addr_t src"
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.Fa "bus_size_t len"
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.Fa "uint32_t *initialseed"
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.Fa "bus_addr_t crcptr"
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.Fa "bus_dmaengine_callback_t callback_fn"
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.Fa "void *callback_arg"
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.Fa "uint32_t flags"
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.Fc
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.Ft struct bus_dmadesc *
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.Fo ioat_crc
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_addr_t src"
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.Fa "bus_size_t len"
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.Fa "uint32_t *initialseed"
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.Fa "bus_addr_t crcptr"
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.Fa "bus_dmaengine_callback_t callback_fn"
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.Fa "void *callback_arg"
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.Fa "uint32_t flags"
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.Fc
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.Ft struct bus_dmadesc *
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.Fo ioat_blockfill
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_addr_t dst"
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@ -183,6 +206,43 @@ from.
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It is invalid to attempt to submit new DMA operations in a
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.Fa bus_dmaengine_callback_t
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context.
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.Pp
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The CRC operations have three distinct modes.
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The default mode is to accumulate.
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By accumulating over multiple descriptors, a user may gather a CRC over several
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chunks of memory and only write out the result once.
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.Pp
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The
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.Ar DMA_CRC_STORE
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flag causes the operation to emit the CRC32C result.
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If
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.Ar DMA_CRC_INLINE
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is set, the result is written inline with the destination data (or source in
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.Fn ioat_crc
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mode).
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If
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.Ar DMA_CRC_INLINE
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is not set, the result is written to the provided
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.Fa crcptr .
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.Pp
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Similarly, the
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.Ar DMA_CRC_TEST
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flag causes the operation to compare the CRC32C result to an existing checksum.
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If
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.Ar DMA_CRC_INLINE
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is set, the result is compared against the inline four bytes trailing the
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source data.
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If it is not set, the result is compared against the value pointed to by
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.Fa crcptr .
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.Pp
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.Fn ioat_copy_crc
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calculates a CRC32C while copying data.
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.Fn ioat_crc
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only computes a CRC32C of some data.
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If the
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.Fa initialseed
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argument to either routine is non-NULL, the CRC32C engine is initialized with
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the value it points to.
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.Sh USAGE
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A typical user will lookup the DMA engine object for a given channel with
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.Fn ioat_get_dmaengine .
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@ -199,9 +259,13 @@ If
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succeeds, there is guaranteed to be room for
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.Fa N
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new operations in the internal ring buffer.
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.Pp
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Then, they will submit one or more operations using
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.Fn ioat_blockfill ,
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.Fn ioat_copy ,
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.Fn ioat_copy_8k_aligned ,
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.Fn ioat_copy_crc ,
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.Fn ioat_crc ,
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or
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.Fn ioat_null .
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After queuing one or more individual DMA operations, they will
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@ -882,8 +882,8 @@ ioat_op_generic(struct ioat_softc *ioat, uint8_t op,
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mtx_assert(&ioat->submit_lock, MA_OWNED);
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KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x",
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flags & ~DMA_ALL_FLAGS));
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KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0,
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("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS));
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if ((flags & DMA_NO_WAIT) != 0)
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mflags = M_NOWAIT;
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else
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@ -1017,6 +1017,164 @@ ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
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return (&desc->bus_dmadesc);
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}
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struct bus_dmadesc *
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ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
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bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
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{
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struct ioat_crc32_hw_descriptor *hw_desc;
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struct ioat_descriptor *desc;
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struct ioat_softc *ioat;
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uint32_t teststore;
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uint8_t op;
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CTR0(KTR_IOAT, __func__);
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ioat = to_ioat_softc(dmaengine);
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if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) {
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ioat_log_message(0, "%s: Device lacks MOVECRC capability\n",
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__func__);
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return (NULL);
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}
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if (((src | dst) & (0xffffffull << 40)) != 0) {
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ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n",
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__func__);
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return (NULL);
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}
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teststore = (flags & _DMA_CRC_TESTSTORE);
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if (teststore == _DMA_CRC_TESTSTORE) {
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ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
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return (NULL);
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}
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if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
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ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
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__func__);
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return (NULL);
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}
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switch (teststore) {
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case DMA_CRC_STORE:
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op = IOAT_OP_MOVECRC_STORE;
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break;
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case DMA_CRC_TEST:
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op = IOAT_OP_MOVECRC_TEST;
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break;
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default:
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KASSERT(teststore == 0, ("bogus"));
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op = IOAT_OP_MOVECRC;
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break;
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}
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if ((flags & DMA_CRC_INLINE) == 0 &&
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(crcptr & (0xffffffull << 40)) != 0) {
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ioat_log_message(0,
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"%s: High 24 bits of crcptr invalid\n", __func__);
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return (NULL);
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}
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desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
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callback_arg, flags & ~_DMA_CRC_FLAGS);
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if (desc == NULL)
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return (NULL);
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hw_desc = desc->u.crc32;
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if ((flags & DMA_CRC_INLINE) == 0)
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hw_desc->crc_address = crcptr;
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else
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hw_desc->u.control.crc_location = 1;
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if (initialseed != NULL) {
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hw_desc->u.control.use_seed = 1;
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hw_desc->seed = *initialseed;
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}
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if (g_ioat_debug_level >= 3)
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dump_descriptor(hw_desc);
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ioat_submit_single(ioat);
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return (&desc->bus_dmadesc);
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}
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struct bus_dmadesc *
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ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
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uint32_t *initialseed, bus_addr_t crcptr,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
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{
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struct ioat_crc32_hw_descriptor *hw_desc;
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struct ioat_descriptor *desc;
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struct ioat_softc *ioat;
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uint32_t teststore;
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uint8_t op;
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CTR0(KTR_IOAT, __func__);
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ioat = to_ioat_softc(dmaengine);
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if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) {
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ioat_log_message(0, "%s: Device lacks CRC capability\n",
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__func__);
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return (NULL);
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}
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if ((src & (0xffffffull << 40)) != 0) {
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ioat_log_message(0, "%s: High 24 bits of src invalid\n",
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__func__);
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return (NULL);
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}
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teststore = (flags & _DMA_CRC_TESTSTORE);
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if (teststore == _DMA_CRC_TESTSTORE) {
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ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
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return (NULL);
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}
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if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
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ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
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__func__);
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return (NULL);
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}
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switch (teststore) {
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case DMA_CRC_STORE:
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op = IOAT_OP_CRC_STORE;
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break;
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case DMA_CRC_TEST:
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op = IOAT_OP_CRC_TEST;
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break;
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default:
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KASSERT(teststore == 0, ("bogus"));
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op = IOAT_OP_CRC;
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break;
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}
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if ((flags & DMA_CRC_INLINE) == 0 &&
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(crcptr & (0xffffffull << 40)) != 0) {
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ioat_log_message(0,
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"%s: High 24 bits of crcptr invalid\n", __func__);
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return (NULL);
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}
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desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
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callback_arg, flags & ~_DMA_CRC_FLAGS);
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if (desc == NULL)
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return (NULL);
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hw_desc = desc->u.crc32;
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if ((flags & DMA_CRC_INLINE) == 0)
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hw_desc->crc_address = crcptr;
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else
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hw_desc->u.control.crc_location = 1;
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if (initialseed != NULL) {
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hw_desc->u.control.use_seed = 1;
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hw_desc->seed = *initialseed;
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}
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if (g_ioat_debug_level >= 3)
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dump_descriptor(hw_desc);
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ioat_submit_single(ioat);
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return (&desc->bus_dmadesc);
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}
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struct bus_dmadesc *
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ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
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bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg,
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@ -52,7 +52,26 @@ __FBSDID("$FreeBSD$");
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* may be prefetched before operation 1 completes.
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*/
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#define DMA_FENCE 0x4
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#define DMA_ALL_FLAGS (DMA_INT_EN | DMA_NO_WAIT | DMA_FENCE)
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#define _DMA_GENERIC_FLAGS (DMA_INT_EN | DMA_NO_WAIT | DMA_FENCE)
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/*
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* Emit a CRC32C as the result of a ioat_copy_crc() or ioat_crc().
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*/
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#define DMA_CRC_STORE 0x8
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/*
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* Compare the CRC32C of a ioat_copy_crc() or ioat_crc() against an expeceted
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* value. It is invalid to specify both TEST and STORE.
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*/
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#define DMA_CRC_TEST 0x10
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#define _DMA_CRC_TESTSTORE (DMA_CRC_STORE | DMA_CRC_TEST)
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/*
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* Use an inline comparison CRC32C or emit an inline CRC32C result. Invalid
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* without one of STORE or TEST.
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*/
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#define DMA_CRC_INLINE 0x20
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#define _DMA_CRC_FLAGS (DMA_CRC_STORE | DMA_CRC_TEST | DMA_CRC_INLINE)
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/*
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* Hardware revision number. Different hardware revisions support different
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@ -151,6 +170,42 @@ struct bus_dmadesc *ioat_copy_8k_aligned(bus_dmaengine_t dmaengine,
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bus_addr_t dst1, bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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/*
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* Copy len bytes from dst to src, like ioat_copy().
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*
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* Additionally, accumulate a CRC32C of the data.
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*
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* If initialseed is not NULL, the value it points to is used to seed the
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* initial value of the CRC32C.
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*
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* If flags include DMA_CRC_STORE and not DMA_CRC_INLINE, crcptr is written
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* with the 32-bit CRC32C result (in wire format).
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*
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* If flags include DMA_CRC_TEST and not DMA_CRC_INLINE, the computed CRC32C is
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* compared with the 32-bit CRC32C pointed to by crcptr. If they do not match,
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* a channel error is raised.
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*
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* If the DMA_CRC_INLINE flag is set, crcptr is ignored and the DMA engine uses
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* the 4 bytes trailing the source data (TEST) or the destination data (STORE).
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*/
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struct bus_dmadesc *ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst,
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bus_addr_t src, bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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/*
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* ioat_crc() is nearly identical to ioat_copy_crc(), but does not actually
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* move data around.
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*
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* Like ioat_copy_crc, ioat_crc computes a CRC32C over len bytes pointed to by
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* src. The flags affect its operation in the same way, with one exception:
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*
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* If flags includes both DMA_CRC_STORE and DMA_CRC_INLINE, the computed CRC32C
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* is written to the 4 bytes trailing the *source* data.
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*/
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struct bus_dmadesc *ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src,
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bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
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bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
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/*
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* Issues a null operation. This issues the operation to the hardware, but the
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* hardware doesn't do anything with it.
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