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Mediatek/Ralink: Get our drivers closer to OpenWRT dts definitions

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This revision gets our Mediatek/Ralink drivers closer to OpenWRT's dts
definitions, so we can reuse them with less modifications later in order
to bring support for a lot of boards at once.

Approved by:	adrian (mentor)
Sponsored by:	Smartcom - Bulgaria AD
Differential Revision:	https://reviews.freebsd.org/D5961
This commit is contained in:
Stanislav Galabov 2016-04-15 15:24:42 +00:00
parent 913b41b84e
commit c1300b5e37
10 changed files with 46 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
sys/dev/rt/if_rt.c
View File

@ -99,13 +99,14 @@ __FBSDID("$FreeBSD$");
#ifdef FDT
/* more specific and new models should go first */
static const struct ofw_compat_data rt_compat_data[] = {
{ "ralink,rt3050-eth", RT_CHIPID_RT3050 },
{ "ralink,rt3352-eth", RT_CHIPID_RT3050 },
{ "ralink,rt3883-eth", RT_CHIPID_RT3050 },
{ "ralink,rt5350-eth", RT_CHIPID_RT5350 },
{ "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
{ "ralink,mt7621-eth", RT_CHIPID_MT7621 },
{ NULL, 0 }
{ "ralink,rt3050-eth", RT_CHIPID_RT3050 },
{ "ralink,rt3352-eth", RT_CHIPID_RT3050 },
{ "ralink,rt3883-eth", RT_CHIPID_RT3050 },
{ "ralink,rt5350-eth", RT_CHIPID_RT5350 },
{ "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
{ "ralink,mt7621-eth", RT_CHIPID_MT7621 },
{ "mediatek,mt7621-eth", RT_CHIPID_MT7621 },
{ NULL, 0 }
};
#endif

2
sys/mips/mediatek/mtk_ehci.c
View File

@ -78,7 +78,7 @@ ehci_fdt_probe(device_t self)
if (!ofw_bus_status_okay(self))
return (ENXIO);
if (!ofw_bus_is_compatible(self, "ralink,rt3xxx-ehci"))
if (!ofw_bus_is_compatible(self, "generic-ehci"))
return (ENXIO);
device_set_desc(self, EHCI_HC_DEVSTR);

4
sys/mips/mediatek/mtk_gpio_v1.c
View File

@ -281,8 +281,8 @@ mtk_gpio_attach(device_t dev)
sc->do_remap = 0;
}
if (OF_hasprop(node, "mtk,num-pins") && (OF_getencprop(node,
"mtk,num-pins", &num_pins, sizeof(num_pins)) >= 0))
if (OF_hasprop(node, "ralink,num-gpios") && (OF_getencprop(node,
"ralink,num-gpios", &num_pins, sizeof(num_pins)) >= 0))
sc->num_pins = num_pins;
else
sc->num_pins = MTK_GPIO_PINS;

6
sys/mips/mediatek/mtk_gpio_v2.c
View File

@ -121,8 +121,8 @@ static int mtk_gpio_intr(void *arg);
#define GPIO_PIORESET(_sc) GPIO_REG((_sc), 0x0040)
static struct ofw_compat_data compat_data[] = {
{ "mtk,mt7621-gpio", 1 },
{ "mtk,mt7628-gpio", 1 },
{ "mtk,mt7621-gpio-bank", 1 },
{ "mtk,mt7628-gpio-bank", 1 },
{ NULL, 0 }
};
@ -281,7 +281,7 @@ mtk_gpio_attach(device_t dev)
else
sc->num_pins = MTK_GPIO_PINS;
for (i = 0; i < num_pins; i++) {
for (i = 0; i < sc->num_pins; i++) {
sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
sc->pins[i].intr_polarity = INTR_POLARITY_HIGH;

4
sys/mips/mediatek/mtk_intr_gic.c
View File

@ -281,10 +281,10 @@ mtk_gic_map_intr(device_t dev, struct intr_map_data *data,
sc = device_get_softc(dev);
if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs)
data->fdt.ncells != 3 || data->fdt.cells[1] >= sc->nirqs)
return (EINVAL);
*isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[0]);
*isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[1]);
return (0);
#else
return (EINVAL);

2
sys/mips/mediatek/mtk_ohci.c
View File

@ -78,7 +78,7 @@ ohci_fdt_probe(device_t self)
if (!ofw_bus_status_okay(self))
return (ENXIO);
if (!ofw_bus_is_compatible(self, "ralink,rt3xxx-ohci"))
if (!ofw_bus_is_compatible(self, "generic-ohci"))
return (ENXIO);
device_set_desc(self, OHCI_HC_DEVSTR);

41
sys/mips/mediatek/mtk_pcie.c
View File

@ -99,7 +99,7 @@ struct mtk_pci_range {
u_long len;
};
#define FDT_RANGES_CELLS (3 * 2)
#define FDT_RANGES_CELLS ((1 + 2 + 3) * 2)
static void
mtk_pci_range_dump(struct mtk_pci_range *range)
@ -117,30 +117,33 @@ mtk_pci_ranges_decode(phandle_t node, struct mtk_pci_range *io_space,
{
struct mtk_pci_range *pci_space;
pcell_t ranges[FDT_RANGES_CELLS];
pcell_t addr_cells, size_cells, par_addr_cells;
pcell_t *rangesptr;
pcell_t cell0, cell1, cell2;
int tuples, i, rv, len;
int tuple_size, tuples, i, rv, len;
/*
* Retrieve 'ranges' property.
*/
if (!OF_hasprop(node, "ranges")) {
printf("%s: %d\n", __FUNCTION__, 1);
if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
return (EINVAL);
}
if (addr_cells != 3 || size_cells != 2)
return (ERANGE);
par_addr_cells = fdt_parent_addr_cells(node);
if (par_addr_cells != 1)
return (ERANGE);
len = OF_getproplen(node, "ranges");
if (len > sizeof(ranges)) {
printf("%s: %d\n", __FUNCTION__, 2);
if (len > sizeof(ranges))
return (ENOMEM);
}
if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) {
printf("%s: %d\n", __FUNCTION__, 3);
if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
return (EINVAL);
}
tuples = len / (sizeof(pcell_t) * 3);
tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
size_cells);
tuples = len / tuple_size;
/*
* Initialize the ranges so that we don't have to worry about
@ -159,18 +162,21 @@ mtk_pci_ranges_decode(phandle_t node, struct mtk_pci_range *io_space,
cell2 = fdt_data_get((void *)rangesptr, 1);
rangesptr++;
if (cell0 == 2) {
if (cell0 & 0x02000000) {
pci_space = mem_space;
} else if (cell0 == 1) {
} else if (cell0 & 0x01000000) {
pci_space = io_space;
} else {
rv = ERANGE;
printf("%s: %d\n", __FUNCTION__, 4);
goto out;
}
pci_space->base = cell1;
pci_space->len = cell2;
pci_space->base = fdt_data_get((void *)rangesptr,
par_addr_cells);
rangesptr += par_addr_cells;
pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
rangesptr += size_cells;
}
rv = 0;
@ -199,6 +205,7 @@ static struct ofw_compat_data compat_data[] = {
{ "ralink,rt3883-pcie", MTK_SOC_RT3883 },
{ "ralink,mt7620a-pcie", MTK_SOC_MT7620A },
{ "ralink,mt7621-pcie", MTK_SOC_MT7621 },
{ "mediatek,mt7621-pci", MTK_SOC_MT7621 },
{ "ralink,mt7628-pcie", MTK_SOC_MT7628 },
{ "ralink,mt7688-pcie", MTK_SOC_MT7628 },
{ NULL, MTK_SOC_UNKNOWN }

1
sys/mips/mediatek/mtk_soc.c
View File

@ -63,6 +63,7 @@ static const struct ofw_compat_data compat_data[] = {
{ "ralink,mtk7620a-soc", MTK_SOC_MT7620A },
{ "ralink,mtk7620n-soc", MTK_SOC_MT7620N },
{ "mediatek,mtk7621-soc", MTK_SOC_MT7621 },
{ "mediatek,mt7621-soc", MTK_SOC_MT7621 },
{ "ralink,mtk7621-soc", MTK_SOC_MT7621 },
{ "ralink,mtk7628an-soc", MTK_SOC_MT7628 },
{ "mediatek,mt7628an-soc", MTK_SOC_MT7628 },

5
sys/mips/mediatek/mtk_usb_phy.c
View File

@ -84,9 +84,10 @@ static void mtk_usb_phy_mt7621_init(device_t);
static void mtk_usb_phy_mt7628_init(device_t);
static struct ofw_compat_data compat_data[] = {
{ "ralink,mt7620a-usbphy", MTK_SOC_MT7620A },
{ "ralink,mt7620-usbphy", MTK_SOC_MT7620A },
{ "ralink,mt7628an-usbphy", MTK_SOC_MT7628 },
{ "ralink,rt3xxx-usbphy", MTK_SOC_RT3352 },
{ "ralink,rt3352-usbphy", MTK_SOC_RT3352 },
{ "ralink,rt3050-usbphy", MTK_SOC_RT3050 },
{ NULL, MTK_SOC_UNKNOWN }
};

2
sys/mips/mediatek/mtk_xhci.c
View File

@ -80,7 +80,7 @@ mtk_xhci_fdt_probe(device_t self)
if (!ofw_bus_status_okay(self))
return (ENXIO);
if (!ofw_bus_is_compatible(self, "mtk,usb-xhci"))
if (!ofw_bus_is_compatible(self, "mediatek,mt8173-xhci"))
return (ENXIO);
device_set_desc(self, XHCI_HC_DEVSTR);