From c1517c0df5c85e41c9490399a78009180643bf0c Mon Sep 17 00:00:00 2001 From: Oleksandr Tymoshenko Date: Thu, 28 Jan 2010 21:55:56 +0000 Subject: [PATCH] - Increase timeouts to 100 milliseconds, 1 millisecond is definitely not enough for PCI controller to get into shape Thanks to: adrian@ --- sys/mips/atheros/ar71xx_pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/mips/atheros/ar71xx_pci.c b/sys/mips/atheros/ar71xx_pci.c index 000860d904c5..d96f5a5c0c6c 100644 --- a/sys/mips/atheros/ar71xx_pci.c +++ b/sys/mips/atheros/ar71xx_pci.c @@ -297,12 +297,12 @@ ar71xx_pci_attach(device_t dev) reset |= (RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); ATH_WRITE_REG(AR71XX_RST_RESET, reset); ATH_READ_REG(AR71XX_RST_RESET); - DELAY(1000); + DELAY(100000); reset &= ~(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); ATH_WRITE_REG(AR71XX_RST_RESET, reset); ATH_READ_REG(AR71XX_RST_RESET); - DELAY(1000); + DELAY(100000); /* Init PCI windows */ ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR); @@ -313,7 +313,7 @@ ar71xx_pci_attach(device_t dev) ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR); ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR); ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR); - DELAY(1000); + DELAY(100000); ar71xx_pci_check_bus_error();