aic7xxx.c:
Correct the BUILD_TCL macro. It was placing the target id in the wrong bits. This was only an issue for adapters that do not perform SCB paging (aha-3940AUW for instance). Don't bother inlining ahc_index_busy_tcl. It is never used in a performance critical path and is a bit chunky. Correct ahc_index_busy_tcl to deal with "busy target tables" embedded in the latter half of 64byte SCBs. Don't initialize the busy target table to its empty state until after we have finished extracting configuration information from chip SRAM. In the common case of using 16 bytes of chip SRAM to do untagged target lookups, we were trashing the last 8 targets configuration data. (actually only target 8 because of the bug in the BUILD_TCL macro). Cram the "bus reset delivered" message back under bootverbose. Fix the cleanup of the SCB busy target table when aborting commands. If the lun is wildcarded, we must loop through all possible luns. aic7xxx.h: Only bother supporting 64 luns right now. It doesn't seem like either this driver or any peripherals will be doing information unit transfers (where the lun number is a 32 bit integer) any time soon. aic7xxx.seq: Fix support for the aic7895. We must flush the data FIFO if performing a manual transfer that is not a multiple of 8 bytes. We were doing this quite regularly for embedded cdbs. Manaually flush the fifo on earlier adapters when dealing with embedded cdbs too. We were stuffing the FIFO with 16 bytes instead, but triggering the flush is more efficient and allows us to remove two instructions from the "copy_to_fifo" routine.
This commit is contained in:
Justin T. Gibbs
parent
fbf29924ba
commit
c27eebfde8
@ -168,8 +168,10 @@
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(0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
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#define TCL_TARGET_OFFSET(tcl) \
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((((tcl) >> 4) & TID) >> 4)
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#define TCL_LUN(tcl) \
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(tcl & (AHC_NUM_LUNS - 1))
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#define BUILD_TCL(scsiid, lun) \
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((lun) | (((scsiid) & TID) >> 4))
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((lun) | (((scsiid) & TID) << 4))
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#define BUILD_SCSIID(ahc, sim, target_id, our_id) \
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((((target_id) << TID_SHIFT) & TID) | (our_id) \
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| (SIM_IS_SCSIBUS_B(ahc, sim) ? TWIN_CHNLB : 0))
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@ -394,8 +396,8 @@ static void ahc_queue_lstate_event(struct ahc_softc *ahc,
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u_int event_arg);
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static void ahc_send_lstate_events(struct ahc_softc *ahc,
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struct tmode_lstate *lstate);
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static void restart_sequencer(struct ahc_softc *ahc);
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static __inline u_int ahc_index_busy_tcl(struct ahc_softc *ahc,
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static void restart_sequencer(struct ahc_softc *ahc);
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static u_int ahc_index_busy_tcl(struct ahc_softc *ahc,
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u_int tcl, int unbusy);
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static __inline void ahc_freeze_ccb(union ccb* ccb);
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@ -468,16 +470,29 @@ restart_sequencer(struct ahc_softc *ahc)
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unpause_sequencer(ahc);
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}
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static __inline u_int
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static u_int
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ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy)
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{
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u_int scbid;
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u_int target_offset;
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target_offset = TCL_TARGET_OFFSET(tcl);
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scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
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if (unbusy)
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ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
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if ((ahc->features & AHC_SCB_BTT) != 0) {
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u_int saved_scbptr;
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saved_scbptr = ahc_inb(ahc, SCBPTR);
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ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
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scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
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if (unbusy)
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ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl),
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SCB_LIST_NULL);
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ahc_outb(ahc, SCBPTR, saved_scbptr);
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} else {
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target_offset = TCL_TARGET_OFFSET(tcl);
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scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
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if (unbusy)
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ahc_outb(ahc, BUSY_TARGETS + target_offset,
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SCB_LIST_NULL);
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}
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return (scbid);
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}
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@ -1199,10 +1214,10 @@ ahc_reset(struct ahc_softc *ahc)
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* not, STPWEN will be false (the value after a POST)
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* and this action will be harmless.
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*
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* We must actually always initialize STPWEN to 1
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* before we restore the saved value. STPWEN is
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* initialized to a tri-state condition which is
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* only be cleared by turning it on.
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* We must always initialize STPWEN to 1 before we
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* restore the saved value. STPWEN is initialized
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* to a tri-state condition which is only be cleared
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* by turning it on.
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*/
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ahc_outb(ahc, SXFRCTL1, sxfrctl1|STPWEN);
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ahc_outb(ahc, SXFRCTL1, sxfrctl1);
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@ -4518,23 +4533,6 @@ ahc_init(struct ahc_softc *ahc)
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if (ahcinitscbdata(ahc) != 0)
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return (ENOMEM);
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/* There are no untagged SCBs active yet. */
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/* XXX will need to change for SCB ram approach */
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for (i = 0; i < 16; i++)
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ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, 0), /*unbusy*/TRUE);
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/* All of our queues are empty */
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for (i = 0; i < 256; i++)
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ahc->qoutfifo[i] = SCB_LIST_NULL;
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for (i = 0; i < 256; i++)
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ahc->qinfifo[i] = SCB_LIST_NULL;
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if ((ahc->features & AHC_MULTI_TID) != 0) {
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ahc_outb(ahc, TARGID, 0);
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ahc_outb(ahc, TARGID + 1, 0);
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}
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/*
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* Allocate a tstate to house information for our
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* initiator presence on the bus as well as the user
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@ -4747,6 +4745,36 @@ ahc_init(struct ahc_softc *ahc)
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ahc->user_discenable = discenable;
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ahc->user_tagenable = tagenable;
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/* There are no untagged SCBs active yet. */
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for (i = 0; i < 16; i++) {
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ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, 0), /*unbusy*/TRUE);
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if ((ahc->features & AHC_SCB_BTT) != 0) {
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int lun;
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/*
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* The SCB based BTT allows an entry per
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* target and lun pair.
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*/
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for (lun = 1; lun < AHC_NUM_LUNS; lun++) {
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ahc_index_busy_tcl(ahc,
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BUILD_TCL(i << 4, lun),
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/*unbusy*/TRUE);
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}
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}
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}
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/* All of our queues are empty */
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for (i = 0; i < 256; i++)
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ahc->qoutfifo[i] = SCB_LIST_NULL;
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for (i = 0; i < 256; i++)
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ahc->qinfifo[i] = SCB_LIST_NULL;
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if ((ahc->features & AHC_MULTI_TID) != 0) {
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ahc_outb(ahc, TARGID, 0);
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ahc_outb(ahc, TARGID + 1, 0);
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}
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/*
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* Tell the sequencer where it can find our arrays in memory.
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*/
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@ -5320,7 +5348,7 @@ ahc_action(struct cam_sim *sim, union ccb *ccb)
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found = ahc_reset_channel(ahc, SIM_CHANNEL(ahc, sim),
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/*initiate reset*/TRUE);
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splx(s);
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if (1 || bootverbose) {
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if (bootverbose) {
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xpt_print_path(SIM_PATH(ahc, sim));
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printf("SCSI bus reset delivered. "
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"%d SCBs aborted.\n", found);
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@ -6577,14 +6605,36 @@ ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
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for (;i < maxtarget; i++) {
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u_int scbid;
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/* XXX Will need lun loop for SCB ram version */
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scbid = ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, 0),
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/*unbusy*/FALSE);
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scbp = &ahc->scb_data->scbarray[scbid];
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if (scbid < ahc->scb_data->numscbs
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&& ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))
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ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, 0),
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/*unbusy*/TRUE);
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&& ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
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u_int minlun;
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u_int maxlun;
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if (lun == CAM_LUN_WILDCARD) {
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/*
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* Unless we are using an SCB based
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* busy targets table, there is only
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* one table entry for all luns of
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* a target.
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*/
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minlun = 0;
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maxlun = 1;
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if ((ahc->flags & AHC_SCB_BTT) != 0)
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maxlun = AHC_NUM_LUNS;
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} else {
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minlun = lun;
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maxlun = lun + 1;
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}
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while (minlun < maxlun) {
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ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4,
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minlun), /*unbusy*/TRUE);
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minlun++;
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}
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}
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}
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/*
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@ -56,12 +56,9 @@
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/*
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* The maximum number of supported luns.
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* Although the identify message only supports 64 luns in SPI3, you
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* can have 2^64 luns when information unit transfers are enabled.
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* The max we can do sanely given the 8bit nature of the RISC engine
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* on these chips is 256.
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* The identify message supports up to 64 luns in SPI3.
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*/
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#define AHC_NUM_LUNS 256
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#define AHC_NUM_LUNS 64
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/*
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* The maximum transfer per S/G segment.
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@ -1112,13 +1112,13 @@ p_command_embedded:
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}
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if ((ahc->features & AHC_CMD_CHAN) != 0) {
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bmov DFDAT, SCB_CDB_STORE, 12;
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if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
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or DFCNTRL, FIFOFLUSH;
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}
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} else {
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/*
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* At most 12 bytes, but we copy 16 to fill
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* the 64bit words in the FIFO
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*/
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call copy_to_fifo_8;
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call copy_to_fifo_8;
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call copy_to_fifo_6;
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call copy_to_fifo_6;
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or DFCNTRL, FIFOFLUSH;
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}
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p_command_loop:
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test SSTAT0, SDONE jnz . + 2;
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@ -1849,10 +1849,6 @@ dfdat_in_2_continued:
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mov DINDIR,DFDAT ret;
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}
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copy_to_fifo_8:
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mov DFDAT,SINDIR;
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copy_to_fifo_7:
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mov DFDAT,SINDIR;
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copy_to_fifo_6:
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mov DFDAT,SINDIR;
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copy_to_fifo_5:
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